CN112992261A - Memory test system - Google Patents
Memory test system Download PDFInfo
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- CN112992261A CN112992261A CN201911304012.2A CN201911304012A CN112992261A CN 112992261 A CN112992261 A CN 112992261A CN 201911304012 A CN201911304012 A CN 201911304012A CN 112992261 A CN112992261 A CN 112992261A
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- 238000012360 testing method Methods 0.000 title claims abstract description 203
- 230000015654 memory Effects 0.000 title claims abstract description 155
- 238000004891 communication Methods 0.000 claims abstract description 18
- 238000012545 processing Methods 0.000 claims abstract description 11
- 230000006870 function Effects 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
The invention provides a memory test system, comprising: the test mainboard is provided with a memory slot for inserting a memory to be tested; the central processing unit is arranged on the test mainboard; the current test module is connected with the memory slot and used for measuring the working current of the memory to be tested; and the test control module is in communication connection with the test mainboard and the current test module and is used for controlling the test mainboard to enter a BIOS setting page so as to set test parameters of the memory to be tested, controlling the central processing unit on the test mainboard to run memory test software after controlling the test mainboard to be started up so as to test the memory to be tested through the test parameters and controlling the current test module to obtain the working current of the memory to be tested. The invention can effectively modify the test parameters of the memory to be tested, is simple and universal, has wide coverage and can further improve the yield of the memory to be tested.
Description
Technical Field
The disclosed embodiments of the present invention relate to the field of computers, and more particularly, to a memory test system.
Background
At present, memories include a UDIMM (desktop memory), a sodim (notebook memory), and the like, and various manufacturing defects exist in production, and generally, production tests are performed on the memories after production so as to screen out defective products.
At present, most memory products are applied to x86 compatible machines, and therefore, a mode of an x86 motherboard matching memory test software is usually used for testing the memory products, the memory test software is software which can run in an x86 CPU 120, but only the memory test software is used, and the memory voltage, the time sequence, the frequency and the like can be modified from the motherboard BIOS code, so that the memory voltage, the time sequence, the frequency and the like of an x86 platform cannot be effectively modified, and the current value of the memory during working cannot be measured, and the coverage is narrow.
Disclosure of Invention
According to an embodiment of the present invention, a memory test system is provided to solve the above problems.
According to an aspect of the present invention, an exemplary memory test system is disclosed, comprising: the test mainboard is provided with a memory slot for inserting a memory to be tested; the central processing unit is arranged on the test mainboard; the current test module is connected with the memory slot and used for measuring the working current of the memory to be tested; and the test control module is in communication connection with the test mainboard and the current test module and is used for controlling the test mainboard to enter a BIOS setting page so as to set test parameters of the memory to be tested, controlling the central processing unit on the test mainboard to run memory test software after controlling the test mainboard to be started up so as to test the memory to be tested through the test parameters and controlling the current test module to obtain the working current of the memory to be tested.
In some embodiments, the test control module includes a memory and a controller, wherein the memory is communicatively coupled to the controller, and the memory has memory test software stored therein; the controller is in communication connection with the test mainboard through a USB interface.
In some embodiments, the controller is configured to simulate functions of a USB keyboard and a mouse, so as to control the test motherboard to enter a BIOS setting page through the USB keyboard and the mouse, so as to set test parameters of the memory to be tested; the controller is used for simulating the function of a USB flash disk through the memory, controlling the central processing unit on the test mainboard to run the memory test software through the USB flash disk, and testing the memory to be tested through the test parameters.
In some embodiments, the controller is configured to simulate a function of a usb disk through the memory, so as to control the central processing unit on the test motherboard to run different memory test software at different test stages through the usb disk.
In some embodiments, the current test module comprises: the adapter plate is inserted into the memory slot; and the current acquisition circuit is arranged on the adapter plate, is electrically connected with the memory to be tested and is in communication connection with the controller through a CAN interface or a UART interface.
In some embodiments, the memory device further includes a temperature control module, wherein the temperature control module includes a temperature control circuit and a high temperature cover electrically connected to the temperature control circuit, wherein the temperature control circuit is in communication connection with the controller through a CAN interface or a UART interface, and the high temperature cover is disposed on the memory to be tested, so that the memory to be tested is located in the high temperature cover.
In some embodiments, the test motherboard is further communicatively connected to the controller through a UART interface, so as to send a test result obtained by testing the memory to be tested through the test parameters to the controller.
In some embodiments, the controller is communicatively connected to the test motherboard through a GPIO interface to control the test motherboard to power on, reset, and power off.
In some embodiments, the test parameters include an operating timing, an operating voltage, and an operating frequency of the memory under test.
In some embodiments, a CPU slot is disposed on the test motherboard, wherein the CPU is inserted into the CPU slot, and the CPU slot and the memory slot are located on the same surface of the test motherboard.
The invention has the following beneficial effects: through the test control module, the test mainboard is controlled to enter a BIOS setting page to set test parameters of the memory to be tested, and after the test mainboard is controlled to be started, the CPU of the test mainboard is controlled to run memory test software to test the memory to be tested through the test parameters, so that the test parameters of the memory to be tested are effectively set, the test parameters of the memory to be tested are effectively modified, the test control module is simple and universal, the coverage is wide, the current in the process of testing the memory to be tested is collected through the current test module, and the yield of the memory to be tested is further improved.
Drawings
The invention will be further described with reference to the accompanying drawings and embodiments, in which:
fig. 1 is a schematic structural diagram of a memory test system according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a memory test system according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution of the present invention is further described in detail below with reference to the accompanying drawings and the detailed description.
Fig. 1 is a schematic structural diagram of a memory test system according to an embodiment of the present invention. The memory test system 100 includes a test motherboard 110, a Central Processing Unit (CPU) 120, a current test module 130, and a test control module 140.
The test motherboard 110 is provided with a memory slot 111 for inserting a memory to be tested. The test motherboard 110 may be an x86 motherboard. The Memory to be tested may be a Dual-Inline-Memory-Modules (DIMM), such as a UDIMM (desktop Memory), a sodim (notebook Memory), and the like. DIMMs may include DDRs (Double Data Rate, Double Data synchronous dynamic random access memory), such as DDR3 and DDR 4.
The CPU 120 is disposed on the test motherboard 110, and the CPU 120 is configured to run a memory test software to test a memory to be tested.
The current test module 130 is communicatively connected to the memory under test. The current test module 130 is used for measuring the working current of the memory to be tested.
The test control module 140 is communicatively connected to the test motherboard 110 and the current test module 130. The test control module 140 is configured to control the test motherboard 110 to enter a BIOS setting page to set a test parameter of the memory to be tested, and after controlling the test motherboard 110 to start up, control the CPU 120 on the test motherboard 110 to run memory test software, so as to test the memory to be tested according to the test parameter, and control the current test module 130 to obtain a working current of the memory to be tested.
In one example, the test parameters of the memory under test include an operating timing, an operating voltage, and an operating frequency of the memory under test.
In this embodiment, through the test control module 140, the test main board 110 is controlled to enter the BIOS setting page to set the test parameters of the memory to be tested, and after the test main board 110 is controlled to start, the CPU 120 on the test main board 110 is controlled to run the memory test software, so as to test the memory to be tested through the test parameters, and effectively set the test parameters of the memory to be tested, thereby effectively modifying the test parameters of the memory to be tested, which is simple and general, and has a wide coverage, and through the current test module 130, the current during testing the memory to be tested is collected, so as to further improve the yield of the memory to be tested.
In some embodiments, as shown in FIG. 2, the test control module 140 includes a memory 142 and a controller 141, wherein the memory 142 is communicatively coupled to the controller 141, and the memory test software is stored in the memory 142.
The controller 141 is communicatively connected to the test motherboard 110 via a USB (Universal Serial Bus) interface 1 b. Specifically, the controller 141 includes a USB interface 1b, the test motherboard 110 includes a USB interface 1b, and the USB interface 1b of the controller 141 is connected to the USB interface 1b of the test motherboard 110, so that the controller 141 is communicatively connected to the test motherboard 110 through the USB interface 1 b.
The controller 141 is used for simulating the functions of the USB keyboard and the mouse, so as to control the test motherboard 110 to enter the BIOS setting page through the USB keyboard and the mouse, so as to set the test parameters of the memory to be tested. The controller 141 simulates the functions of the USB keyboard and the mouse through the communication protocol of the keyboard and the mouse, so that the controller 141 can be used as the USB keyboard and the mouse, and further controls the test motherboard 110 to enter the BIOS setting page through the USB keyboard and the mouse, and further sets the test parameters of the memory to be tested on the BIOS setting page.
The controller 141 is configured to simulate a function of the usb disk through the memory 142, so as to control the test motherboard 110 to run the memory test software through the usb disk, and test the memory to be tested through the test parameters. The controller 141 simulates the function of the usb disk through the communication protocol of the usb disk, so that the controller 141 can use the memory 142 as the usb disk, and further, the CPU 120 on the test motherboard 110 runs the memory test software under the guidance of the usb disk, and tests the memory to be tested through the test parameters. In an example, the controller 141 is configured to simulate the function of a usb disk via the storage 142, so as to control the CPU 120 on the test motherboard 110 to run different memory test software at different test stages via the usb disk. Therefore, different tests on the memory to be tested at different test stages are realized.
In this embodiment, the test control module 140 simulates functions of a USB keyboard, a mouse, and a USB disk, so as to effectively set test parameters of the memory to be tested, and test the memory to be tested according to the test parameters, which is simple and universal.
In some embodiments, as shown in fig. 2, the current test module 130 includes an interposer 131 and a current collection circuit 132. The interposer 131 is inserted into the memory slot 111. The current collecting circuit 132 is disposed on the adapter plate 131 and is in communication connection with the memory to be tested. In one example, as shown in fig. 2, the current collection circuit 132 is communicatively connected to the Controller 141 via a CAN (Controller Area Network) interface 1 a. In an example, the adapter board 131 is connected to the memory to be tested, and when the memory to be tested is connected to the adapter board 131, the current collection circuit 132 on the adapter board 131 is electrically connected to the pins of the memory to be tested, so that the current collection circuit 132 can collect the working current of the memory to be tested. The current collection circuit 132 is in communication connection with the controller 141 through the CAN interface 1a, the controller 141 sends a current collection instruction to the current collection circuit 132 through the CAN interface 1a, the current collection circuit 132 responds to the current collection instruction, the collected working current of the memory to be tested is returned to the controller 141, and then the controller 141 obtains the working current of the memory to be tested, which is collected by the current collection circuit 132. Specifically, the adapter plate 131 is provided with a CAN interface 1a, the controller 141 includes the CAN interface 1a, and the CAN interface 1a of the controller 141 is connected to the CAN interface 1a of the adapter plate 131, so that the current collection circuit 132 is in communication connection with the controller 141 through the CAN interface 1 a. In other examples, the current collection circuit 132 may also be communicatively coupled to the controller 141 via a UART (Universal Asynchronous Receiver/Transmitter) interface.
In some embodiments, as shown in fig. 2, the memory test system 100 further includes a temperature control module 150, wherein the temperature control module 150 includes a temperature control circuit 151 and a high temperature enclosure 152 electrically connected to the temperature control circuit 151. In an example, as shown in fig. 2, the temperature control circuit 151 is communicatively connected to the controller 141 through the CAN interface 1a, and the high temperature enclosure 152 is disposed on the memory to be tested, so that the memory to be tested is located in the high temperature enclosure 152. In other examples, temperature control circuitry 151 may also be communicatively coupled to control 141 via a UART interface.
The controller 141 sends a temperature setting instruction to the temperature control circuit 151, and the temperature control circuit 151 receives the temperature setting instruction of the controller 141, and controls the high temperature cover 152 to heat up or stop heating up, so that the memory to be tested is at a corresponding temperature, and further, the memory to be tested is tested at the corresponding temperature, and the test of the working temperature of the memory to be tested is realized. When testing the memory to be tested, the temperature of the memory to be tested may be 85 degrees or 65 degrees. In one example, a heating wire and a temperature sensor are disposed within the high temperature enclosure 152, wherein the heating wire and the temperature sensor are electrically connected to the temperature control circuit 151, respectively. The temperature control circuit 151 receives a temperature setting instruction of the controller 141, controls the heating wires in the high temperature enclosure 152 to heat, so that the high temperature enclosure 152 is heated, feeds back the temperature in the high temperature enclosure 152 through the temperature sensor, and controls the heating wires in the high temperature enclosure 152 to stop heating when the temperature in the high temperature enclosure 152 reaches a corresponding temperature, so that the high temperature enclosure 152 keeps the corresponding temperature.
In some embodiments, as shown in fig. 2, the test motherboard 110 is further communicatively connected to the controller 141 through a UART (Universal Asynchronous Receiver/Transmitter) interface 1c, so as to send a test result obtained by testing the memory to be tested according to the test parameters to the controller 141. Specifically, the controller 141 includes a UART interface 1c, the test motherboard 110 includes the UART interface 1c, and the UART interface 1c of the controller 141 is connected to the UART interface 1c of the test motherboard 110, so that the controller 141 is communicatively connected to the test motherboard 110 through the UART interface 1 c.
In some embodiments, as shown in fig. 2, the controller 141 is communicatively connected to the test motherboard 110 through a GPIO (General-purpose input/output) interface 1d to control the test motherboard 110 to be powered on, reset, and powered off. Specifically, the controller 141 includes a GPIO interface 1d, the test motherboard 110 includes the GPIO interface 1d, and the UART interface 1c of the controller 141 is connected to the GPIO interface 1d of the test motherboard 110, so that the controller 141 is communicatively connected to the test motherboard 110 through the GPIO interface 1 d.
In some embodiments, as shown in fig. 2, controller 141 also includes an ethernet interface 1 f. The external device is communicatively connected to the controller 141 through the ethernet interface 1f, and the external device may transmit relevant information, for example, a start test instruction, to the controller 141.
It should be noted that the controller 141 is in communication connection with the test motherboard 110, the current collection circuit 132, the temperature control circuit 151, an external device, and the like through different interfaces, and a communication module is provided in the controller 141, or the controller 141 communicates with the test motherboard 110, the current collection circuit 132, the temperature control circuit 151, an external device, and the like through an external communication module and its corresponding interface.
In some embodiments, as shown in fig. 2, the test control module 140 further includes a power source 143, and the power source 143 is electrically connected to the test motherboard 110 to provide a power supply voltage to the test motherboard 110. The controller 141 can control whether to supply power to the power source 143, and when the controller 141 sends a power supply instruction, the power source 143 operates to supply power, and when a power failure instruction is sent, the power source 143 does not operate to stop supplying power. The power source 143 may also remain electrically connected to the test motherboard 110 at all times.
The CPU 120 is disposed on the test motherboard 110, and specifically, as shown in fig. 2, a CPU slot 112 is disposed on the test motherboard 110, and the CPU 120 is inserted into the CPU slot 112, in an example, the CPU slot 112 and the memory slot 111 are located on the same surface of the test motherboard 110. It should be noted that, in the present invention, only the portion of the test motherboard 110 related to the present invention is described, and the test motherboard 110 may further include other portions, which is not limited herein.
It will be apparent to those skilled in the art that many modifications and variations can be made in the apparatus and method while maintaining the teachings of the present disclosure. Accordingly, the above disclosure should be considered limited only by the scope of the following claims.
Claims (10)
1. A memory test system, comprising:
the test mainboard is provided with a memory slot for inserting a memory to be tested;
the central processing unit is arranged on the test mainboard;
the current test module is connected with the memory slot and used for measuring the working current of the memory to be tested;
and the test control module is in communication connection with the test mainboard and the current test module and is used for controlling the test mainboard to enter a BIOS setting page so as to set test parameters of the memory to be tested, controlling the central processing unit on the test mainboard to run memory test software after controlling the test mainboard to be started up so as to test the memory to be tested through the test parameters and controlling the current test module to obtain the working current of the memory to be tested.
2. The memory test system of claim 1,
the test control module comprises a memory and a controller, wherein the memory is in communication connection with the controller, and memory test software is stored in the memory;
the controller is in communication connection with the test mainboard through a USB interface.
3. The memory test system of claim 2,
the controller is used for simulating the functions of a USB keyboard and a mouse so as to control the test mainboard to enter a BIOS setting page through the USB keyboard and the mouse and set the test parameters of the memory to be tested;
the controller is used for simulating the function of a USB flash disk through the memory, controlling the central processing unit on the test mainboard to run the memory test software through the USB flash disk, and testing the memory to be tested through the test parameters.
4. The memory test system of claim 3,
the controller is used for simulating the function of a USB flash disk through the memory so as to control the central processing unit on the test mainboard to run different memory test software at different test stages through the USB flash disk.
5. The memory test system of claim 2, wherein the current test module comprises:
the adapter plate is inserted into the memory slot;
and the current acquisition circuit is arranged on the adapter plate, is electrically connected with the memory to be tested and is in communication connection with the controller through a CAN interface or a UART interface.
6. The memory test system according to claim 2, further comprising a temperature control module, wherein the temperature control module comprises a temperature control circuit and a high temperature cover electrically connected to the temperature control circuit, wherein the temperature control circuit is communicatively connected to the controller through a CAN interface or a UART interface, and the high temperature cover is disposed on the memory under test so that the memory under test is located in the high temperature cover.
7. The memory test system according to claim 2, wherein the test motherboard is further communicatively connected to the controller via a UART interface, so as to send a test result obtained by testing the memory under test with the test parameters to the controller.
8. The memory test system of claim 2,
the controller is in communication connection with the test mainboard through a GPIO interface to control the test mainboard to be started, reset and shut down.
9. The memory test system of claims 1-8, wherein the test parameters include an operating timing, an operating voltage, and an operating frequency of the memory under test.
10. The memory test system of claim 9,
the testing mainboard is provided with a CPU slot, wherein the CPU is inserted into the CPU slot, and the CPU slot and the memory slot are positioned on the same surface of the testing mainboard.
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| CN201911304012.2A CN112992261B (en) | 2019-12-17 | 2019-12-17 | Memory test system |
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| CN201911304012.2A CN112992261B (en) | 2019-12-17 | 2019-12-17 | Memory test system |
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Cited By (1)
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