CN102097321A - Method for preparing power NMOS device - Google Patents

Method for preparing power NMOS device Download PDF

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Publication number
CN102097321A
CN102097321A CN200910201929XA CN200910201929A CN102097321A CN 102097321 A CN102097321 A CN 102097321A CN 200910201929X A CN200910201929X A CN 200910201929XA CN 200910201929 A CN200910201929 A CN 200910201929A CN 102097321 A CN102097321 A CN 102097321A
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China
Prior art keywords
contact hole
preparation
nmos device
power
power nmos
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Pending
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CN200910201929XA
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Chinese (zh)
Inventor
金勤海
曹俊
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Priority to CN200910201929XA priority Critical patent/CN102097321A/en
Publication of CN102097321A publication Critical patent/CN102097321A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a method for preparing a power N-channel metal oxide semiconductor (NMOS) device. After an N+ resource region of the power NMOS device is formed, the method comprises the following steps of: (1) depositing an interlayer film on the formed structure; (2) defining the graph of a contact hole by adopting a photolithographic process, and etching the interlayer film to form the contact hole; (3) implanting nitrogen into the bottom of the contact hole by adopting an ion implantation process, then implanting boron, and performing thermal annealing treatment so that a P+ implantation region formed at the bottom of the contact hole is connected with a body region of the power MOS device; and (4) finishing the preparation of the power MOS device by adopting the conventional processes.

Description

The preparation method of power nmos device
Technical field
The present invention relates to a kind of preparation method of power N type groove MOS device.
Background technology
In the preparation of power nmos device, the tagma need be drawn with electrode, form and power NMOS (power N type metal oxide semiconductor field-effect transistor) parasitic diode in parallel, can avoid in the device the second breakdown of parasitic bipolar transistor (triode).The zone that need contact with tagma (tagma is the p type in nmos device) in the contact hole bottom forms heavily doped region (p+ district) thus.In present power nmos device preparation method, two kinds of methods are arranged.Method 1 is injected for increasing a P+ district, be specially when the N+ zone of preparation nmos device (seeing Fig. 3 and Fig. 4), when injecting, the N+ ion blocks earlier the zone (below of the contact hole of designs) that needs to form P+ with photoresist, photoetching process is exposed the zone that needs prepare P+ once more after the N+ district finishes, then carry out ion and inject formation P+ district (it is deep to the tagma), then be the technology such as deposit, contact hole etching of interlayer film, form structure as shown in Figure 1, adopt this method that the dead resistance between tagma and the source region is further reduced.Method 2 is when contact hole etching, will be etched to the tagma, forms structure as shown in Figure 2.The enforcement of method 1 need increase a photoetching and ion injects, and the etching depth in the method 2 to add ambassador's etching technics more complicated.
Summary of the invention
Technical problem to be solved by this invention provides a kind of preparation method of power nmos device, and it can reduce the process complexity of original power nmos device preparation.
For solving the problems of the technologies described above, the preparation method of power nmos device of the present invention after the N+ district of power nmos device forms, comprises the steps:
(1) at film between illuvium on the structure of above-mentioned formation;
(2) utilize photoetching process to define the figure of contact hole, film forms contact hole between etch layer;
(3) adopt ion implantation technology, nitrogen injects in elder generation in the contact hole bottom, and boron is injected in the back, then carries out thermal anneal process the P+ injection region of contact hole bottom formation and the tagma of described power MOS (Metal Oxide Semiconductor) device are joined;
(4) then adopt the common process step to finish the preparation of described power MOS (Metal Oxide Semiconductor) device.
The preparation method of power nmos device of the present invention has reduced the lithography layer that P+ district ion injects on original process 1 basis, promptly lacked lithography layer one, reduces the technology cost.And compare the complicated technology of the contact hole etching of having avoided high-aspect-ratio with method 2, and just inject and reach same effect by increasing by a step nitrogen, reduced technology difficulty.Simultaneously, this method can be used the preparation of polytype power nmos device.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the partial cross section figure by the prepared power N type bilateral diffusion MOS device of conventional method 1;
Fig. 2 is the partial cross section schematic diagram by the prepared power N type bilateral diffusion MOS device of conventional method 2;
Fig. 3 is the partial cross section schematic diagram with the corresponding power nmos device of conventional method 1 corresponding steps;
Fig. 4 is the preparation flow figure of conventional method 1;
Fig. 5 is the preparation flow figure of power nmos device of the present invention;
Fig. 6 is for adopting the schematic cross-section of the prepared N type groove MOS device of method of the present invention, and the power nmos device of other different structure also can adopt with quadrat method and prepare;
Fig. 7 is for implementing the schematic cross-section after the injection of N+ district in the method for the present invention;
Fig. 8 is for implementing the schematic cross-section after boron and nitrogen are injected in contact hole bottom in the method for the present invention.
Embodiment
Preparation method's (see figure 5) of power nmos device of the present invention at tagma injection, grid chemical wet etching and after forming the N+ source region (see figure 7) of power nmos device, comprises the steps:
(1) at film between illuvium on the structure of above-mentioned formation;
(2) utilize photoetching process to define the figure of contact hole, film forms contact hole between etch layer;
(3) adopt ion implantation technology, inject nitrogen earlier in the contact hole bottom, the boron that reinjects also can inject boron earlier, and nitrogen reinjects.Then carry out thermal anneal process, make the tagma of P+ injection region that contact hole bottom forms and the described power MOS (Metal Oxide Semiconductor) device (see figure 8) of joining;
(4) then adopt common process step (preparation technology is in full accord with the conventional power MOS transistor) to finish the preparation of described power MOS (Metal Oxide Semiconductor) device, with the groove nmos device is example, the final structure that forms as shown in Figure 6 forms the P+ district of going deep into the tagma in the contact hole bottom.
In the above-mentioned flow process, the nitrogen implantation dosage scope in the step 3 can be 10 12~10 16Atom/cm 2, energy range is 1Kev~200Kev.The dosage range 10 that boron injects 14~10 16Atom/cm 2, energy range is 1~200Kev.The temperature of annealing in process can be made as 400-1200 degree centigrade, and the time can be 10 seconds~and 10 hours.

Claims (4)

1. the preparation method of a power nmos device is characterized in that, after the N+ source region of described power nmos device forms, comprises the steps:
(1) at film between illuvium on the structure of above-mentioned formation;
(2) utilize photoetching process to define the figure of contact hole, film forms contact hole between etch layer;
(3) employing ion implantation technology is injected nitrogen earlier in the contact hole bottom, and the boron that reinjects then carries out thermal anneal process the P+ injection region of contact hole bottom formation and the tagma of described power MOS (Metal Oxide Semiconductor) device are joined;
(4) then adopt the common process step to finish the preparation of described power MOS (Metal Oxide Semiconductor) device.
2. the preparation method of power nmos device according to claim 1 is characterized in that: the ion of contact hole bottom injects in the described step 3, injects the nitrogen boron that reinjects earlier and replaces with and inject the boron nitrogen that reinjects earlier.
3. the preparation method of power nmos device according to claim 1 and 2 is characterized in that: the dosage that injects nitrogen in the described step 3 is: 10 12~10 16Atom/cm 2, the injection energy is 1~200Kev, the dosage that injects boron is: 10 14~10 16Atom/cm 2, the injection energy is 1~200Kev.
4. the preparation method of power nmos device according to claim 1 and 2 is characterized in that: the temperature of thermal anneal process is 400~1200 ℃ in the described step 3, and the processing time is 10 seconds~10 hours.
CN200910201929XA 2009-12-15 2009-12-15 Method for preparing power NMOS device Pending CN102097321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200910201929XA CN102097321A (en) 2009-12-15 2009-12-15 Method for preparing power NMOS device

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Application Number Priority Date Filing Date Title
CN200910201929XA CN102097321A (en) 2009-12-15 2009-12-15 Method for preparing power NMOS device

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CN102097321A true CN102097321A (en) 2011-06-15

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CN200910201929XA Pending CN102097321A (en) 2009-12-15 2009-12-15 Method for preparing power NMOS device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972080A (en) * 2014-05-20 2014-08-06 上海华力微电子有限公司 ONO structure and manufacturing method for ONO capacitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972080A (en) * 2014-05-20 2014-08-06 上海华力微电子有限公司 ONO structure and manufacturing method for ONO capacitor

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Application publication date: 20110615