CN102064108B - Method for manufacturing medium/nitride composite structure enhanced field effect transistor - Google Patents
Method for manufacturing medium/nitride composite structure enhanced field effect transistor Download PDFInfo
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- CN102064108B CN102064108B CN201010541356.8A CN201010541356A CN102064108B CN 102064108 B CN102064108 B CN 102064108B CN 201010541356 A CN201010541356 A CN 201010541356A CN 102064108 B CN102064108 B CN 102064108B
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Abstract
The invention discloses a method for manufacturing a medium/nitride composite structure enhanced field effect transistor, which comprises the steps of: sequentially growing a AlGaN buffer layer, a GaN channel layer, a AlN inserting layer, a AlGaN barrier layer and a AlInN cap layer on a substrate; and forming a AlInN/AlGaN/AlN composite front barrier and a GaN/AlGaN back barrier into a high electronic air tightness external channel well limited by strong electrons. The thick AlInN cap layer with lattice match remarkably improves the electronic air tightness of an external channel, and the high and wide barriers provided by the AlInN cap layer strengthen the quantum restriction of the channel well, thus the serial resistance of the external channel is lowered and the ohmic contact resistance is reduced. After the AlInN layer is corroded by using a dry method channeling process and the AlGaN barrier layer is thinned, a Si3N4 medium layer with set thickness is deposited by using an atom layer deposition (ALD) process, thus the quantum restriction of an internal channel well is strengthened, and the ON state current of the element is improved by band distortion of a heterojunction, caused in a way that an electron wave function does not permeate into the barrier layer, under the condition that a large grid voltage change is ensured. A negative space charge is introduced on the surface of the Si3N4 medium layer by using a fluorine plasma process, thus the barrier height is increased, electron air in the internal channel well is consumed fully to ensure that the inner channel is pinched off under zero grid voltage. An ideal module enhancing work is realized.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor device, especially a kind of method of manufacturing medium/nitride composite structure enhancement mode field effect transistor.Specifically with can with cut-out method produce respectively there is the outer raceway groove trap of high density high mobility two-dimensional electron gas and under zero grid voltage pinch off, the large positive grid voltage lower channel that can prevent opened under positive grid voltage can be with the interior raceway groove trap distorting, the method for efficient in order to manufacture, high-power enhancement type gallium nitride field-effect transistor.Belong to technical field of semiconductor device.
Background technology
Enhancement mode field effect transistor is a kind of field effect transistor of working under positive grid voltage.It requires the outer raceway groove outside gate electrode to open, and series resistance is very low, and interior raceway groove pinch off under zero grid voltage under gate electrode is being opened under positive grid voltage, has good switch performance.This just requires inside and outside raceway groove to have diverse heterostructure.Therefore, in heterogeneous structure material design, first to design the heterostructure of outer raceway groove, make to produce in raceway groove the two-dimensional electron gas of high density, high mobility.Then, cut out the heterostructure of interior raceway groove under gate electrode by semiconductor technology, exhaust the two-dimensional electron gas in raceway groove trap completely, and can under large positive grid voltage, open interior raceway groove, rebuild the two-dimensional electron gas of high density, high mobility.Therefore it not only will design high-performance raceway groove trap, also will seek can be with the scheme of cutting out efficiently, implements effectively can be with and cut out in the grid region of submicron-scale.
Electron gas density in AlGaN/GaN heterojunction raceway groove trap depends on the polarization charge on heterogeneous interface.Enable the interior raceway groove of band after cutting out can be under zero grid voltage pinch off, can not use the barrier layer that polarization charge is too high.This has just limited the electron gas density in outer raceway groove.At present external customary way is on channel barrier layer, to cover one deck cap layer outside, improves raceway groove trap electron gas density with the polarization charge between cap layer/barrier layer.Everybody uses AlN to make cap layer.But lattice mismatch is very large between AlN and GaN, the AlN cap layer that can only grow very thin, heterogeneous interface from raceway groove trap away from, channel electrons air tightness improves few.In addition, the large band offsets on AlN/AlGaN interface and strong polarization charge can form again a very strong interface trap, and the electronics in raceway groove trap is transferred in barrier layer, have reduced the mobility of electronics.
Being with of interior raceway groove cut out and is a thorny difficult problem.Customary way is to carry out attenuate barrier layer thickness by grooving at present, the electron gas density of raceway groove in reducing.But, make interior raceway groove pinch off under zero grid voltage, barrier layer must be thinned to below 5nm.Like this, under positive grid voltage, just no longer can produce effective quantum limit, make electron wave function be penetrated into barrier layer surface, form surface wells, produce and can be with distortion, reduce the electron gas density in raceway groove trap, cause interior raceway groove can not open completely under positive grid voltage.And electronics in surface wells increased again grid current, many authors blanket dielectric layer on barrier layer, makes MISFET and suppresses grid current.Although this device can increase positive grid voltage, the serious distortion of being with makes device performance degeneration.Another kind method is to process and introduce surface negative charge with fluoro plasma, exhausts the electron gas of interior raceway groove.But, must carry out pinch off raceway groove with very strong negative electrical charge, thereby reduce the electric current in trench digging road.Moreover strong surface negative charge equally also can cause can be with distortion.
Present patent application person finds to use in the time of the outer raceway groove of design enhancement mode field effect transistor and the AlInN cap layer of GaN Lattice Matching substitutes used AlN cap layer, not only can solve Lattice Matching and grow thick AlInN cap layer, make the more close raceway groove trap of interfacial polarization electric charge, improve the electron gas density of raceway groove trap.But also reduced band offsets and the polarization charge on heterogeneous interface, and improve the trap position of interface trap, prevent that electron wave function is penetrated into barrier layer.Being with while cutting out of raceway groove in research, discovery covers Si on the barrier layer of attenuate
3n
4dielectric layer, can utilize Si
3n
4/ AlGaN heterojunction is transformed interior raceway groove trap, then uses fluoro plasma PROCESS FOR TREATMENT Si
3n
4surface, introduces suitable negative electrical charge, realizes pinch off under zero grid voltage and the interior raceway groove trap that can open completely under large positive grid voltage, suppress under positive grid voltage in raceway groove trap can be with distortion.Thereby two hang-ups in the design of enhancement mode field effect transistor are solved.
Summary of the invention
Object of the present invention is intended to cover with the AlInN cap layer of Lattice Matching the heterostructure of the outer raceway groove of thin AlGaN barrier layer formation.Utilize the polarization charge on AlInN/AlGaN heterogeneous interface to improve the two-dimensional electron gas density in GaN raceway groove trap.Strengthen the two-dimensional characteristics of electron gas in GaN raceway groove trap with the high potential barrier of thick AlInN cap layer, improve electron transport performance.Reduce series resistance and the ohmic contact resistance of outer raceway groove, increase the channel current of HFET.Corrode the Si that sets thickness after AlInN cap layer and attenuate AlGaN barrier layer with the deposit of ALD technique with dry corrosion process
3n
4dielectric layer, uses fluoro plasma treatment process at Si
3n
4high concentration negative space charge is introduced on surface, constructs perfect interior raceway groove heterostructure.Make more than threshold voltage just moving on to 0V.And use Si
3n
4/ AlGaN heterostructure is strengthened the quantum limit of interior raceway groove trap under large positive grid voltage, prevents heterostructure band distortion.Realize high performance enhancement mode work.
Technical solution of the present invention: a kind of method of manufacturing medium/nitride composite structure enhancement mode field effect transistor, is characterized in that the method comprises following processing step:
One, the AlGaN resilient coating of growing successively on substrate, GaN channel layer, AlN insert layer, AlGaN barrier layer and AlInN cap layer;
Two, growing GaN channel layer on AlGaN resilient coating, forms back of the body potential barrier and improves raceway groove pinch-off behavior, and field effect transistor threshold voltage is shuffled;
Three, growth and the AlInN layer of GaN Lattice Matching on thin AlGaN barrier layer, utilizes polarization charge on AlInN/AlGaN heterogeneous interface to increase the electron gas density in GaN channel layer below.Utilize the band offsets on this heterogeneous interface to set up high potential barrier, prevent that the electron wave function in channel layer is penetrated into barrier layer, strengthening electronic two-dimensional characteristics, improves electron mobility; Be built into outer raceway groove trap, improve electron gas density and mobility in raceway groove trap, reduce outer raceway groove series resistance and ohmic contact resistance;
Four, corrode after AlInN cap layer 6 and attenuate AlGaN barrier layer with directly deposit Si on the AlGaN of attenuate barrier layer of atomic layer deposition (ALD) technique with dry process
3n
4dielectric layer Si
3n
4/ AlGaN heterojunction forms high potential barrier, constructs the raceway groove trap of interior raceway groove;
Five, use fluoro plasma technique at Si
3n
4in layer, introduce high density negative electrical charge, exhaust the two-dimensional electron gas in interior raceway groove trap with strong negative electrical charge, make interior raceway groove pinch off under zero grid voltage, just opening under grid voltage, realize enhancement mode work, the Si of optimal design fluoro plasma PROCESS FOR TREATMENT
3n
4/ AlGaN combines potential barrier, prevents that the raceway groove under large positive grid voltage can be with distortion, increases channel current.
Advantage of the present invention: cover thin AlGaN barrier layer with the AlInN cap layer of Lattice Matching and make cap layer polarization charge approach GaN raceway groove trap, can more effectively utilize cap layer heterojunction polarization charge to improve the electron gas density in raceway groove trap.The band offsets of AlInN/AlGaN heterojunction and polarization charge can be raised the trap position of cap bed boundary trap, prevent that channel electrons is penetrated into interface trap and barrier layer, improve electronics two-dimensional characteristics and transport performance, reduce outer raceway groove series resistance.AlInN barrier height is low, and AlInN/AlGaN composite potential barrier raceway groove trap electron gas density is high, on AlInN barrier layer, makes ohmic contact, can reduce contact resistance.On the AlGaN of attenuate barrier layer, the Si of thickness is set in deposit
3n
4layer provides perfect high barrier heterojunction structure for interior raceway groove trap, prevents that large positive grid voltage lower channel electron wave function is penetrated into barrier layer surface and causes and can be with distortion, has improved electron mobility and channel current.At Si
3n
4dielectric layer surface is processed and is introduced space negative electrical charge with fluoro plasma, has improved barrier height, exhausts channel electrons gas, realizes the enhancement mode work of positive grid voltage.
Brief description of the drawings
Accompanying drawing 1 is the material structure figure of medium/nitride composite structure enhancement mode field effect transistor of the present invention.
Accompanying drawing 2 is structure charts of raceway groove in medium/nitride composite structure enhancement mode field effect transistor of the present invention.
In figure, 1 is substrate, the 2nd, AlGaN resilient coating, the 3rd, GaN channel layer, the 4th, AlN insert layer, the 5th, AlGaN barrier layer, the 6th, AlInN Lattice Matching cap layer, the 7th, Si
3n
4dielectric layer, the 8th, the AlGaN barrier layer of attenuate.
Embodiment
Further describe by reference to the accompanying drawings medium/nitride composite structure enhancement mode field effect transistor manufacture method, its step is divided: the AlGaN resilient coating 2 of, growing successively on substrate 1, GaN channel layer 3, AlN insert layer 4, AlGaN barrier layer 5 and AlInN cap layer 6;
Two, self-consistent solution Schrodinger equation and Poisson's equation, the two-dimensional electron gas density in energy band, electron wave function and the raceway groove of calculating heterostructure;
Three, regulate height and the width of GaN/AlGaN back of the body potential barrier and AlInN/AlGaN/AlN/GaN early barrier, make to produce in raceway groove trap sufficiently high two-dimensional electron gas density, and optimize component ratio and the thickness of selecting AlInN, AlGaN and AlN, improve the trap position of AlInN/AlGaN interface trap, make not exist in interface trap electronics, guarantee that channel electrons wave function does not permeate in AlInN/AlGaN interface trap and barrier layer, completes the optimal design of outer raceway groove heterostructure.
Four,, according to shown in Fig. 2, corrode AlInN cap layer 6 and attenuate AlGaN barrier layer 8 is rear with ALD technique deposit Si on the AlGaN of attenuate barrier layer 8 with dry corrosion process
3n
4dielectric layer 7, obtains raceway groove in medium/nitride composite structure enhancement mode field effect transistor.
Five, use fluoro plasma treatment process at Si
3n
4negative space charge is introduced on layer surface;
Six, the Si through fluoro plasma processing
3n
4the AlGaN layer of layer and attenuate is regarded new heterojunction as,
The Schrodinger equation of this new heterojunction of self-consistent solution and Poisson's equation, raceway groove energy band, electron wave function and electron gas density in calculating;
Seven, design GaN/AlGaN back of the body potential barrier and Si
3n
4the structure of/AlGaN/AlN/GaN early barrier, makes interior raceway groove trap pinch off under zero grid voltage, under large positive grid voltage electronics still well quantum limit in raceway groove trap, do not occur to be with distortion, in the grid voltage mobility scale of setting, gate capacitance remains unchanged, and completes the optimal design of interior raceway groove heterostructure.
The medium/nitride composite structure enhancement mode field effect transistor of the inside and outside raceway groove heterostructure of optimal design, in manufacturing process, 1) with photoetching, metal deposit and annealing process in source, leak ohmic contact regions and make ohmic contact, utilize high density, high mobility two-dimensional electron gas in low potential barrier and the outer raceway groove of AlInN to reduce ohmic contact resistance; 2) in the dry process grooving of gate electrode region, corrode after AlInN cap layer and attenuate AlGaN barrier layer, set the Si of thickness with the deposit of ALD technique
3n
4dielectric layer; 3) at Si
3n
4negative space charge is introduced with fluoro plasma treatment process in dielectric layer surface, makes the interior raceway groove heterostructure of setting; 4) on interior raceway groove heterojunction, depositing metal is made Schottky barrier again, thereby makes the medium/nitride composite structure enhancement mode field effect transistor with the inside and outside raceway groove heterostructure of optimal design.
Embodiment 1:
Al grows on substrate 1
0.04ga
0.96n resilient coating 2 and the 10nm GaN channel layer 3 that undopes, forms back of the body potential barrier.The plain AlN insert layer 4 of 1nm of growing on channel layer 3 again, the 5nm Al that undopes
0.25ga
0.75n barrier layer and the 14nm Al that undopes
0.83in
0.17n cap layer 6, forms early barrier.Calculate band offsets and polarization charge on various heterogeneous interfaces, according to effective mass and dielectric constant self-consistent solution Schrodinger equation and the Poisson's equation of layers of material, calculate to such an extent that the electron gas density of outer raceway groove is 1.775*10
13cm
-2.The whole quantum limit of electron wave function are in GaN raceway groove trap, and electronics has strong two-dimensional characteristics and height transports performance.Outer raceway groove series resistance and ohmic contact resistance are reduced.Then corrode AlInN cap layer 6 and attenuate AlGaN barrier layer by dry method grooving technique, leave 2nmAlGaN barrier layer, with ALD technique deposit 7nm Si
3n
4layer 7, uses fluoro plasma technique at Si
3n
4in the surperficial 5nm of layer, introduce 2*10
19cm
-3the negative space charge of concentration.Self-consistent solution Schrodinger equation and Poisson's equation, trying to achieve zero grid voltage lower channel electron gas density is zero, raceway groove pinch off.Under 3.7V grid voltage, electron gas density is 1.377*10
13cm
-2.In whole grid voltage mobility scale, electron gas density increases with grid voltage rising is linear, and gate capacitance remains unchanged.Reach desirable enhancement mode operating state.
Embodiment 2:
Al grows on substrate 1
0.07ga
0.93n resilient coating 2 and the 10nm GaN channel layer 3 that undopes, forms back of the body potential barrier.The plain AlN insert layer 4 of 1nm of growing on channel layer 3 again, the 5nm Al that undopes
0.3ga
0.7n barrier layer and the 20nm Al that undopes
0.83in
0.17n cap layer 6, forms early barrier.Self-consistent solution Schrodinger equation and Poisson's equation, calculate to such an extent that the electron gas density of outer raceway groove is 1.789*10
13cm
-2.The whole quantum limit of electron wave function are in GaN raceway groove trap, and electronics has strong two-dimensional characteristics and height transports performance.Outer raceway groove series resistance and ohmic contact resistance are reduced.Then corrode AlInN cap layer 6 and attenuate AlGaN barrier layer by dry method grooving technique, leave 2nmAlGaN barrier layer, with ALD technique deposit 5nm Si
3n
4layer 7, uses fluoro plasma technique at Si
3n
4in the surperficial 5nm of layer, introduce 2*10
19cm
-3the negative space charge of concentration.Self-consistent solution Schrodinger equation and Poisson's equation, trying to achieve zero grid voltage lower channel electron gas density is zero, raceway groove pinch off.Under 3.5V grid voltage, electron gas density is 1.496*10
13cm
-2.In whole grid voltage mobility scale, electron gas density increases with grid voltage rising is linear, and gate capacitance remains unchanged.Reach desirable enhancement mode operating state.
Embodiment 3:
Al grows on substrate 1
0.1ga
0.9n resilient coating 2 and the 10nm GaN channel layer 3 that undopes, forms back of the body potential barrier.The plain AlN insert layer 4 of 1nm of growing on channel layer 3 again, the 5nm Al that undopes
0.35ga
0.65n barrier layer and the 25nm Al that undopes
0.83in
0.17n cap layer 6, forms early barrier.Self-consistent solution Schrodinger equation and Poisson's equation, calculate to such an extent that the electron gas density of outer raceway groove is 1.738*10
13cm
-2.The whole quantum limit of electron wave function are in GaN raceway groove trap, and electronics has strong two-dimensional characteristics and height transports performance.Outer raceway groove series resistance and ohmic contact resistance are reduced.Then corrode AlInN cap layer 6 and attenuate AlGaN barrier layer by dry method grooving technique, leave 2nmAlGaN barrier layer, with ALD technique deposit 5nm Si
3n
4layer 7, uses fluoro plasma technique at Si
3n
4in the surperficial 5nm of layer, introduce 2*10
19cm
-3the negative space charge of concentration.Self-consistent solution Schrodinger equation and Poisson's equation, trying to achieve zero grid voltage lower channel electron gas density is zero, raceway groove pinch off.Under 3.6V grid voltage, electron gas density is 1.619*10
13cm
-2.In whole grid voltage mobility scale, electron gas density increases with grid voltage rising is linear, and gate capacitance remains unchanged.Reach desirable enhancement mode operating state.
Claims (1)
1. manufacture a method for medium/nitride composite structure enhancement mode field effect transistor, it is characterized in that the method comprises that following processing step is:
One, the AlGaN resilient coating of growing successively on substrate, GaN channel layer, AlN insert layer, AlGaN barrier layer and AlInN cap layer, specifically
(1) growing GaN channel layer on AlGaN resilient coating, forms back of the body potential barrier and improves raceway groove pinch-off behavior, and field effect transistor threshold voltage is shuffled;
(2) the AlInN layer of growth and GaN Lattice Matching on 5nmAlGaN barrier layer, utilize polarization charge on AlInN/AlGaN heterogeneous interface to increase the electron gas density in GaN channel layer below, utilize the band offsets on this heterogeneous interface to set up high potential barrier, prevent that the electron wave function in channel layer is penetrated into barrier layer, strengthening electronic two-dimensional characteristics, improve electron mobility, be built into outer raceway groove trap, improve electron gas density and mobility in raceway groove trap, reduce outer raceway groove series resistance and ohmic contact resistance;
Two, corrode after AlInN cap layer and part AlGaN barrier layer with directly deposit Si on remaining AlGaN barrier layer of atomic layer deposition (ALD) technique with dry process
3n
4, use Si
3n
4/ AlGaN heterojunction forms high potential barrier, constructs the raceway groove trap of interior raceway groove;
Three, use fluoro plasma technique at Si
3n
4in layer, introduce high density negative electrical charge, use 2*10
19cm
-3the negative space charge of concentration exhausts the two-dimensional electron gas in interior raceway groove trap, makes interior raceway groove pinch off under zero grid voltage, under positive grid voltage, opens, and realizes enhancement mode work, the Si of optimal design fluoro plasma PROCESS FOR TREATMENT
3n
4/ AlGaN combines potential barrier, prevents that the raceway groove under 3.7V grid voltage, 3.6V grid voltage and 3.5V grid voltage can be with distortion, increases channel current.
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| CN105336770A (en) * | 2014-08-06 | 2016-02-17 | 江西省昌大光电科技有限公司 | Gallium nitride based high electron mobility transistor epitaxial structure and manufacturing method thereof |
| CN104576371B (en) * | 2014-12-11 | 2018-07-20 | 中国电子科技集团公司第五十五研究所 | A method of manufacture electron gas back barrier gallium nitride hetero junction field effect pipe |
| CN104979215B (en) | 2015-06-23 | 2018-01-02 | 京东方科技集团股份有限公司 | Low-temperature polysilicon film transistor and preparation method thereof |
| CN106098793A (en) * | 2016-06-30 | 2016-11-09 | 江苏能华微电子科技发展有限公司 | Schottky diode epitaxial wafer and preparation method thereof |
| CN108666359A (en) * | 2017-03-29 | 2018-10-16 | 北京大学 | A kind of device architecture and implementation method improving GaN enhancement type channel mobilities using novel barrier layer |
| CN108091687B (en) * | 2017-12-22 | 2020-10-27 | 大连芯冠科技有限公司 | GaNHEMT with plasma passivation layer and preparation method |
| CN111463273A (en) * | 2020-03-25 | 2020-07-28 | 西北工业大学 | Long-off HEMT device based on gallium nitride heterojunction epitaxy and preparation method thereof |
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