CN102054803A - External radiator packaging structure for matrix island-exposed chip face-up radiating block - Google Patents

External radiator packaging structure for matrix island-exposed chip face-up radiating block Download PDF

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Publication number
CN102054803A
CN102054803A CN 201010558822 CN201010558822A CN102054803A CN 102054803 A CN102054803 A CN 102054803A CN 201010558822 CN201010558822 CN 201010558822 CN 201010558822 A CN201010558822 A CN 201010558822A CN 102054803 A CN102054803 A CN 102054803A
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CN
China
Prior art keywords
chip
radiating block
packaging structure
radiator
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN 201010558822
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Chinese (zh)
Inventor
王新潮
梁志忠
高盼盼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN 201010558822 priority Critical patent/CN102054803A/en
Publication of CN102054803A publication Critical patent/CN102054803A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

The invention relates to an external radiator packaging structure for a matrix island-exposed chip face-up radiating block. The external radiator packaging structure comprises a chip (3), a metal matrix island (1), a metal inner pin (4), a metal wire (5), a conductive or nonconductive heat conducting bonding material I (2) and a plastic package body (8), wherein the metal matrix island (1) is loaded below the chip; the metal wire (5) is used for interconnecting signals from the chip to the metal inner pin; the conductive or nonconductive heat conducting bonding material I (2) is arranged between the chip and the metal matrix island; and the metal matrix island (1) is exposed out of the plastic package body (8). The external radiator packaging structure is characterized in that: a radiating block (7) is arranged above the chip (3), and a conductive or nonconductive heat conducting bonding material II (6) is embedded between the radiating block (7) and the chip (3); and a radiator (11) is arranged above the radiating block (7), and a conductive or nonconductive heat conducting bonding material III (13) is embedded between the radiator (11) ad the radiating block (7). The packaging structure has high radiating capability.

Description

The heat radiating block positively arranged external radiator packaging structure of base island exposed chip
Technical field
The present invention relates to the heat radiating block positively arranged external radiator packaging structure of a kind of base island exposed chip.Belong to the semiconductor packaging field.
Background technology
The radiating mode of traditional Chip Packaging form mainly be to have adopted the Metal Substrate island of chip below as heat radiation conduction instrument or approach, and there is following not enough point in the heat radiation of this conventional package mode conduction:
1, Metal Substrate island volume is too little
The Metal Substrate island is in the conventional package form, in order to pursue the reliability safety of packaging body, nearly all adopted the Metal Substrate island to be embedded in the packaging body, and in limited packaging body, to imbed the interior pin (as shown in Figures 1 and 2) of metal of Metal Substrate island and signal, power supply conduction usefulness simultaneously, very the little so effective area on Metal Substrate island and volume just seem, and the function of the heat radiation of high heat also will be served as in the Metal Substrate island simultaneously, will seem deficiency more.
2, baried type Metal Substrate island (as shown in Figures 1 and 2)
The Metal Substrate island is in the conventional package form, in order to pursue the reliability safety of packaging body, nearly all adopted the Metal Substrate island to be embedded in the packaging body, and the Metal Substrate island is about dependence or four fine support bars in corner fix or support metal Ji Dao, also because the characteristic of this fine support bar, the heat that has caused the Metal Substrate island to be absorbed from the chip, can't conduct out from fine support bar fast, so the heat of chip can't or be transmitted to the packaging body external world fast, caused the life-span quick aging of chip even burn or burnt out.
3, Metal Substrate island exposed type (as shown in Figures 3 and 4)
Though expose on the Metal Substrate island, can provide also will good heat-sinking capability than the heat sinking function of baried type, because the volume on Metal Substrate island and area still very little in packaging body, so heat dissipation capability can be provided, still very limited.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, providing a kind of can provide the strong base island exposed chip of heat dissipation capability heat radiating block positively arranged external radiator packaging structure.
The object of the present invention is achieved like this: the heat radiating block positively arranged external radiator packaging structure of a kind of base island exposed chip, include chip, the Metal Substrate island of being carried of chip below, the interior pin of metal, chip to conduction or nonconducting heat conduction bonding material I and plastic-sealed body between wire, chip and the Metal Substrate island of the signal interconnection of the interior pin of metal, the base island exposed plastic-sealed body of described metal, it is characterized in that above described chip, being provided with radiating block, be equipped with conduction or nonconducting heat conduction bonding material II between this radiating block and the described chip; Above described radiating block, be provided with radiator, be equipped with conduction or nonconducting heat conduction bonding material III between this radiator and the described radiating block.
The invention has the beneficial effects as follows:
The present invention passes through addition radiating block above chip, and sets up radiator outside plastic-sealed body, serves as the function of the heat radiation of high heat, can provide heat dissipation capability strong, makes the heat of chip can be transmitted to the packaging body external world fast.Can be applied in and make it become height or superelevation heat radiation (High Thermal or Super High Thermal) ability on the packaging body of general packing forms and the packaging technology, can become SHT-FBP/QFN as FBP can become SHT-QFN/BGA and can become SHT-BGA/CSP and can become SHT-CSP ...Avoided the life-span quick aging of chip even burn or burnt out.
Description of drawings
Fig. 1 is Metal Substrate island baried type chip-packaging structure schematic diagram in the past.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 is Metal Substrate island exposed type chip-packaging structure schematic diagram in the past.
Fig. 4 is the vertical view of Fig. 3.
Fig. 5 is heat radiating block positively arranged external radiator packaging structure embodiment 1 schematic diagram of base island exposed chip of the present invention.
Fig. 6 is heat radiating block positively arranged external radiator packaging structure embodiment 2 schematic diagrames of base island exposed chip of the present invention.
Reference numeral among the figure:
Pin 4, wire 5, conduction or nonconducting heat conduction bonding material II 6, radiating block 7, plastic-sealed body 8, radiator 11, conduction or nonconducting heat conduction bonding material III 13 in Metal Substrate island 1, conduction or nonconducting heat conduction bonding material I 2, chip 3, the metal.
Embodiment
Embodiment 1:
Referring to Fig. 5, Fig. 5 is heat radiating block positively arranged external radiator packaging structure embodiment 1 schematic diagram of base island exposed chip of the present invention.As seen from Figure 5, the heat radiating block positively arranged external radiator packaging structure of base island exposed chip of the present invention, include chip 3, the Metal Substrate island 1 of being carried of chip below, the interior pin 4 of metal, chip to conduction or nonconducting heat conduction bonding material I 2 and plastic-sealed body 8 between wire 5, chip and the Metal Substrate island of the signal interconnection of the interior pin of metal, plastic-sealed body 8 is exposed on described Metal Substrate island 1, above described chip 3, be provided with radiating block 7, be equipped with conduction or nonconducting heat conduction bonding material II 6 between this radiating block 7 and the described chip 3; Above described radiating block 7, be provided with radiator 11, be equipped with conduction or nonconducting heat conduction bonding material III 13 between this radiator 11 and the described radiating block 7.
The material of described radiating block 7 can be copper, aluminium, pottery or alloy etc.
The material of described radiator 11 can be copper, aluminium, pottery or alloy etc.
Embodiment 2:
Embodiment 2 only is with the difference of embodiment 1: described radiator 11 is for radiating cap, as Fig. 6.

Claims (4)

1. heat radiating block positively arranged external radiator packaging structure of base island exposed chip, include chip (3), the Metal Substrate island (1) of being carried of chip below, pin (4) in the metal, chip is to the wire (5) of the signal interconnection of the interior pin of metal, conduction between chip and the Metal Substrate island or nonconducting heat conduction bonding material I (2) and plastic-sealed body (8), plastic-sealed body (8) is exposed on described Metal Substrate island (1), it is characterized in that being provided with radiating block (7), be equipped with conduction or nonconducting heat conduction bonding material II (6) between this radiating block (7) and the described chip (3) in described chip (3) top; Be provided with radiator (11) in described radiating block (7) top, be equipped with conduction or nonconducting heat conduction bonding material III (13) between this radiator (11) and the described radiating block (7).
2. the heat radiating block positively arranged external radiator packaging structure of a kind of base island exposed chip according to claim 1, the material that it is characterized in that described radiating block (7) is copper, aluminium, pottery or alloy.
3. the heat radiating block positively arranged external radiator packaging structure of a kind of base island exposed chip according to claim 1, the material that it is characterized in that described radiator (11) is copper, aluminium, pottery or alloy.
4. according to claim 1, the heat radiating block positively arranged external radiator packaging structure of 2 or 3 described a kind of base island exposed chips, it is characterized in that: described radiator (11) is a radiating cap.
CN 201010558822 2010-01-29 2010-11-25 External radiator packaging structure for matrix island-exposed chip face-up radiating block Pending CN102054803A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201010558822 CN102054803A (en) 2010-01-29 2010-11-25 External radiator packaging structure for matrix island-exposed chip face-up radiating block

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
CN201010115546.3 2010-01-29
CN201010115546 2010-01-29
CN201010115536 2010-01-29
CN201010115536.X 2010-01-29
CN 201010558822 CN102054803A (en) 2010-01-29 2010-11-25 External radiator packaging structure for matrix island-exposed chip face-up radiating block

Publications (1)

Publication Number Publication Date
CN102054803A true CN102054803A (en) 2011-05-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201010558822 Pending CN102054803A (en) 2010-01-29 2010-11-25 External radiator packaging structure for matrix island-exposed chip face-up radiating block

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05299544A (en) * 1992-04-20 1993-11-12 Hitachi Ltd Semiconductor device
US5814536A (en) * 1995-12-27 1998-09-29 Lsi Logic Corporation Method of manufacturing powdered metal heat sinks having increased surface area
CN1355564A (en) * 2000-11-24 2002-06-26 矽品精密工业股份有限公司 Semiconductor package and its making method
CN1630073A (en) * 2003-12-19 2005-06-22 威宇科技测试封装有限公司 Chip ball grid array packaging structure
CN1725460A (en) * 2005-05-27 2006-01-25 江苏长电科技股份有限公司 Plane button type packing technology of integrated circuit or discrete component and its packing structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05299544A (en) * 1992-04-20 1993-11-12 Hitachi Ltd Semiconductor device
US5814536A (en) * 1995-12-27 1998-09-29 Lsi Logic Corporation Method of manufacturing powdered metal heat sinks having increased surface area
CN1355564A (en) * 2000-11-24 2002-06-26 矽品精密工业股份有限公司 Semiconductor package and its making method
CN1630073A (en) * 2003-12-19 2005-06-22 威宇科技测试封装有限公司 Chip ball grid array packaging structure
CN1725460A (en) * 2005-05-27 2006-01-25 江苏长电科技股份有限公司 Plane button type packing technology of integrated circuit or discrete component and its packing structure

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Application publication date: 20110511