CN102053939A - Hot-plug control method of Peripheral Component Interconnect Express (PCIE) tab - Google Patents
Hot-plug control method of Peripheral Component Interconnect Express (PCIE) tab Download PDFInfo
- Publication number
- CN102053939A CN102053939A CN2009102077543A CN200910207754A CN102053939A CN 102053939 A CN102053939 A CN 102053939A CN 2009102077543 A CN2009102077543 A CN 2009102077543A CN 200910207754 A CN200910207754 A CN 200910207754A CN 102053939 A CN102053939 A CN 102053939A
- Authority
- CN
- China
- Prior art keywords
- peripheral device
- device element
- element interconnection
- quick peripheral
- tab
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to a hot-plug control method of a Peripheral Component Interconnect Express (PCIE) tab. The hot-plug function of the PCIE tab is realized by the control of a PCIE fixture connected between a host computer PCIE slot and the PCIE tab, so that the performance of the PCIE tab can be continuously tested without restarting a host computer in the testing process of the PCIE tab.
Description
Technical field
The invention relates to the hot plug control method of a kind of tab (Option Card), especially about the hot plug control method of a kind of quick peripheral device element interconnection (Peripheral Component Interconnect Express, be called for short PCIE) tab.
Background technology
Peripheral device element interconnection (Peripheral Component Interconnect is called for short PCI) is a kind of bus standard that connects computer motherboard and peripheral equipment, is formulated by Intel Company and delivers.It can be connected with address bus, data bus, the most control bus pin of CPU (central processing unit) (Central Processing Unit, be called for short CPU), but must be by the control chip signal of transferring.The PCI standard code entity size of this bus (comprising live width), electricity characteristic, bus timing and agreement etc., advantages such as bus structure are simple, cost is low, simplicity of design that it has.
Fast the peripheral device element interconnection is a kind of up-to-date bus and interface standard, is the higher development of PCI, and it has continued to use existing P CI programming concept and communication standard, but builds based on serial communication system faster.The characteristics of PCIE maximum are its versatility, not only can allow it be used for being connected of south bridge and other equipment, also can extend to the connection between chipset, even also can be used to connect graphic chips, like this, whole I/O (I/O) system reunifies, and will further simplify computer system, increases the portability and the modularization of computer.In addition, because PCIE Mining has used at present popular in the industry point-to-point connected in series, common parallel framework compared with PCI and more early stage computer bus, its each equipment all has the special use of oneself to connect, do not need to whole bus request bandwidth, and can bring up to a very high frequency to the data transfer rate, reach PCI the high bandwidth that can not provide.Can only realize one-way transmission at single Shi Jian Week in phase with respect to existing P CI bus, the advantage of PCIE is the transfer rate and the quality that can provide higher.
At present, when testing, after a PCIE tab test is finished, must restart main frame at PCIE tab (Option Card) on production line, the PCIE tab that more renews then is so that test once more.So, owing to need constantly restart main frame, therefore, the efficient of in the prior art PCIE tab being tested is lower, and then expects that providing a kind of need not restart the method that main frame just can be tested the PCIE tab continuously.
Summary of the invention
In order to solve above-mentioned the problems of the prior art and defective, the invention provides the hot plug control method of a kind of quick peripheral device element interconnection (hereinafter to be referred as PCIE) tab, can realize the hot plug function of PCIE tab by the PCIE anchor clamps control that is connected between host PC IE slot and the PCIE tab, and then need not restart main frame and just can test the performance of PCIE tab continuously.
The hot plug control method of a kind of PCIE tab proposed by the invention, by being connected the hot plug function of the PCIE anchor clamps control realization PCIE tab between host PC IE slot and the PCIE tab, this hot plug control method comprises following steps:
When opening main frame, store the PCIE configuration space of PCIE tab in advance, to be used for that the PCIE configuration space is carried out extensive Complex at every turn;
When needs control PCIE tab is carried out heat insertion operation, detect downstream (Downstream) interface whether the PCIE tab has inserted the PCIE anchor clamps earlier;
After detecting the PCIE tab and having inserted the downstream interface of PCIE anchor clamps, open the power supply of the downstream interface of PCIE anchor clamps;
Enable the upstream device of PCIE anchor clamps;
Open the downstream link of PCIE anchor clamps;
By the PCIE configuration space that stores in advance the PCIE configuration space of PCIE tab is carried out extensive Complex;
Enable the PCIE tab or the driver of PCIE tab is installed, insert operation with the heat of finishing the PCIE tab;
When needs control PCIE tab is carried out hot drawing and gone out to operate, detect in the downstream interface of PCIE anchor clamps whether be inserted with the PCIE tab;
After being inserted with the PCIE tab in the downstream interface that detects the PCIE anchor clamps, the driver of forbidding PCIE tab or unloading PCIE tab;
Close the downstream link of PCIE anchor clamps;
The upstream device of forbidding PCIE anchor clamps;
Close the power supply of the downstream interface of PCIE anchor clamps; And
Extract the PCIE tab in the downstream interface of PCIE anchor clamps, go out operation with the hot drawing of finishing the PCIE tab.
Wherein, in the hot plug control method of the PCIE tab that the invention described above proposed, described PCIE test fixture is the Himalia anchor clamps based on MSP430 chip and PEX8632 chip.
In sum, the hot plug control method of PCIE tab proposed by the invention, because can be by being connected the hot plug function of the PCIE anchor clamps control realization PCIE tab between host PC IE slot and the PCIE tab, and then make in the test process of PCIE tab, need not restart main frame and just can test the performance of PCIE tab continuously.Therefore, greatly improve testing efficiency and reduced the test duration, can help real robotization and the intelligent test of realizing the PCIE tab.
Description of drawings
Fig. 1 is the flow chart of steps of hot plug control method of the PCIE tab of one embodiment of the invention;
Fig. 2 is the power pin synoptic diagram of the downstream interface of PCIE anchor clamps in the hot plug control method of PCIE tab of the present invention;
The syndeton calcspar of PCIE anchor clamps that the Mining of institute uses in the hot plug control method of Fig. 3 PCIE tab of the present invention and main frame and PCIE tab; And
Fig. 4 is the structure calcspar of the PCIE anchor clamps that the Mining of institute uses in the hot plug control method of PCIE tab of the present invention.
Description of reference numerals
10 Himalia anchor clamps
20 main frames
30 PCIE tab
Embodiment
Relevant characteristics and implementation of the present invention cooperate diagram to be described in detail as follows do preferred embodiment.
Relevant characteristics and implementation of the present invention cooperate diagram to be described in detail as follows do preferred embodiment.
Please refer to Fig. 1, this figure is the flow chart of steps of hot plug control method of the PCIE tab of one embodiment of the invention, as shown in the figure, the hot plug control method of a kind of PCIE tab provided by the present invention, by being connected the hot plug function of the PCIE anchor clamps control realization PCIE tab between host PC IE slot and the PCIE tab, this hot plug control method comprises following steps:
Step 101 when opening main frame, stores the PCIE configuration space of PCIE tab, to be used for that the PCIE configuration space is carried out extensive Complex at every turn in advance;
Step 102, judgement need control PCIE tab to carry out heat insertion operation or hot drawing goes out operation;
Step 103, when needs control PCIE tab is carried out heat insertion operation, detect downstream (Downstream) interface whether the PCIE tab has inserted the PCIE anchor clamps earlier, wherein, described PCIE anchor clamps are the Himalia anchor clamps based on MSP430 chip and PEX8632 chip;
Step 104, after detecting the PCIE tab and having inserted the downstream interface of PCIE anchor clamps, open the power supply of the downstream interface of PCIE anchor clamps, wherein, described power source voltage is respectively: SB10 3V3 AUX, SB8 3V3, SA9 3V3, SA10 3V3, SB1 12V, SB2 12V, SB3 12V, SA2 12V and SA3 12V, and its power pin is as shown in Figure 2;
Step 105, enable the upstream device of PCIE anchor clamps, wherein, in Windows operating system, enable the upstream device of PCIE anchor clamps (that is: Himalia anchor clamps) by system application interface (System Application Program Interface is called for short System API);
Step 106, the downstream link of opening the PCIE anchor clamps wherein, is opened the downstream link of PCIE anchor clamps (that is: Himalia anchor clamps) by the buffer of control PEX8632 chip;
Step 107 is carried out extensive Complex by the PCIE configuration space that stores in advance to the PCIE configuration space of PCIE tab; And
Step 108, enable the PCIE tab or the driver of PCIE tab is installed, insert operation with the heat of finishing the PCIE tab, wherein, in Windows operating system, enable the PCIE tab, and be the driver that the PCIE tab is installed in (SuSE) Linux OS by system application interface (System API);
Step 109, when needs control PCIE tab is carried out hot drawing and is gone out to operate, can be at first by noticing that by next button (Attention Button) triggers a hot drawing and goes out signal, step 110, and then whether be inserted with the PCIE tab in the downstream interface of detection PCIE anchor clamps, wherein, described PCIE anchor clamps are the Himalia anchor clamps based on MSP430 chip and PEX8632 chip;
Step 111, after being inserted with the PCIE tab in the downstream interface that detects the PCIE anchor clamps, the driver of forbidding PCIE tab or unloading PCIE tab, wherein, in Windows operating system, forbid the PCIE tab, and in (SuSE) Linux OS, unload the driver of PCIE tab by system application interface (System API);
Step 112, the downstream of closing the PCIE anchor clamps links, and wherein, closes the downstream link of PCIE anchor clamps (that is: Himalia anchor clamps) by the buffer of control PEX8632 chip;
Step 113, the upstream device of forbidding PCIE anchor clamps wherein, is forbidden the upstream device of PCIE anchor clamps (that is: Himalia anchor clamps) by system application interface (System API) in Windows operating system;
Step 114, close the power supply of the downstream interface of PCIE anchor clamps, wherein, described power source voltage is respectively: SB10 3V3 AUX, SB8 3V3, SA9 3V3, SA10 3V3, SB1 12V, SB2 12V, SB3 12V, SA2 12V and SA3 12V, and its power pin is as shown in Figure 2; And
Step 115 is extracted the PCIE tab in the downstream interface of PCIE anchor clamps, goes out operation with the hot drawing of finishing the PCIE tab.
Please refer to Fig. 3 and Fig. 4 now, the PCIE anchor clamps that Fig. 3 uses for the Mining of institute in the hot plug control method of PCIE tab of the present invention and the syndeton calcspar of main frame and PCIE tab, Fig. 4 is the structure calcspar of the PCIE anchor clamps that the Mining of institute uses in the hot plug control method of PCIE tab of the present invention, as shown in Figures 3 and 4, the PCIE anchor clamps that the Mining of institute uses in the hot plug control method of PCIE tab of the present invention can be the Himalia anchor clamps 10 based on MSP430 chip and PEX8632 chip, wherein, the MSP430 chip can be used as core micro controller unit (Core MCU), and the PEX8632 chip then can be used as PCIE switch (PCIE Switch).
One end of Himalia anchor clamps 10 links to each other with PCIE slot on the main frame 20, the other end links to each other with PCIE tab 30, in order to the supply voltage by the control downstream interface and cooperate operating process in the hot plug control method of the present invention, and then realize the hot plug function of PCIE tab.
What also need here to specify a bit is exactly the means of communication of the core micro controller unit (that is: MSP430 chip) on application program (App) and the Himalia anchor clamps 10 of main frame 20, application program (App) is operated universal input and output (the General Purpose I/O of PCIE switch (that is: PEX8632 chip) by the PCIE configuration space of visit main frame 20, be called for short GPIO) buffer and utilize the GPIO buffer of PEX8632 chip to simulate serial circumference equipment interface (Serial Peripheral interface, be called for short SPI) agreement and then carry out communication with the core micro controller unit, that is, send various control commands and read corresponding execution result to the core micro controller unit.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; being familiar with those of ordinary skill in the art ought can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (8)
1. the hot plug control method of a quick peripheral device element interconnection tab, by being connected the hot plug function of quick this quick peripheral device element interconnection tab of peripheral device element interconnection anchor clamps control realization between an a main frame quick peripheral device element interconnection slot and the quick peripheral device element interconnection tab, this hot plug control method comprises following steps:
When opening main frame, store the quick peripheral device element interconnection configuration space of this quick peripheral device element interconnection tab in advance, to be used for that this quick peripheral device element interconnection configuration space is carried out extensive Complex at every turn;
When this quick peripheral device element interconnection tab of needs control is carried out heat insertion operation, detect the downstream interface whether this quick peripheral device element interconnection tab has inserted these quick peripheral device element interconnection anchor clamps earlier;
After detecting this quick peripheral device element interconnection tab and having inserted the downstream interface of these quick peripheral device element interconnection anchor clamps, open the power supply of the downstream interface of these quick peripheral device element interconnection anchor clamps;
Enable the upstream device of these quick peripheral device element interconnection anchor clamps;
Open the downstream link of these quick peripheral device element interconnection anchor clamps;
By this quick peripheral device element interconnection configuration space of storing in advance this quick peripheral device element interconnection configuration space of this quick peripheral device element interconnection tab is carried out extensive Complex;
Enable this quick peripheral device element interconnection tab or the driver of this quick peripheral device element interconnection tab is installed, insert operation with the heat of finishing this quick peripheral device element interconnection tab;
When this quick peripheral device element interconnection tab of needs control is carried out hot drawing and gone out to operate, detect in the downstream interface of these quick peripheral device element interconnection anchor clamps whether be inserted with this quick peripheral device element interconnection tab;
After being inserted with this quick peripheral device element interconnection tab in the downstream interface that detects these quick peripheral device element interconnection anchor clamps, forbidding this quick peripheral device element interconnection tab or unload the driver of this quick peripheral device element interconnection tab;
Close this downstream link of these quick peripheral device element interconnection anchor clamps;
Forbid this upstream device of these quick peripheral device element interconnection anchor clamps;
Close the power supply of the downstream interface of these quick peripheral device element interconnection anchor clamps; And
Extract this quick peripheral device element interconnection tab in the downstream interface of these quick peripheral device element interconnection anchor clamps, go out operation with the hot drawing of finishing this quick peripheral device element interconnection tab.
2. hot plug control method according to claim 1, wherein these quick peripheral device element interconnection anchor clamps are the Himalia anchor clamps based on a MSP430 chip and a PEX8632 chip.
3. this downstream link of these quick peripheral device element interconnection anchor clamps is wherein opened or close to hot plug control method according to claim 2 by the buffer of controlling this PEX8632 chip.
4. this upstream devices of this quick peripheral device element interconnection anchor clamps is wherein enabled or forbid to hot plug control method according to claim 1 by the system application interface in a Windows operating system.
5. this quick peripheral device element interconnection tab is enabled or forbidden to hot plug control method according to claim 1 wherein by the system application interface in a Windows operating system.
6. the driver of this quick peripheral device element interconnection tab is wherein installed or unload to hot plug control method according to claim 1 in (SuSE) Linux OS.
7. hot plug control method according to claim 1, wherein when this quick peripheral device element interconnection tab of needs control is carried out hot drawing and is gone out to operate, can be at first by noticing that by next button triggers a hot drawing and go out signal, and then detect in the downstream interface of these quick peripheral device element interconnection anchor clamps whether be inserted with this quick peripheral device element interconnection tab.
8. hot plug control method according to claim 1, wherein the power source voltage of the downstream interface of these quick peripheral device element interconnection anchor clamps is respectively: SB10 3V3 AUX, SB8 3V3, SA9 3V3, SA10 3V3, SB1 12V, SB2 12V, SB3 12V, SA2 12V and SA3 12V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102077543A CN102053939A (en) | 2009-10-30 | 2009-10-30 | Hot-plug control method of Peripheral Component Interconnect Express (PCIE) tab |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102077543A CN102053939A (en) | 2009-10-30 | 2009-10-30 | Hot-plug control method of Peripheral Component Interconnect Express (PCIE) tab |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102053939A true CN102053939A (en) | 2011-05-11 |
Family
ID=43958281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009102077543A Pending CN102053939A (en) | 2009-10-30 | 2009-10-30 | Hot-plug control method of Peripheral Component Interconnect Express (PCIE) tab |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102053939A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104679621A (en) * | 2013-11-28 | 2015-06-03 | 英业达科技有限公司 | Hot plug system and method thereof |
| CN104820646A (en) * | 2015-05-25 | 2015-08-05 | 烽火通信科技股份有限公司 | PCIE (peripheral component interface express) device dynamic scanning method supporting multi RC (remote control) in Linux system |
| CN105354162A (en) * | 2015-11-02 | 2016-02-24 | 烽火通信科技股份有限公司 | Method and apparatus for implementing hot-plug of PCIE device based on Linux |
| CN105474126A (en) * | 2013-09-27 | 2016-04-06 | 英特尔公司 | Improved power control techniques for integrated PCIE controllers |
| CN107341123A (en) * | 2017-07-25 | 2017-11-10 | 郑州云海信息技术有限公司 | A kind of method and system of PCIe card hot plug |
| CN107423169A (en) * | 2016-05-23 | 2017-12-01 | 百度（美国）有限责任公司 | For testing the method and system of high-speed peripheral interconnection equipment |
| CN109117406A (en) * | 2018-08-23 | 2019-01-01 | 郑州云海信息技术有限公司 | A kind of hot-swappable test method of PCIE, device, terminal and storage medium |
| CN111147401A (en) * | 2019-12-20 | 2020-05-12 | 苏州浪潮智能科技有限公司 | PHY card hot plug method and device |
| WO2021159651A1 (en) * | 2020-02-10 | 2021-08-19 | 苏州浪潮智能科技有限公司 | Control device for centralized power supply of server |
-
2009
- 2009-10-30 CN CN2009102077543A patent/CN102053939A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105474126A (en) * | 2013-09-27 | 2016-04-06 | 英特尔公司 | Improved power control techniques for integrated PCIE controllers |
| CN105474126B (en) * | 2013-09-27 | 2019-11-26 | 英特尔公司 | Improved power control techniques for integrated PCIE controller |
| CN104679621A (en) * | 2013-11-28 | 2015-06-03 | 英业达科技有限公司 | Hot plug system and method thereof |
| CN104820646B (en) * | 2015-05-25 | 2018-02-16 | 烽火通信科技股份有限公司 | More RC PCIE device dynamic scan method is supported under linux system |
| CN104820646A (en) * | 2015-05-25 | 2015-08-05 | 烽火通信科技股份有限公司 | PCIE (peripheral component interface express) device dynamic scanning method supporting multi RC (remote control) in Linux system |
| CN105354162A (en) * | 2015-11-02 | 2016-02-24 | 烽火通信科技股份有限公司 | Method and apparatus for implementing hot-plug of PCIE device based on Linux |
| CN107423169A (en) * | 2016-05-23 | 2017-12-01 | 百度（美国）有限责任公司 | For testing the method and system of high-speed peripheral interconnection equipment |
| CN107423169B (en) * | 2016-05-23 | 2022-05-13 | 百度（美国）有限责任公司 | Method and system for testing high speed peripheral device interconnection equipment |
| CN107341123A (en) * | 2017-07-25 | 2017-11-10 | 郑州云海信息技术有限公司 | A kind of method and system of PCIe card hot plug |
| CN109117406A (en) * | 2018-08-23 | 2019-01-01 | 郑州云海信息技术有限公司 | A kind of hot-swappable test method of PCIE, device, terminal and storage medium |
| CN109117406B (en) * | 2018-08-23 | 2022-02-18 | 郑州云海信息技术有限公司 | PCIE hot plug test method, device, terminal and storage medium |
| CN111147401A (en) * | 2019-12-20 | 2020-05-12 | 苏州浪潮智能科技有限公司 | PHY card hot plug method and device |
| WO2021159651A1 (en) * | 2020-02-10 | 2021-08-19 | 苏州浪潮智能科技有限公司 | Control device for centralized power supply of server |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102053939A (en) | Hot-plug control method of Peripheral Component Interconnect Express (PCIE) tab | |
| CN107423169B (en) | Method and system for testing high speed peripheral device interconnection equipment | |
| CN100377101C (en) | Method and apparatus for testing host computer board including interconnecting peripheries quickly | |
| KR20210065834A (en) | Partial link width states for bidirectional multilane links | |
| US20120311215A1 (en) | Peripheral component interconnect express expansion system and method | |
| JP2017510094A (en) | Interconnect retimer enhancements | |
| CN204331708U (en) | A kind of portable set and a kind of host computer system | |
| US9665513B2 (en) | Systems and methods for automatic root port to non-transparent bridge switching for a PCI express interconnect architecture | |
| TWI665390B (en) | Method of controlling a plurality of cooling fan modules, server system and non-transitory computer-readable storage medium | |
| US9317353B2 (en) | Method, apparatus and system for performing voltage margining | |
| CN102053898A (en) | Method for testing bus interface on PCIE (Peripheral Component Interface Express) slot of host and read-write test method thereof | |
| WO2017112046A1 (en) | Device, method and system for performing closed chassis debug with a repeater | |
| CN111124985A (en) | Read-only control method and device for mobile terminal | |
| CN114201360A (en) | AER function management method, device, server and storage medium | |
| CN1983204A (en) | Device and method for correcting and repairing BIOS function by LPC interface | |
| CN102467400A (en) | Control method on multiport network interface card | |
| US9158609B2 (en) | Universal serial bus testing device | |
| US11226757B2 (en) | Hot plug memory device data protection method | |
| CN104035844A (en) | Fault testing method and electronic device | |
| CN101452417B (en) | Monitor method and monitor device thereof | |
| US10346566B2 (en) | Method and device for simulating disk drive | |
| CN102467430A (en) | Universal serial bus (USB) test device and method | |
| CN105068962A (en) | I2C controller access method and I2C controller access system | |
| CN102421004B (en) | Debugging method and device for television software system | |
| CN111124970B (en) | Daughter board hot plug method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20110511 |