CN111124970B - Daughter board hot plug method and device - Google Patents
Daughter board hot plug method and device Download PDFInfo
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- CN111124970B CN111124970B CN201811285645.9A CN201811285645A CN111124970B CN 111124970 B CN111124970 B CN 111124970B CN 201811285645 A CN201811285645 A CN 201811285645A CN 111124970 B CN111124970 B CN 111124970B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The application provides a method and a device for hot plugging of a daughter board, wherein the method comprises the following steps: when a target daughter board is inserted into the target slot position, determining the type of the target daughter board; when the type of the target daughter board is determined to be a non-peripheral component high-speed interconnected PCIE daughter board, setting a hot plug mode of the target slot position to be a non-PCIE mode through the FPGA chip; and when a hot plug key signal corresponding to the target slot position is detected and the target daughter board is determined to be in a non-powered state, powering on the target daughter board through the FPGA chip. The method can realize the hot plug of the non-PCIE daughter board.
Description
Technical Field
The present application relates to communications technologies, and in particular, to a method and an apparatus for hot plugging a daughter board.
Background
A PCIE (Peripheral Component Interconnect Express) bus protocol itself supports hot plug of a daughter board, and in general, when a large number of daughter boards need to be connected, an IO-Expander (IO (Input/output) Expander) may be used for implementation.
As shown in fig. 1, in the multi-daughter board connection framework, a CPU (central processing Unit) may be connected to multiple IO-expanders through a PCIE bridge, so as to connect multiple daughter boards. The IO-Expander is an expansion chip of I2C-GPIO (General Purpose Input/Output), the CPU is connected with the PCIE bridge chip through a PCIE bus, and the PCIE bridge chip is connected with the IO-Expander through an I2C (Inter-Integrated Circuit, two-wire serial bus) bus; for the PICE daughter board, the PCIE bridge chip is also connected with the PCIE daughter board through the PCI downlink port.
The current multi-daughter board connection frame supports the hot plug of a PCIE daughter board, and the implementation process is as follows:
and (3) hot plug process: when the PCIE daughter board is inserted into the slot position, the PCIE bridge chip receives an interrupt signal, scans the IO-Expander state corresponding to the slot position, finds that the PCIE daughter board is on line, and updates the register state; at this time, if the hot plug key is pressed down, the PCIE bridge chip may receive a hot plug key signal, the CPU reads the hot plug key signal, and determines that the PCIE daughter board is hot-plugged when determining that the PCIE daughter board is in a non-powered state, at this time, the CPU powers on the PCIE daughter board through a register of the PCIE bridge chip, detects a PCIE connection state of the PCIE daughter board, and if normal, performs scanning and initializing PCI device operations.
And (3) hot drawing: if the hot plug key is pressed down, the PCIE bridge chip receives a hot plug key signal, the CPU reads the hot plug key signal, and when the PCIE daughter board is determined to be in a power-on state, the CPU determines that the PCIE daughter board is hot-plugged, at the moment, the CPU can unload all PCI resources of the PCIE daughter board, and power off is carried out on the PCIE daughter board through the PCIE register.
However, practice shows that the existing multi-sub-board connection framework only supports the hot plug of the PCIE sub-board, but cannot realize the hot plug of the non-PCIE sub-board.
Disclosure of Invention
In view of the above, the present application provides a method and an apparatus for hot plugging a daughter board.
Specifically, the method is realized through the following technical scheme:
according to a first aspect of the embodiments of the present application, a method for hot plugging a daughter board is provided, which is applied to a main control chip in a multi-daughter-board connection frame, wherein the multi-daughter-board connection frame further includes an FPGA chip, and the main control chip realizes multi-daughter-board connection through the FPGA chip; the method comprises the following steps:
when a target daughter board is inserted into the target slot position, determining the type of the target daughter board;
when the type of the target daughter board is determined to be a non-peripheral component high-speed interconnected PCIE daughter board, setting a hot plug mode of the target slot position to be a non-PCIE mode through the FPGA chip;
and when a hot plug key signal corresponding to the target slot position is detected and the target daughter board is determined to be in a non-powered state, powering on the target daughter board through the FPGA chip.
Optionally, the determining the type of the target daughter board includes:
and reading the value of a target daughter board type acquisition register corresponding to the target slot position in the FPGA chip, and determining the type of the target daughter board according to the value of the target daughter board type acquisition register.
Optionally, the reading a value of a target daughter board type obtaining register corresponding to the target slot in the FPGA chip, and determining the type of the target daughter board according to the value of the target daughter board type obtaining register includes:
and reading values of a power lamp control signal, a clock enable signal and a power failure detection signal corresponding to the target slot position, and determining the type of the target daughter board according to the values of the power lamp control signal, the clock enable signal and the power failure detection signal corresponding to the target slot position.
Optionally, the setting, by the FPGA chip, the hot plug mode of the target slot to the non-PCIE mode includes:
and when the type of the target daughter board is determined to be a non-peripheral component high-speed interconnected PCIE daughter board, setting the hot plug mode of the target slot position to be a non-PCIE mode through a target daughter board hot plug mode switching register corresponding to the target slot position on the FPGA chip.
Optionally, the powering on the target daughter board through the FPGA chip includes:
and when a hot plug key signal corresponding to the target slot position is detected and the target daughter board is determined to be in an unpowered state, powering on the target daughter board through a target daughter board power supply control register corresponding to the target slot position on the FPGA chip.
Optionally, after the target daughter board is powered on by the FPGA chip, the method further includes:
and setting a value of a target daughter board slot position identification SlotID register corresponding to the target slot position on the FPGA chip according to the slot position number of the target slot position, so that the target daughter board determines the slot position number of the target slot position according to the value of the target daughter board SlotID register, and sets the ID of the target daughter board according to the slot position number of the target slot position.
Optionally, the setting, according to the slot number of the target slot, a value of a target daughter board slot identifier SlotID register corresponding to the target slot on the FPGA chip includes:
and setting values of a power lamp control signal, a clock enabling signal and a power failure detection signal corresponding to the target slot position according to the slot position number of the target slot position.
Optionally, after the target daughter board is powered on, the method further includes:
when the hot plug key signal corresponding to the target slot position is detected, reading the value of the target daughter board hot plug mode switching register;
and when the hot plug mode of the target slot position is a non-PCIE mode and the target daughter board is in a power-on state, the target daughter board is powered off through the target daughter board power supply control register.
Optionally, after the power of the target daughter board is cut off through the target daughter board power supply control register, the method further includes:
and setting the hot plug mode of the target slot position to be a PCIE mode through the target daughter board hot plug mode switching register.
According to a second aspect of the embodiments of the present application, a daughter board hot plug device is provided, which is applied to a main control chip in a multi-daughter board connection frame, and is characterized in that the multi-daughter board connection frame further includes an FPGA chip, and the main control chip realizes multi-daughter board connection through the FPGA chip; the device comprises: the device comprises a detection unit, a determination unit, a setting unit and a control unit; wherein:
the determining unit is used for determining the type of the target daughter board when the target daughter board is detected to be inserted into the target slot position;
the setting unit is used for setting the hot plug mode of the target slot position to be a non-PCIE mode through the FPGA chip when the determining unit determines that the type of the target daughter board is a non-peripheral component high-speed interconnected PCIE daughter board;
the control unit is used for electrifying the target daughter board through the FPGA chip when the detection unit detects a hot plug key signal corresponding to the target slot position and the determination unit determines that the target daughter board is in an unpowered state.
Optionally, the apparatus further comprises: a reading unit; wherein:
the reading unit is used for reading the value of a target daughter board type acquisition register corresponding to the target slot position in the FPGA chip;
the determining unit is specifically configured to determine the type of the target daughter board according to the value of the target daughter board type obtaining register.
Optionally, the reading unit is specifically configured to read values of a power lamp control signal, a clock enable signal, and a power failure detection signal corresponding to the target slot;
the determining unit is specifically configured to determine the type of the target daughter board according to values of a power lamp control signal, a clock enable signal, and a power failure detection signal corresponding to the target slot.
Optionally, the setting unit is specifically configured to set the hot plug mode of the target slot to the non-PCIE mode through a target daughter board hot plug mode switch register corresponding to the target slot on the FPGA chip when the determining unit determines that the type of the target daughter board is the non-peripheral component high-speed interconnect PCIE daughter board.
Optionally, the control unit is specifically configured to power on the target daughter board through a target daughter board power control register corresponding to the target slot on the FPGA chip when the detection unit detects a hot plug key signal corresponding to the target slot and the determination unit determines that the target daughter board is in an unpowered state.
Optionally, the setting unit is further configured to set a value of a target daughter board slot identification SlotID register corresponding to the target slot on the FPGA chip according to the slot number of the target slot, so that the target daughter board determines the slot number of the target slot according to the value of the target daughter board SlotID register, and sets an ID of the target daughter board according to the slot number of the target slot.
Optionally, the setting unit is specifically configured to set values of a power lamp control signal, a clock enable signal, and a power failure detection signal corresponding to the target slot according to the slot number of the target slot.
Optionally, the reading unit is further configured to read a value of the target daughter board hot plug mode switching register when the detecting unit detects a hot plug key signal corresponding to the target slot;
the control unit is further configured to power off the target daughter board through the target daughter board power control register when the hot plug mode of the target slot is the non-PCIE mode and the target daughter board is in a power-on state.
Optionally, the setting unit is further configured to set the hot plug mode of the target slot to the PCIE mode through the target daughter board hot plug mode switching register.
The daughter board hot plug method of the embodiment of the application realizes IO-Expander by using the FPGA chip, when the main control chip detects that the target daughter board is inserted into the target slot, the type of the target daughter board is determined, when the type of the target daughter board is determined to be a non-PCIE daughter board, the hot plug mode of the target slot is set to be a non-PCIE mode through the FPGA chip, and when a hot plug key signal corresponding to the target slot is detected and the target daughter board is determined to be in a non-power-on state, the target daughter board is powered on through the FPGA chip, so that the hot plug of the non-PCIE daughter board is realized.
Drawings
FIG. 1 is a schematic diagram of a typical multi-daughter board connection frame;
FIG. 2 is a block diagram illustrating a multi-daughter board connection frame according to an exemplary embodiment of the present application;
FIG. 3 is a flowchart illustrating a method for hot-plugging a daughter board according to an exemplary embodiment of the present disclosure;
FIG. 4 is an architectural diagram illustrating a specific application scenario in an exemplary embodiment of the present application;
FIG. 5 is a schematic diagram illustrating a configuration of a daughter board hot swap device according to an exemplary embodiment of the present application;
fig. 6 is a schematic structural diagram of a daughter board hot plug device according to still another exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
In order to make those skilled in the art better understand the technical solutions provided by the embodiments of the present application, a brief description will be given below of a multi-daughter board connection frame provided by the embodiments of the present application.
Referring to fig. 2, a schematic structural diagram of a multi-daughter board connection frame according to an embodiment of the present disclosure is shown in fig. 2, where the multi-daughter board connection frame may include a main control chip (e.g., a CPU), a PCIE bridge chip, and an FPGA chip.
In the multi-daughter board connection frame shown in fig. 2, to implement hot plug of a non-PCIE daughter board, IO-Expander is implemented by an FPGA chip, one FPGA chip may include multiple IO-expanders, and a main control chip may implement multi-daughter board connection by the FPGA chip.
In the multi-daughter board connection frame shown in fig. 2, a module for hot plug control of daughter boards (including PCIE daughter boards and non-PCIE daughter boards) is disposed on an FPGA chip, and the module includes a daughter board type acquisition register, a daughter board hot plug mode switching register, a daughter board slot id (slot identifier) configuration register, and a daughter board power control register, which respectively correspond to each IO-Expander.
The main control chip is connected with the FPGA chip through a bus (the type of the bus is not limited), and can read or/and set the value of a register in the FPGA chip so as to control the hot plug of the daughter board.
In order to make the aforementioned objects, features and advantages of the embodiments of the present application more comprehensible, embodiments of the present application are described in detail below with reference to the accompanying drawings.
Referring to fig. 3, a schematic flow chart of a daughter board hot plug method provided in an embodiment of the present application is shown, where the daughter board hot plug method may be applied to a main control chip in a multi-daughter board connection frame (for example, the main control chip in the multi-daughter board connection frame shown in fig. 2), and the main control chip implements multi-daughter board connection through an FPGA chip, as shown in fig. 3, the daughter board hot plug method may include the following steps:
and step S300, when the target daughter board is inserted into the target slot position, determining the type of the target daughter board.
In the embodiment of the present application, the target slot is not specifically referred to a fixed slot, but may refer to any slot in the multi-daughter board connection frame, and the following description of the embodiment of the present application is not repeated.
The slot positions in the multi-daughter-board connecting frame correspond to the IO-expanders one by one.
In the embodiment of the application, the daughter board inserted by the multi-daughter-board connection frame is the PCIE daughter board by default, and therefore, when a daughter board (referred to as a target daughter board herein) is inserted in the target slot, the master control chip may obtain a signal inserted by the target daughter board by reading the register of the PCIE bridge chip.
When the main control chip detects that the target daughter board is inserted into the target slot, the main control chip can determine the type of the target daughter board.
In one example, the main control chip may obtain a value of a daughter board type obtaining register (referred to herein as a target daughter board type obtaining register) corresponding to the target slot in the FPGA chip by reading the value, and determine the type of the target daughter board according to the value of the target daughter board type obtaining register.
In one embodiment of the present application, the reading a value of a target daughter board type obtaining register corresponding to the target slot in the FPGA chip, and determining the type of the target daughter board according to the value of the target daughter board type obtaining register may include:
and reading values of a power lamp control signal, a clock enable signal and a power failure detection signal corresponding to the target slot position, and determining the type of the target daughter board according to the values of the power lamp control signal, the clock enable signal and the power failure detection signal corresponding to the target slot position.
In this embodiment, it is considered that three signals, namely, a power supply lamp control signal, a clock enable signal and a power failure detection signal, are not required for a non-PCIE daughter board, and for a PCIE daughter board, values of the three signals are all 0 in a normal case, so that the type of the daughter board can be identified by the values of the three signals, that is, when the values of the three signals are all 0, it is determined that the inserted daughter board is a PCIE daughter board, and when the values of the three signals are not all 0, it is determined that the inserted daughter board is a non-PCIE daughter board.
The correspondence between the values of the three signals and the specific type of the non-PCIE daughter board is not limited herein.
In this embodiment, when the non-PCIE daughter board is inserted into the slot, the multi-daughter board connection frame may set the values of the power supply lamp control signal, the clock enable signal, and the power failure detection signal to values matched with the type of the non-PCIE daughter board through hardware.
Correspondingly, when the main control chip detects that the target daughter board is inserted into the target slot position, the main control chip can read the values of the power lamp control signal, the clock enable signal and the power failure detection signal corresponding to the target slot position, and determine the type of the target daughter board according to the values of the power lamp control signal, the clock enable signal and the power failure detection signal corresponding to the target slot position.
And S310, when the type of the target daughter board is determined to be the PCIE daughter board, setting the hot plug mode of the target slot position to be a non-PCIE mode through the FPGA chip.
In the embodiment of the application, when the main control chip determines that the type of the target daughter board is the PCIE daughter board, the hot plug mode of the target slot may be set to the non-PCIE mode through the FPGA chip.
In one example, the main control chip may set the hot plug mode of the target slot to the non-PICE mode through a daughter board hot plug mode switch register (referred to herein as a target daughter board hot plug mode switch register) corresponding to the target slot on the FPGA.
For example, if it is assumed that the value of the daughter board hot plug mode switch register is 0, it indicates that the daughter board requiring hot plug is a PCIE daughter board, and when the value of the daughter board hot plug mode switch register is 1, it indicates that the daughter board requiring hot plug is a non-PCIE daughter board, the initial value of the daughter board hot plug mode switch register corresponding to each slot on the FPGA chip may be 0, and when the CPU detects that the target daughter board is inserted into the target slot and determines that the target daughter board is a non-PCIE daughter board, the value of the daughter board hot plug mode switch register may be set to 1 (i.e., a non-PCIE mode value).
And step S320, when the hot plug key signal corresponding to the target slot position is detected and the target daughter board is determined to be in a non-power-on state, powering on the target daughter board through the FPGA chip.
In the embodiment of the application, when the target daughter board needs to be hot-plugged, the hot-plugging key corresponding to the target slot position is pressed.
Correspondingly, when the main control chip detects the hot plug key signal corresponding to the target slot position, the power state (powered-on state or unpowered-off state) of the target daughter board can be detected.
When the target daughter board is in a non-powered state, the main control chip can determine that hot plug processing needs to be performed on the target daughter board, and at the moment, the main control chip can power on the target daughter board through the FPGA chip.
For example, the main control chip may power up the target daughter board through a daughter board power control register (referred to herein as a target daughter board power control register) corresponding to the target slot on the FPGA.
Further, in one of the embodiments, after the main control chip powers on the target slot, a value of a target slot ID register corresponding to the target slot on the FPGA chip may be set according to the slot number of the target slot, so that the target slot determines the slot number of the target slot according to the value of the target slot ID register, and sets its own ID according to the slot number of the target slot.
In this embodiment, it is considered that ID setting is required before normal operation after the daughter board is inserted into the slot, for example, an IP (Internet protocol) address and a MAC (Media Access Control) are required to be set for the network daughter board, and the ID of the daughter board may be set according to the slot where the daughter board is located, so that it is required to obtain information about the slot where the daughter board is located after the daughter board is inserted into the slot.
Correspondingly, in this embodiment of the application, after the main control chip powers on the target daughter board, a value of a daughter board SlotID register (referred to as a target daughter board SlotID register herein) corresponding to the target slot position on the FPGA chip may also be set according to the slot number of the target slot position.
The target daughter board can determine the slot number of the slot where the target daughter board is located (namely, the target slot) by reading the value of the SlotID register of the target daughter board, and set the ID of the target daughter board according to the slot number of the target slot.
In one embodiment of the present application, setting a value of a target daughter board SlotID register corresponding to the target slot on the FPGA chip according to the slot number of the target slot may include:
and setting values of a power lamp control signal, a clock enabling signal and a power failure detection signal corresponding to the target slot position according to the slot position number of the target slot position.
In this embodiment, after the main control chip powers on the target daughter board, values of the power lamp control signal, the clock enable signal, and the power failure detection signal corresponding to the target slot may be used to identify the slot number of the target slot.
Correspondingly, the main control chip can set the values of the power lamp control signal, the clock enable signal and the power failure detection signal corresponding to the target slot position according to the slot position number of the target slot position; furthermore, the target sub-board can determine the slot number of the target slot by reading the values of the power lamp control signal, the clock enable signal and the power failure detection signal corresponding to the target slot, and set the ID of the target sub-board according to the slot number of the target slot, so that the non-PCIE sub-board is completed by hot plug.
Further, in one embodiment of the present application, after the target daughter board is powered on, the method may further include:
when a hot plug key signal corresponding to the target slot position is detected, reading the value of a hot plug mode switching register of the target daughter board;
and when the hot plug mode of the target slot position is a non-PCIE mode and the target daughter board is in a power-on state, the target daughter board is powered off through the target daughter board power supply control register.
In this embodiment, when the daughter board needs to be hot-unplugged, the hot-plug button is pressed again.
When the main control chip detects a hot plug key signal corresponding to the target slot, the main control chip may detect a hot plug mode (PCIE mode or non-PCIE mode) of the target slot.
When the main control chip determines that the hot plug mode of the target slot position is the non-PCIE mode, the main control chip can further detect the power state of the target daughter board, if the target daughter board is in the power-on state, the main control chip determines that hot plug processing needs to be carried out on the target daughter board, and at the moment, the main control chip can carry out power failure on the target daughter board through the target daughter board power control register.
Further, in this embodiment, in order to be compatible with a PCIE daughter board hot plug implementation scheme in the existing multi-daughter board connection frame, after the main control chip powers off the target daughter board, the hot plug mode of the target slot may be set to the PCIE mode through the target daughter board hot plug mode switching register, so that when the daughter board is inserted into the target slot again, the PCIE bridge chip may receive the interrupt signal and update the state of the register, and then the main control chip may determine that there is daughter board insertion according to the register that reads the PCIE bridge chip, and then process the daughter board insertion according to the manner described in step S300 to step S330.
In order to enable those skilled in the art to better understand the technical solutions provided in the embodiments of the present application, the following describes the technical solutions provided in the embodiments of the present application with reference to specific application scenarios.
Referring to fig. 4, for an architecture diagram of a specific application scenario provided in the embodiment of the present application, as shown in fig. 4, in the application scenario, taking a non-PCIE daughter board as a network daughter board, a bus between a CPU and an FPGA chip has a bus connection of an unlimited type in addition to a PCIE bus (the CPU is connected to a PCIE bridge chip through a PCIE bus, and the PCIE bridge chip is connected to the FPGA chip through an I2C bus).
In the application scenario shown in fig. 4, the PCIE daughter board is inserted by default, and therefore, the CPU may obtain a signal inserted into the daughter board through the register of the PCIE bridge chip.
In the hot plug process, when the CPU detects a signal of the daughter board insertion, the value of the corresponding daughter board type acquisition register may be read, that is, the values of the power supply lamp control signal, the clock enable signal, and the power supply failure detection signal are read. If the number of the daughter boards is 0, determining that the type of the daughter board is a PCIE daughter board; and if not, determining that the type of the daughter board is a non-PCIE daughter board.
The specific correspondence relationship between the values of the network daughter board and the power lamp control signal, the clock enable signal, and the power failure detection signal is not limited herein.
In this embodiment, when the CPU determines that the type of the inserted daughter board is the network daughter board, the CPU may set the hot plug mode of the slot where the network daughter board is inserted to the non-PCIE mode through the corresponding daughter board hot plug mode switching register.
When the hot plug key corresponding to the slot position into which the network daughter board is inserted is pressed, the CPU can detect a hot plug key signal, at the moment, the network daughter board can detect the power state of the network daughter board, if the power state is not powered on, the CPU can power on the network daughter board through the corresponding daughter board power control register, and the value of the corresponding daughter board SlotID register is set according to the slot position number of the slot position into which the network daughter board is inserted.
The network daughter board reads the value of the corresponding daughter board SlotID register, determines the slot position number of the slot position where the network daughter board is located according to the value of the daughter board SlotID register, configures the IP address and the MAC address of the network daughter board according to the slot position number, and completes hot plug of the network daughter board.
The network daughter board can inquire the corresponding relation between the slot position number and the IP address and the corresponding relation between the slot position number and the MAC address according to the slot position number of the slot position where the network daughter board is located, so as to determine the IP address and the MAC address of the network daughter board, and configure the IP address and the MAC address.
When the CPU detects the hot plug key signal corresponding to the slot where the network daughter board is located again, the CPU can detect the hot plug mode of the slot, if the slot is in the non-PCIE mode, the CPU can cut off the power of the network daughter board through the corresponding daughter board power control register, the hot plug mode of the slot is set to be the PCIE mode, and the hot plug of the network daughter board is completed.
Therefore, in the embodiment of the application, on the basis of the hot plug of the PCIE daughter board, the hardware of the main control chip and the switching system does not need to be modified, and the uniform hot plug operation of the non-PCIE daughter board is realized, so that a user can realize uniform hot plug without distinguishing which type of daughter board is used.
It should be noted that, in the embodiment of the present application, for specific implementation of hot plug of a PCIE daughterboard, reference may be made to relevant description in a hot plug scheme of a PCIE daughterboard in an existing multi-daughterboard connection frame, and details of the embodiment of the present application are not described herein again.
In addition, for a PCIE daughter board or a non-PCIE daughter board, the signal connection between the FPGA chip and the daughter board that needs hot plugging is the same, that is, both include: the system comprises a power supply control signal, a power supply lamp control signal, a clock enabling signal, a power supply state detection signal, a power supply fault detection signal, a daughter board reset signal and a key signal.
For a non-PCIE daughterboard, except that the power supply lamp control signal, the clock enable signal, and the power failure detection signal may be used for the daughterboard type identifier and the slot identifier according to the manner described in the above embodiment, the functions of the other signals may be the same as those in the PCIE daughterboard hot plug flow, which is not described herein again in this embodiment of the application.
In the embodiment of the application, IO-Expander is realized by using the FPGA chip, when the main control chip detects that the target daughter board is inserted into the target slot, the type of the target daughter board is determined, when the type of the target daughter board is determined to be a non-PCIE daughter board, the hot plug mode of the target slot is set to be a non-PCIE mode through the FPGA chip, and when a hot plug key signal corresponding to the target slot is detected and the target daughter board is determined to be in a non-power-on state, the target daughter board is powered on through the FPGA chip, so that the hot plug of the non-PCIE daughter board is realized.
The methods provided herein are described above. The following describes the apparatus provided in the present application:
referring to fig. 5, a schematic structural diagram of a daughter board hot plug device provided in an embodiment of the present application is shown, where the daughter board hot plug device may be applied to a main control chip in the foregoing method embodiment, and as shown in fig. 5, the daughter board hot plug device may include: a detection unit 510, a determination unit 520, a setting unit 530, and a control unit 540; wherein:
the determining unit 520 is configured to determine the type of the target daughter board when the detecting unit 510 detects that the target daughter board is inserted into the target slot;
the setting unit 530 is configured to set, when the determining unit 520 determines that the type of the target daughter board is a non-Peripheral Component Interconnect Express (PCIE) daughter board, a hot plug mode of the target slot to a non-PCIE mode through the FPGA chip;
the control unit 540 is configured to power on the target daughter board through the FPGA chip when the detection unit 510 detects a hot plug key signal corresponding to the target slot and the determination unit 520 determines that the target daughter board is in an unpowered state.
In an alternative embodiment, as shown in fig. 6, the apparatus further comprises: a reading unit 550; wherein:
the reading unit 550 is configured to read a value of a target daughter board type acquisition register corresponding to the target slot in the FPGA chip;
the determining unit 520 is specifically configured to determine the type of the target daughter board according to the value of the target daughter board type obtaining register.
In an optional embodiment, the reading unit 550 is specifically configured to read values of a power lamp control signal, a clock enable signal, and a power failure detection signal corresponding to the target slot;
the determining unit 520 is specifically configured to determine the type of the target daughter board according to values of the power lamp control signal, the clock enable signal, and the power failure detection signal corresponding to the target slot.
In an optional implementation manner, the setting unit 530 is specifically configured to set, when the determining unit 520 determines that the type of the target daughter board is a non-peripheral component interconnect express PCIE daughter board, a hot plug mode of the target slot to be a non-PCIE mode through a target daughter board hot plug mode switch register corresponding to the target slot on the FPGA chip.
In an optional implementation manner, the control unit 540 is specifically configured to power on the target daughter board through a target daughter board power control register corresponding to the target slot on the FPGA chip when the detection unit 510 detects a hot plug key signal corresponding to the target slot and the determination unit 520 determines that the target daughter board is in an unpowered state.
In an optional implementation manner, the setting unit 530 is further configured to set a value of a target daughter board slot identifier SlotID register, corresponding to the target slot, on the FPGA chip according to the slot number of the target slot, so that the target daughter board determines the slot number of the target slot according to the value of the target daughter board SlotID register, and sets its own ID according to the slot number of the target slot.
In an optional embodiment, the setting unit 530 is specifically configured to set values of a power lamp control signal, a clock enable signal, and a power failure detection signal corresponding to the target slot according to a slot number of the target slot.
In an optional implementation manner, the reading unit 550 is further configured to read a value of the target daughter board hot plug mode switch register when the detecting unit 510 detects a hot plug key signal corresponding to the target slot;
the control unit 540 is further configured to power off the target daughter board through the target daughter board power control register when the hot plug mode of the target slot is the non-PCIE mode and the target daughter board is in a power-on state.
In an optional implementation manner, the setting unit 530 is further configured to set the hot plug mode of the target slot to the PCIE mode through the target daughter board hot plug mode switch register.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (18)
1. A hot plug method of daughter boards is applied to a main control chip in a multi-daughter board connection frame, and is characterized in that the multi-daughter board connection frame also comprises a Field Programmable Gate Array (FPGA) chip, and the main control chip realizes multi-daughter board connection through the FPGA chip; the method comprises the following steps:
when a target daughter board is inserted into the target slot position, determining the type of the target daughter board;
when the type of the target daughter board is determined to be a non-peripheral component high-speed interconnected PCIE daughter board, setting a hot plug mode of the target slot position to be a non-PCIE mode through the FPGA chip;
and when a hot plug key signal corresponding to the target slot position is detected and the target daughter board is determined to be in a non-powered state, powering on the target daughter board through the FPGA chip.
2. The method of claim 1, wherein the determining the type of the target daughter board comprises:
and reading the value of a target daughter board type acquisition register corresponding to the target slot position in the FPGA chip, and determining the type of the target daughter board according to the value of the target daughter board type acquisition register.
3. The method of claim 2, wherein the reading a value of a target daughter board type obtaining register corresponding to the target slot in the FPGA chip and determining the type of the target daughter board according to the value of the target daughter board type obtaining register comprises:
and reading values of a power lamp control signal, a clock enable signal and a power failure detection signal corresponding to the target slot position, and determining the type of the target daughter board according to the values of the power lamp control signal, the clock enable signal and the power failure detection signal corresponding to the target slot position.
4. The method of claim 1, wherein the setting, by the FPGA chip, the hot plug mode of the target slot to the non-PCIE mode comprises:
and when the type of the target daughter board is determined to be a non-peripheral component high-speed interconnected PCIE daughter board, setting the hot plug mode of the target slot position to be a non-PCIE mode through a target daughter board hot plug mode switching register corresponding to the target slot position on the FPGA chip.
5. The method of claim 1, wherein said powering up the target daughter board by the FPGA chip comprises:
and when a hot plug key signal corresponding to the target slot position is detected and the target daughter board is determined to be in an unpowered state, powering on the target daughter board through a target daughter board power supply control register corresponding to the target slot position on the FPGA chip.
6. The method of claim 1, after the target daughter board is powered up by the FPGA chip, further comprising:
and setting a value of a target daughter board slot position identification SlotID register corresponding to the target slot position on the FPGA chip according to the slot position number of the target slot position, so that the target daughter board determines the slot position number of the target slot position according to the value of the target daughter board SlotID register, and sets the ID of the target daughter board according to the slot position number of the target slot position.
7. The method of claim 6, wherein the setting a value of a target daughter board slot identification (SlotID) register on the FPGA chip corresponding to the target slot according to the slot number of the target slot comprises:
and setting values of a power lamp control signal, a clock enabling signal and a power failure detection signal corresponding to the target slot position according to the slot position number of the target slot position.
8. The method of claim 4, wherein after powering up the target daughter board, further comprising:
when the hot plug key signal corresponding to the target slot position is detected, reading the value of the target daughter board hot plug mode switching register;
and when the hot plug mode of the target slot position is a non-PCIE mode and the target daughter board is in a power-on state, the target daughter board is powered off through the target daughter board power supply control register.
9. The method of claim 8, wherein after powering down the target daughter board via the target daughter board power control register, further comprising:
and setting the hot plug mode of the target slot position to be a PCIE mode through the target daughter board hot plug mode switching register.
10. A hot plug device for a daughter board is applied to a main control chip in a multi-daughter-board connecting frame and is characterized in that the multi-daughter-board connecting frame also comprises a Field Programmable Gate Array (FPGA) chip, and the main control chip realizes multi-daughter-board connection through the FPGA chip; the device comprises: the device comprises a detection unit, a determination unit, a setting unit and a control unit; wherein:
the determining unit is used for determining the type of the target daughter board when the detecting unit detects that the target daughter board is inserted into the target slot position;
the setting unit is used for setting the hot plug mode of the target slot position to be a non-PCIE mode through the FPGA chip when the determining unit determines that the type of the target daughter board is a non-peripheral component high-speed interconnected PCIE daughter board;
the control unit is used for electrifying the target daughter board through the FPGA chip when the detection unit detects a hot plug key signal corresponding to the target slot position and the determination unit determines that the target daughter board is in an unpowered state.
11. The apparatus of claim 10, further comprising: a reading unit; wherein:
the reading unit is used for reading the value of a target daughter board type acquisition register corresponding to the target slot position in the FPGA chip;
the determining unit is specifically configured to determine the type of the target daughter board according to the value of the target daughter board type obtaining register.
12. The apparatus of claim 11,
the reading unit is specifically configured to read values of a power lamp control signal, a clock enable signal, and a power failure detection signal corresponding to the target slot;
the determining unit is specifically configured to determine the type of the target daughter board according to values of a power lamp control signal, a clock enable signal, and a power failure detection signal corresponding to the target slot.
13. The apparatus of claim 10,
the setting unit is specifically configured to set the hot plug mode of the target slot to the non-PCIE mode through a target daughter board hot plug mode switch register corresponding to the target slot on the FPGA chip when the determination unit determines that the type of the target daughter board is the non-peripheral component high-speed interconnect PCIE daughter board.
14. The apparatus of claim 10,
the control unit is specifically configured to power on the target daughter board through a target daughter board power control register corresponding to the target slot on the FPGA chip when the detection unit detects a hot plug key signal corresponding to the target slot and the determination unit determines that the target daughter board is in an unpowered state.
15. The apparatus of claim 10,
the setting unit is further configured to set a value of a target daughter board slot identification SlotID register corresponding to the target slot on the FPGA chip according to the slot number of the target slot, so that the target daughter board determines the slot number of the target slot according to the value of the target daughter board SlotID register, and sets its own ID according to the slot number of the target slot.
16. The apparatus of claim 15,
the setting unit is specifically configured to set values of a power lamp control signal, a clock enable signal and a power failure detection signal corresponding to the target slot according to the slot number of the target slot.
17. The apparatus of claim 13,
the reading unit is further used for reading the value of the target daughter board hot plug mode switching register when the detection unit detects the hot plug key signal corresponding to the target slot position;
the control unit is further configured to power off the target daughter board through the target daughter board power control register when the hot plug mode of the target slot is the non-PCIE mode and the target daughter board is in a power-on state.
18. The apparatus of claim 17,
the setting unit is further configured to set the hot plug mode of the target slot to the PCIE mode through the target daughter board hot plug mode switching register.
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| CN107341123A (en) * | 2017-07-25 | 2017-11-10 | 郑州云海信息技术有限公司 | A kind of method and system of PCIe card hot plug |
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| CN106155970A (en) * | 2015-05-11 | 2016-11-23 | 广达电脑股份有限公司 | Automatically hardware recovery method and automatically hardware recovery system |
| CN108647169A (en) * | 2018-05-14 | 2018-10-12 | 杭州宏杉科技股份有限公司 | A kind of hot plug processing method and processing device |
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