CN102047403A - 电子器件及电子器件的制造方法 - Google Patents
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Abstract
本发明涉及一种电子器件,所述电子器件包括嵌入在衬底中的集成电路(1),其中所述衬底至少包括设置在集成电路(1)相反两侧上的第一(3)和第二(9)导电结构,以及经由在衬底中的孔洞(8)建立第一(3)和第二(9)导电结构之间和/或与集成电路(1)之间的电连接(10、11、12和13)。
Description
技术领域
本发明涉及一种包括嵌入衬底中的集成电路的电子器件。
此外,本发明涉及一种制造电子器件的方法。
背景技术
在本发明范围内的电子器件,特别是用于射频识别(RFID)应用的智能卡通常包括封装在模块中的集成电路,所述集成电路然后与天线相连,并且随后集成于卡体中。对于标准卡,通常所述模块与附着到衬底箔粘合,通过焊接工艺将绝缘导线天线嵌入并且粘合在所述衬底箔中。该衬底箔被称作嵌体,在单独的步骤中将所述衬底箔层压到最终的RFID卡中。
另一种生产嵌体的替代方法采用所谓的直接芯片粘合工艺。在这种情况下,天线包括导电材料形成的结构层,例如薄金属箔、导电油墨、电镀镀层等,所述集成电路经由如倒装芯片工艺与天线直接连接。
例如,WO 2007/075352A2公开了一种用于组装电子器件的方法,特别是用于RFID插入物和/或器件的组装。该已知方法包括将带有键合焊盘(例如隆起焊盘)的芯片热嵌入在衬底中并将芯片与所述衬底上表面上的天线元件相连。在该过程中,在衬底层表面上设置天线结构的步骤与将天线结构与芯片相接触的步骤彼此独立,因而造成了程序上的不便。
为了使芯片与天线结构相连,压缩了组装。在压缩期间,芯片的隆起焊盘穿透衬底,以便与衬底上表面上的天线结构建立接触。在压缩期间,将相当大的应力施加于芯片的键合焊盘或隆起焊盘区域,使得在隆起焊盘邻近或者隆起焊盘下面的区域中不设置芯片的精细结构,通常芯片应该具有足以提供必要强度的厚度。
在所有描述的方法中,实际收发机嵌体都不是平坦的,因此需要增加附加层以补偿厚度上的差异,提供镶嵌标签,随后再次层压或胶粘在最终的卡中。采用模块的结构目前能够达到的最小厚度约为300μm。采用直接芯片粘合的结构也有缺点,即在层压工艺期间集成电路或多或少未被保护,这将集成电路厚度限制在100μm左右,以便给出合理的管芯强度值。假如是倒装芯片工艺,则要求附加的隆起焊盘,这也被视为影响成品机械可靠性的关键,因为隆起焊盘下方的应力集中很高。
另一个问题是天线的制造,特别是建立用于连接天线的两个末端的桥接。用于智能卡嵌体的天线通常通过印制或者刻蚀工艺制造。然后,所述集成电路直接与天线连接(直接芯片粘合),从而通过不同方法完成所述桥接。如果天线由印制工艺制造,通常绝缘层和附加迹线在附加工艺步骤中印制以建立桥接。如果天线由刻蚀工艺制造,天线衬底的两侧将被构图然后被电连接。
替代地,集成电路封装在模块或者插入件中,要求集成电路与模块的引线(例如通过引线键合)或者插入件(倒装芯片工艺)的电相连。这样,插入件也可以用作桥接。
上述所有制造方法存在的共同问题是天线制造工艺要求若干个步骤。假如使用了插入件或者模块,制造工艺甚至更加复杂,因为还需要在集成电路与引线之间以及在引线与天线之间建立附加互连。特别是对于超薄嵌体或者镶嵌标签的实现,薄型集成电路的处理是困难的。此外,薄型集成电路公知是光敏的,可能不得不应用保护层。
因此,本发明的目的旨在提供一种电子器件,特别是用于RFID应用的智能卡,所述电子器件具有改进的天线桥接设计,因其简单、结实、尤其是超薄的结构而表现突出。另外,电子器件的生产简单、成本低,特别是简化了许多工艺步骤。
因此,本发明的另一个目的是提供一种制造上述电子器件的方法,特别是用于RFID应用的智能卡,所述方法采用尽最少的工艺步骤,并能解决关于天线桥接而存在的问题。
发明内容
本发明的目的是通过一种如权利要求1中阐述的电子器件来实现。
本发明的目的还通过一种如权利要求14中阐述的电子器件制造方法来实现。
本发明的其他优点通过在从属权利要求中阐述的特征来实现。
根据本发明,所述电子器件包括嵌入在衬底中的集成电路,其中所述衬底具有设置在集成电路相反两侧上的至少第一和第二导电结构,以及经由衬底中的孔洞建立第一和第二导电结构之间和/或与集成电路之间的电连接。通过在衬底中设置和实现集成电路以及第一和第二导电结构这种构造,也实现了特别紧凑的设计,其中所述集成电路被完全保护起来免受外界的影响。因为第一和第二导电结构设置在集成电路的相反两侧,使得直接在衬底上或衬底中设置例如天线结构成为可能,从而假如根据本发明的优选实施例,第一导电结构在第二导电结构的两个区域之间形成了导电桥接是特别有优势的。因此,其中一个导电结构可以形成天线,位于集成电路相反一侧的另外一个导电结构可以形成桥接,用于连接天线的两个相距末端或者区域。所述桥接作为衬底中的附加层得以实现,并未明显增加设计的复杂性。同时,所述桥接层可用于增加衬底的稳定性,可以作为集成电路的保护层。特别是,桥接层可用于保护集成电路在生产期间免受曝光。
根据本发明,第一导电结构与第二导电结构之间和/或与集成电路之间的连接通过衬底中的孔洞实现,导致连接路径完全被衬底保护起来并且完全嵌入衬底中。此外,电连接不要求任何隆起焊盘出现在集成电路上,因为在孔洞中引入的导电介质可以与所述结构的各个接触面直接接触,实现电连接,导致了特别薄的结构。另一个优点是各结构之间无需金属互连以实现电气连接。
孔洞可以配置用于或者将第二导电结构与第一导电结构的电连接或者将第二导电结构与集成电路电连接或者二者兼有。对于这一点,如果衬底在集成电路接触面上面包括至少一个孔洞用于将第二导电结构与集成电路电连接,则本发明器件的优选实施例得以实现。相应地,根据优选实施例,衬底在第一导电结构接触面上面包括至少一个孔洞用于将第一导电结构与第二导电结构电连接。依赖于接触面尺寸,集成电路在具有第一导电结构的层上的定位容限以及第二导电结构相对于集成电路的定位容限可以比现有技术设计更高。
如果衬底作为层组合,则可以实现特别简单的设计。因此,本发明提供了用于组合的优选实施例,其中集成电路设置在衬底的两层之间,第二导电结构设置在背离集成电路的至少一个衬底层的表面上,第一导电结构设置在面对集成电路的至少一个衬底层的表面上。在该实施例中,导电结构再次设置在集成电路相反的两侧,从而例如第二导电结构是设置在衬底的外表面上,在存在集成电路的情况下第一导电结构设置在两个衬底层之间,所述集成电路有利地设置在第一导电结构的上方。
对于这一点,优选实施例的特征在于第一导电结构被设计作为通过绝缘层与集成电路分离的导电层。所述绝缘层可同时用作粘合剂,用于在导电层上固定集成电路。所述导电层可以是金属载体或者任何一种导电材料。然而,如果导电层没有选择金属载体,则通常需要用于所述导电层的附加衬底。因此,根据优选实施例,导电层设置在载体上,特别是聚合物载体。这样,所述载体可以作为保护层,还可以加强本发明器件的刚度。所述导电层,既可以是金属载体也可以是涂覆有导电层的非导电载体,实现了特别薄的设计。
对于应用本发明器件作为RFID智能卡的嵌体,实施例是优选的,其中第二导电结构包括至少一个呈螺旋状的导电迹线。这种结构导致了可用表面积的特别有效的利用,从而螺旋状迹线的两端可以通过由第一导电结构形成的桥接彼此相连。这样,根据优选实施例,第一导电结构和第二导电结构一起形成了天线,例如用于RFID应用的天线。按照特别有利的方式,第二导电结构可以包括两个彼此分离的螺旋状导电迹线,两个迹线均被实质上同轴地设置,从而所述桥接连接了内部迹线的内端和外部迹线的外端。换言之,这种结构也可以被描述为划分为两个螺旋状区域的单个螺旋状迹线,从而分离点连接至集成电路,所述连接优选地经由孔洞建立。
第二导电结构的制造可以通过现有公知技术以不同的方式实现。然而如果根据优选实施例,第二导电结构由导电油墨制造,并且第一和第二导电结构之间和/或与集成电路之间的电连接通过填充衬底中孔洞的导电油墨实现,可以得到特别简单的制造方法。这样,第二导电结构的应用,例如天线,以及与第一导电结构和/或集成电路的电连接可以在单一的工艺步骤中执行,因此导致一种非常有效的制造方法。
替代地,第一与第二导电结构之间和/或与集成电路之间的电连接可以通过填充衬底中孔洞的导电膏或者导电胶实现。
如上所述,由于其非常低的结构高度,本发明器件特别适合集成在智能卡中。因此,根据优选实施例,所述器件作为用于智能卡的嵌体。
对于这一点,如果所述衬底由热塑性材料制造,则更为有利。
本发明方法包括以下步骤:
-在具有第一导电结构的层上设置集成电路;
-将集成电路嵌入衬底;
-在衬底中形成孔洞;
-在衬底表面上形成第二导电结构,所述表面在与第一导电结构相反的集成电路一侧;
-通过孔洞将第二导电结构与第一导电结构和/或集成电路电连接。
因此,利用最少的工艺步骤,集成电路可以是嵌入的,同时导电结构例如用于RFID应用的天线可以形成且与集成电路电连接。由于本发明设计,当在集成电路相反两侧上存在第一和第二导电结构时,其中根据优选实施例,一个导电结构可以用于连接第一导电结构相距的末端或区域,第一导电结构在第二导电结构的两个区域之间形成导电桥接。由于第一导电结构以集成在模块中的附件层形式存在,无需另外的步骤隔离第二导电结构的区域以在待连接的第二导电结构的两个区域之间形成桥接。
由本发明制造方法形成的结构已经是结实的,无需如现有技术进行这种结构的压缩以将集成电路连接至第二导电结构。改进地在衬底上形成孔洞,例如通过激光钻孔,以便可以通过孔洞实现导电结构的后续电连接。
根据本发明特别优选的实施例,所述形成第二导电结构的步骤和所述连接第二导电结构的步骤在单一的工艺步骤中执行。根据优选实施例,当所述形成第二导电结构的步骤包括用导电油墨印制所述结构并且在所述印制期间用导电油墨填充所述孔洞以将第二导电结构与第一导电结构和/或集成电路连接时,这使得特别简单、有效的方式成为可能。因此,工艺步骤的数量还可以进一步减少,该制造方法适合于大规模生产。
替代地,所述形成第二导电结构的步骤可以包括构建和刻蚀衬底以形成金属导电路径。这些技术可以通过采用已有设备执行。对于这一点,根据本发明优选实施例的所述连接所述第二结构的步骤包括在孔洞中涂覆导电膏或导电胶。用于在导电结构之间或者导电结构与集成电路之间建立电连接的方法可以分别地采用用以形成第二导电结构的几乎所有方法。替代地,所述连接所述第二结构的步骤可以通过焊接或者电镀沉积完成。
根据本发明优选实施例,所述嵌入步骤包括在衬底的两层之间层压集成电路。通过以叠层的形式提供衬底,可以随后设置本发明器件的各种部件,提供了一种生产的简单工艺过程。对于这一点,在背离集成电路表面的至少一个衬底层的表面上形成第一导电结构以及在面对集成电路的至少一个衬底层的表面上形成第二导电结构是有利的。在该方法中,所述导电结构设置在集成电路相反的两侧,其中第二导电结构例如设置在衬底的外表面上,而第一导电结构,正如集成电路的情况,设置在两个衬底层之间。
替代地,为了在单一的工艺步骤中形成第二导电结构和连接第二导电结构,在嵌入集成电路的步骤之前执行所述形成第二导电结构的步骤是方便的。这使得在单独的步骤中以及根据情况在独立的位置上形成第二导电结构成为可能,以至于衬底层和设置其上的预先形成的导电结构可以用于嵌入步骤。这样,在嵌入步骤之后自然会发生连接第二导电结构的步骤。
在执行连接第二导电结构的步骤之前,要求在衬底中形成孔洞。在本发明特别优选的实施例中,所述形成孔洞的步骤包括激光钻孔,提供了一种甚至当集成电路已经嵌入在衬底中时、在衬底上形成所述孔洞的极其精确的方法。替代地,在所述将集成电路嵌入衬底中的步骤之前执行所述形成孔洞的步骤,这样有利于形成孔洞而不存在损伤集成电路的危险。根据另一个替代实施例,可以在嵌入步骤期间形成孔洞,特别是通过在集成电路上提供键合焊盘或隆起焊盘,当集成电路在两个衬底层之间受压时所述焊盘被压入衬底,因此形成了用于将键合焊盘或隆起焊盘与第二导电结构相连的孔洞。这一方法在WO 2007/075352A2中进行了描述。
根据本发明优选实施例,所述集成电路包括接触面和包括接触面的第一导电结构,并且在所述接触面上方的衬底中形成孔洞。这样,第二导电结构可以经由孔洞直接与第一导电结构和集成电路相连,其中依赖于接触面的尺寸,接触面的提供导致了集成电路在第一导电结构上且相对于接触面上方孔洞具有比现有技术更大的定位容限。可以在集成电路的键合焊盘或隆起焊盘上实现接触面,但是在优选实施例中,所述接触面位于IC表面的平面内,并未从IC表面上凸出。这样,当集成电路在衬底层之间受压时,在接触面区域内的集成电路不会遭受机械应力峰,因此集成电路精细结构受损的危险降至最低。
根据本发明优选实施例,将具有第一导电结构的层被选定为导电层。优选地,导电层设置在载体上,特别是聚合物载体。具有第一导电结构的层可以因此由能够提供所需强度的材料制成,从而实现了特别薄的总体设计。
以一种特别有利的方式执行本发明方法时,所述在具有第一导电结构的层上设置集成电路的步骤包括在所述集成电路和第一导电结构之间插入绝缘层。这样增加了器件的机械强度,且形成了在第一导电结构与集成电路任何外部导电部分之间的所需电隔离。此外,如果绝缘层同时用作粘合剂,则便于集成电路的后续处理。特别是,在自动化生产环境中,固定至具有第一导电结构的层的集成电路能够被自动化采集设备更容易地采集和处理。
根据本发明优选实施例,所述形成第二导电结构的步骤包括以螺旋状形式在衬底上应用至少一个导电迹线,这允许有效使用衬底上的可用空间。优选地,第二导电结构形成天线,例如用于RFID应用的天线。这样,第一导电结构用作连接卷状天线两端的桥接。
在本发明的优选实施例中,所述衬底由热塑性材料制成,从而用于软化热塑性材料的采用加热方法的层压工艺可以形成包括电子器件所有组件的平坦模块。对于这一点,优选地设计衬底以形成用于智能卡的嵌体。
结合下文所述实施例来阐述本发明的上述及其他方面,并且本发明的上述和其他方面据此将是清楚明白的。
附图说明
下文将结合附图所示的实施例作为非限制性示例,更为详细地描述本发明。
图1示出了在第一导电结构上的集成电路结构的剖面图;
图2示出了图1所示结构的平面图;
图3示出了嵌入衬底中的图1所示结构的剖面图;
图4示出了带有孔洞的图3所示结构的剖面图,所述孔洞用于使导电结构彼此连接;
图5示出了具有彼此相连的第一和第二导电结构的电子器件的剖面图;以及
图6示出了图5所示电子器件的平面图,图5是沿图6所示V-V线剖开的剖面图。
具体实施方式
在图1中,通过插入绝缘层4,在第一工艺步骤中将集成电路1被放置在第一导电结构上,所述第一导电结构在本例中是设置在诸如聚合物载体的载体2上的导电层3。该绝缘层4还作为粘合剂将集成电路1牢固地固定在导电层3上。从工艺的角度来看,将集成电路1固定在载体2上的处理工艺比直接采集和放置的工艺步骤简单得多,可以容易地被集成在天线制造和层压环境中。所述第一工艺步骤类似于用于插入件的集成电路的封装,但是不需要集成电路和载体导电部分之间的金属互连,且具有非常宽松的定位容限。从图2所示的俯视图可以看出,可以通过优化后续工艺步骤的方式对导电层3进行构图。特别是应该认识到:集成电路1在导电层3上的精确定位并不关键,因为在工艺过程的后期阶段导电层3为第二导电结构提供了足够的面积用于后续接触。同时,集成电路1的电接触面5足够大,为第二导电结构留有一定的定位容限。
从图3中可以看出,在第二工艺步骤中,其上设置有集成电路1的载体2嵌入在衬底的两层6和7之间,以便形成封闭结构。载体2既可以直接作用于衬底材料上,也可以层压在衬底层之间。
在下一步工艺步骤中,如图4所示,通过例如激光钻孔孔洞8打开衬底材料,所述孔洞位于集成电路1的接触面5的上方以及导电层2或其接触面的上方。替代地,也可以在嵌入步骤之前在衬底层7上打孔。
随后,在衬底层7的上表面上应用第二导电结构9,例如通过用导电油墨在衬底层7上印制所述结构并同时填充孔洞8,以便在第二导电结构9和集成电路1之间建立电连接10和11以及在第二导电结构9和第一导电结构3之间建立电连接12和13。
图6示出了最终嵌体,例如用于智能卡的嵌体。从图6所示的俯视图可以看出,第二导电结构9已经应用为螺旋状导电迹线以形成天线,例如用于RFID应用的天线。所述天线通过电连接10和11与集成电路1相连。天线的两个相距末端14和15通过电连接12和13与导电层3相连,因此导电层3在天线的两端14和15之间形成的导电桥接。
最后,值得注意的是,上述实施例阐述但不限制本发明,本领域普通技术人员可以在不脱离所附权利要求所限定的本发明范围下设计出许多替代实施例。在权利要求中,括号内的参考数字不得理解为对权利要求的限制。单词“包括”及其变形不排除未在权利要求或说明书中罗列的其他元件或步骤的存在。某一元件的单数参考不排除该元件的复数参考,反之亦然。在罗列了若干装置的关于器件的权利要求中,若干装置可以用同一个软件或硬件项目表示。在不同的从属权利要求中引用的方法并不表示这些方法的组合不能加以利用。
Claims (13)
1.一种电子器件,包括嵌入在衬底中的集成电路(1),其中所述衬底至少包括设置在集成电路(1)相反两侧上的第一(3)和第二(9)导电结构,以及经由在衬底中的孔洞(8)建立的第一(3)和第二(9)导电结构之间和/或与集成电路(1)之间的电连接。
2.根据权利要求1中所述的电子器件,其中第一导电结构(3)在第二导电结构(9)的两个区域之间形成导电桥接。
3.根据权利要求1或2中所述的电子器件,其中集成电路(1)设置在衬底上的两层(6,7)之间,第二导电结构(9)设置在背离集成电路(1)的至少一个衬底层(7)的表面上,第一导电结构(3)设置在面对集成电路(1)的至少一个衬底(6)的表面上。
4.根据权利要求1至3任一项中所述的电子器件,其中第一导电结构(3)被设计作为通过绝缘层(4)与集成电路(1)分离的导电层。
5.根据权利要求4中所述的电子器件,其中导电层设置在载体(2)上,特别是聚合物载体上。
6.根据权利要求1至5任一项中所述的电子器件,其中第二导电结构(9)由导电油墨制成,并且第一(3)和第二(9)导电结构之间和/或与集成电路(1)的电连接(10、11、12和13)通过在衬底中的孔洞(8)填充导电油墨实现。
7.根据权利要求1至6任一项中所述的电子器件,其中所述电子器件设置为用于智能卡的嵌体。
8.一种制造电子器件的方法,包括以下步骤:
-在具有第一导电结构(3)的层(6)上设置集成电路(1),
-将集成电路(1)嵌入衬底,
-在衬底中形成孔洞(8),
-在衬底表面上形成第二导电结构(9),所述表面在与第一导电结构(3)相反的集成电路(1)一侧,
-通过孔洞(8)将第二导电结构(9)与第一导电结构(3)和/或集成电路(1)电连接。
9.根据权利要求8中所述的方法,其中所述形成第二导电结构(9)的步骤和所述连接第二导电结构(9)的步骤在单一的工艺步骤中执行。
10.根据权利要求8或9中所述的方法,其中所述形成第二导电结构(9)的步骤包括用导电油墨印制所述结构(9),并且在所述印制期间用油墨填充所述孔洞(8)以将第二导电结构(9)与第一导电结构(3)和/或与集成电路(1)相连。
11.根据权利要求8至10任一项中所述的方法,其中所述嵌入步骤包括在衬底的两层(6,7)之间层压集成电路(1)。
12.根据权利要求8至11任一项中所述的方法,其中所述在具有第一导电结构(3)的层(6)上设置集成电路(1)的步骤包括在所述集成电路(1)和第一导电结构(3)之间插入绝缘层(4)。
13.根据权利要求8至12任一项中所述的方法,其中第二导电结构(9)形成天线,例如用于RFID应用的天线。
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EP08104214 | 2008-06-02 | ||
EP08104214.5 | 2008-06-02 | ||
PCT/IB2009/051966 WO2009147547A1 (en) | 2008-06-02 | 2009-05-13 | Electronic device and method of manufacturing an electronic device |
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CN102047403A true CN102047403A (zh) | 2011-05-04 |
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US (1) | US20110073357A1 (zh) |
EP (1) | EP2286446A1 (zh) |
CN (1) | CN102047403A (zh) |
WO (1) | WO2009147547A1 (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2286445A1 (en) | 2008-06-02 | 2011-02-23 | Nxp B.V. | Method for manufacturing an electronic device |
US8735735B2 (en) * | 2010-07-23 | 2014-05-27 | Ge Embedded Electronics Oy | Electronic module with embedded jumper conductor |
US9205605B2 (en) * | 2012-04-25 | 2015-12-08 | Textron Innovations Inc. | Multi-function detection liner for manufacturing of composites |
CN103489790A (zh) * | 2012-06-14 | 2014-01-01 | 智瑞达科技(苏州)有限公司 | 芯片扇出封装结构的封装方法 |
US9224695B2 (en) * | 2013-02-28 | 2015-12-29 | Infineon Technologies Ag | Chip arrangement and a method for manufacturing a chip arrangement |
EP3109799B1 (fr) * | 2015-04-15 | 2018-10-17 | Maintag | Procede de fabrication d'une etiquette multicouche de type rfid, etiquette multicouche rfid et son utilisation |
DE102016106698A1 (de) * | 2016-04-12 | 2017-10-12 | Infineon Technologies Ag | Chipkarte und Verfahren zum Herstellen einer Chipkarte |
Family Cites Families (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2833111B2 (ja) * | 1989-03-09 | 1998-12-09 | 日立化成工業株式会社 | 回路の接続方法及びそれに用いる接着剤フィルム |
DE4435802A1 (de) * | 1994-10-06 | 1996-04-11 | Giesecke & Devrient Gmbh | Verfahren zur Herstellung von Datenträgern mit eingebetteten Elementen und Vorrichtung zur Durchführung des Verfahrens |
JP3842362B2 (ja) * | 1996-02-28 | 2006-11-08 | 株式会社東芝 | 熱圧着方法および熱圧着装置 |
FR2749687B1 (fr) * | 1996-06-07 | 1998-07-17 | Solaic Sa | Carte a memoire et procede de fabrication d'une telle carte |
US6077382A (en) * | 1997-05-09 | 2000-06-20 | Citizen Watch Co., Ltd | Mounting method of semiconductor chip |
US6690845B1 (en) * | 1998-10-09 | 2004-02-10 | Fujitsu Limited | Three-dimensional opto-electronic modules with electrical and optical interconnections and methods for making |
US6706546B2 (en) * | 1998-10-09 | 2004-03-16 | Fujitsu Limited | Optical reflective structures and method for making |
US6611635B1 (en) * | 1998-10-09 | 2003-08-26 | Fujitsu Limited | Opto-electronic substrates with electrical and optical interconnections and methods for making |
US6845184B1 (en) * | 1998-10-09 | 2005-01-18 | Fujitsu Limited | Multi-layer opto-electronic substrates with electrical and optical interconnections and methods for making |
US6684007B2 (en) * | 1998-10-09 | 2004-01-27 | Fujitsu Limited | Optical coupling structures and the fabrication processes |
US6343171B1 (en) * | 1998-10-09 | 2002-01-29 | Fujitsu Limited | Systems based on opto-electronic substrates with electrical and optical interconnections and methods for making |
US6785447B2 (en) * | 1998-10-09 | 2004-08-31 | Fujitsu Limited | Single and multilayer waveguides and fabrication process |
US6421013B1 (en) * | 1999-10-04 | 2002-07-16 | Amerasia International Technology, Inc. | Tamper-resistant wireless article including an antenna |
EP1259103B1 (en) * | 2000-02-25 | 2007-05-30 | Ibiden Co., Ltd. | Multilayer printed wiring board and method for producing multilayer printed wiring board |
EP1346411A2 (en) * | 2000-12-01 | 2003-09-24 | Broadcom Corporation | Thermally and electrically enhanced ball grid array packaging |
US6856007B2 (en) * | 2001-08-28 | 2005-02-15 | Tessera, Inc. | High-frequency chip packages |
US7176506B2 (en) * | 2001-08-28 | 2007-02-13 | Tessera, Inc. | High frequency chip packages with connecting elements |
US7176055B2 (en) * | 2001-11-02 | 2007-02-13 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component |
JP3492348B2 (ja) * | 2001-12-26 | 2004-02-03 | 新光電気工業株式会社 | 半導体装置用パッケージの製造方法 |
DE10250621B4 (de) * | 2002-10-30 | 2004-09-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Erzeugen verkapselter Chips und zum Erzeugen eines Stapels aus den verkapselten Chips |
US6919508B2 (en) * | 2002-11-08 | 2005-07-19 | Flipchip International, Llc | Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing |
WO2004064159A1 (ja) * | 2003-01-15 | 2004-07-29 | Fujitsu Limited | 半導体装置及び三次元実装半導体装置、並びに半導体装置の製造方法 |
US20040145874A1 (en) | 2003-01-23 | 2004-07-29 | Stephane Pinel | Method, system, and apparatus for embedding circuits |
JP4479209B2 (ja) * | 2003-10-10 | 2010-06-09 | パナソニック株式会社 | 電子回路装置およびその製造方法並びに電子回路装置の製造装置 |
JP4339739B2 (ja) * | 2004-04-26 | 2009-10-07 | 太陽誘電株式会社 | 部品内蔵型多層基板 |
US6974724B2 (en) * | 2004-04-28 | 2005-12-13 | Nokia Corporation | Shielded laminated structure with embedded chips |
TWI372413B (en) * | 2004-09-24 | 2012-09-11 | Semiconductor Energy Lab | Semiconductor device and method for manufacturing the same, and electric appliance |
DE102004049356B4 (de) * | 2004-10-08 | 2006-06-29 | Infineon Technologies Ag | Halbleitermodul mit einem internen Halbleiterchipstapel und Verfahren zur Herstellung desselben |
US7098070B2 (en) * | 2004-11-16 | 2006-08-29 | International Business Machines Corporation | Device and method for fabricating double-sided SOI wafer scale package with through via connections |
US7688206B2 (en) * | 2004-11-22 | 2010-03-30 | Alien Technology Corporation | Radio frequency identification (RFID) tag for an item having a conductive layer included or attached |
US20060109130A1 (en) * | 2004-11-22 | 2006-05-25 | Hattick John B | Radio frequency identification (RFID) tag for an item having a conductive layer included or attached |
US7339275B2 (en) * | 2004-11-22 | 2008-03-04 | Freescale Semiconductor, Inc. | Multi-chips semiconductor device assemblies and methods for fabricating the same |
TWI301660B (en) * | 2004-11-26 | 2008-10-01 | Phoenix Prec Technology Corp | Structure of embedding chip in substrate and method for fabricating the same |
US20060214278A1 (en) * | 2005-03-24 | 2006-09-28 | Nokia Corporation | Shield and semiconductor die assembly |
JP4551255B2 (ja) * | 2005-03-31 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4016039B2 (ja) * | 2005-06-02 | 2007-12-05 | 新光電気工業株式会社 | 配線基板および配線基板の製造方法 |
TWI290375B (en) * | 2005-07-15 | 2007-11-21 | Via Tech Inc | Die pad arrangement and bumpless chip package applying the same |
DE102005037321B4 (de) * | 2005-08-04 | 2013-08-01 | Infineon Technologies Ag | Verfahren zur Herstellung von Halbleiterbauteilen mit Leiterbahnen zwischen Halbleiterchips und einem Schaltungsträger |
EP1770610A3 (en) * | 2005-09-29 | 2010-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8101868B2 (en) * | 2005-10-14 | 2012-01-24 | Ibiden Co., Ltd. | Multilayered printed circuit board and method for manufacturing the same |
US8067253B2 (en) | 2005-12-21 | 2011-11-29 | Avery Dennison Corporation | Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film |
US20070158804A1 (en) * | 2006-01-10 | 2007-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, manufacturing method of semiconductor device, and RFID tag |
TWI269462B (en) * | 2006-01-11 | 2006-12-21 | Advanced Semiconductor Eng | Multi-chip build-up package of an optoelectronic chip and method for fabricating the same |
TWI411964B (zh) * | 2006-02-10 | 2013-10-11 | Semiconductor Energy Lab | 半導體裝置 |
DE102006007381A1 (de) * | 2006-02-15 | 2007-08-23 | Infineon Technologies Ag | Halbleiterbauelement für einen Ultraweitband-Standard in der Ultrahochfrequenz-Kommunikation und Verfahren zur Herstellung desselben |
US20070252233A1 (en) * | 2006-04-28 | 2007-11-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the semiconductor device |
US7838976B2 (en) * | 2006-07-28 | 2010-11-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a semiconductor chip enclosed by a body structure and a base |
TWI301663B (en) * | 2006-08-02 | 2008-10-01 | Phoenix Prec Technology Corp | Circuit board structure with embedded semiconductor chip and fabrication method thereof |
JP4995834B2 (ja) * | 2006-12-07 | 2012-08-08 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
EP1978472A3 (en) * | 2007-04-06 | 2015-04-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
CN101675518B (zh) * | 2007-05-10 | 2012-12-05 | 飞思卡尔半导体公司 | 芯片上功率引线球栅阵列封装 |
US7980477B2 (en) * | 2007-05-17 | 2011-07-19 | Féinics Amatech Teoranta | Dual interface inlays |
US8237259B2 (en) * | 2007-06-13 | 2012-08-07 | Infineon Technologies Ag | Embedded chip package |
US9610758B2 (en) * | 2007-06-21 | 2017-04-04 | General Electric Company | Method of making demountable interconnect structure |
US9953910B2 (en) * | 2007-06-21 | 2018-04-24 | General Electric Company | Demountable interconnect structure |
KR100885924B1 (ko) * | 2007-08-10 | 2009-02-26 | 삼성전자주식회사 | 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법 |
US7790576B2 (en) * | 2007-11-29 | 2010-09-07 | Stats Chippac, Ltd. | Semiconductor device and method of forming through hole vias in die extension region around periphery of die |
US7648911B2 (en) * | 2008-05-27 | 2010-01-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias |
-
2009
- 2009-05-13 WO PCT/IB2009/051966 patent/WO2009147547A1/en active Application Filing
- 2009-05-13 EP EP09757899A patent/EP2286446A1/en not_active Withdrawn
- 2009-05-13 US US12/995,848 patent/US20110073357A1/en not_active Abandoned
- 2009-05-13 CN CN2009801204060A patent/CN102047403A/zh active Pending
Also Published As
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WO2009147547A1 (en) | 2009-12-10 |
EP2286446A1 (en) | 2011-02-23 |
US20110073357A1 (en) | 2011-03-31 |
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