CN102044474A - Surface treatment method of copper metal layer subjected to chemically mechanical polishing - Google Patents
Surface treatment method of copper metal layer subjected to chemically mechanical polishing Download PDFInfo
- Publication number
- CN102044474A CN102044474A CN2009101970837A CN200910197083A CN102044474A CN 102044474 A CN102044474 A CN 102044474A CN 2009101970837 A CN2009101970837 A CN 2009101970837A CN 200910197083 A CN200910197083 A CN 200910197083A CN 102044474 A CN102044474 A CN 102044474A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- copper
- mechanical polishing
- layer
- chemico
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a surface treatment method of a copper metal layer subjected to chemically mechanical polishing, which comprises the steps of: providing a semiconductor substrate, wherein a dielectric layer is arranged on the surface of the semiconductor substrate, an opening is formed in the dielectric layer, metal copper is filed in the opening; carrying out chemically mechanical polishing on the semiconductor substrate until the metal copper in the opening is level to the surface of the dielectric layer; cleaning the dielectric layer and the surface of the metal copper with an alkali preparation; preprocessing surface plasma on the dielectric layer and the surface of the metal copper; and forming an etching stopping layer on the dielectric layer and the surface of the metal copper. Through simple regulation of the process, the invention avoids oxidization of the surface of the copper and the diffusion of copper ions in the dielectric layer, repairs the crystal lattice and the surface state of the dielectric layer to be a certain extent, improves the electric performance parameters of breakdown voltage, TDDB (Time Dependent Dielectric Breakdown), and the like, and enhances the element performances.
Description
Technical field
The present invention relates to field of semiconductor technology, the surface treatment method after particularly a kind of copper metal layer chemico-mechanical polishing.
Background technology
Along with the continuous development of semiconductor technology, the physical dimension of semiconductor device continues to dwindle, and has reached the 32nm magnitude at present, and with constantly dwindling of dimensions of semiconductor devices, new ghost effect constantly occurs.Wherein the RC delay is one of key factor that influences the device reaction speed.For addressing this problem, need to improve metal interconnect structure and postpone to reduce RC.The corresponding techniques scheme comprises conductivity that improves interconnecting metal and dielectric constant (k) value that reduces dielectric layer.In the technology below 90nm, copper has replaced aluminium comprehensively becomes interconnecting metal.Copper has better conductivity than aluminium, and electromigration effect is also less.About the dielectric layer material, the also extensive use of new material (k＜2.7) of low-k (low k) is to replace traditional oxide layer.But compare with oxide layer, advanced low-k materials is structurally loose porous usually, and is also slightly poor with the tack of packing material.
In integrated circuit was made, dual damascene (dual damascene) technology was used for forming copper interconnecting line on dielectric layer.One of them important step is chemico-mechanical polishing (CMP), is used to remove the unnecessary copper in dielectric layer surface, realizes planarization.But in CMP technology, pollutants such as the particle of the residual polishing fluid of silicon chip surface meeting, byproduct of reaction.Therefore after CMP technology, all need avoid defective is introduced device and caused integrity problem usually through cleaning to remove these pollutants.
In dual-damascene technics, in groove, fill copper before usually on channel bottom and sidewall deposit layer of metal barrier layer (barrier), its composition is titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN).Its effect is to prevent that copper is diffused in the dielectric layer.And also need similar dielectric barrier to prevent the diffusion of copper in copper line surface.For the such structure of metal-insulator semiconductor in the device (MIS), select for use silicon nitride (Si3N4) or phosphorosilicate glass (PSG) to diffuse in silicon and the dielectric layer to prevent copper ion usually as diffusion impervious layer.Therefore, the surface state of copper and dielectric layer has bigger influence to the reliability of low dielectric coefficient medium layer, mainly shows on puncture voltage (VBD), the time correlation dielectric breakdown parameters such as (time dependent dielectric breakdown:TDDB).
Based on foregoing, in the semiconductor technology below 65nm, the integrity problem of low dielectric coefficient medium layer is a key factor that influences device performance.Publication number be 20080047592 U.S. Patent application proposed a kind of behind CMP the method with the cleaning silicon chip surface, this method is applicable to that dielectric layer is the conventional oxidation layer or the situation of advanced low-k materials, situation for advanced low-k materials, then mainly inquired into of the influence of this cleaning method, not mentioned improvement to the electrical parameter aspect to device topography.
Therefore, the needs proposition is a kind of cleans and the surface-treated effective ways after CMP technology, improves the electric property of low dielectric coefficient medium layer.
Summary of the invention
The problem that the present invention solves provides the surface treatment method after a kind of copper metal layer chemico-mechanical polishing, can improve the reliability of low dielectric coefficient medium layer, prolongs the puncture life-span of dielectric layer.
For addressing the above problem, the invention provides the surface treatment method after a kind of copper metal layer chemico-mechanical polishing, the cleaning fluid behind the CMP is a basic formulations, carries out the gaseous plasma preliminary treatment before etching stop layer forms.Comprise the following step:
Semiconductor substrate is provided, and described semiconductor substrate surface has dielectric layer, is formed with opening in the described dielectric layer, is filled with metallic copper in the described opening;
Described Semiconductor substrate is carried out chemico-mechanical polishing, to described opening interior metallic copper and dielectric layer flush;
Use basic formulations that the surface of described dielectric layer and metallic copper is cleaned;
Surface plasma preliminary treatment to described dielectric layer and metallic copper;
Surface at described dielectric layer and metallic copper forms etching stop layer.
Optionally, the pH value of described basic formulations is 9～13.
Optionally, the pretreated gas of described gaseous plasma is selected from ammonia (NH
3), nitrogen (N
2), helium (He), hydrogen (H
2).
Optionally, the flow of described ammonia is 100～200sccm.
Optionally, the pretreated reaction temperature of described gaseous plasma is 360～400 ℃.
Optionally, described pretreated process time of gaseous plasma is 15～20sec.
Optionally, described dielectric layer is an advanced low-k materials.
Optionally, described etching stop layer is silicon nitride (Si
3N
4), nitrogen-doped silicon carbide (NDC).
Optionally, the formation method of described etching stop layer is low-pressure chemical vapor phase deposition (LPCVD), plasma enhanced CVD (PECVD).
Compared with prior art, such scheme has the following advantages: by the simple adjustment to technological process, use basic formulations to clean after the CMP, be formed up to the promoting the circulation of qi bulk plasmon preliminary treatment of advancing at etching stop layer again, the oxidation and the drift diffusion of copper ion in dielectric layer on copper surface have been avoided, and the lattice and the surface state of having repaired dielectric layer to a certain extent, improve puncture voltage, time correlation dielectric breakdown parameter electric property parameters such as (TDDB), improved device performance.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.The drafting of accompanying drawing focuses on illustrating purport of the present invention not painstakingly according to actual ratio.In the accompanying drawings, for cheer and bright, part layer and zone are carried out amplification.
Fig. 1 is the schematic flow sheet of the surface treatment method after the copper metal layer chemico-mechanical polishing of one embodiment of the present of invention;
Fig. 2 to Fig. 3 is the cross-sectional view of the surface treatment method after the copper metal layer chemico-mechanical polishing of one embodiment of the present of invention;
Fig. 4 is the structural representation that dielectric layer punctures test;
Fig. 5, the 6th, prior art and electric performance test result's of the present invention Weibull distribution figure.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Method provided by the invention is not only applicable to the copper metal layer CMP aftertreatment technology that dielectric layer is an advanced low-k materials, is applicable to the situation of dielectric layer material for other material types yet.
At first briefly introduce relevant technological process, what choose in the present embodiment is the dielectric layer of metallic intermediate layer (inter-metal).In addition, also can correspondingly be generalized to the CMP technology of other levels, also therewith roughly the same to the dielectric layer of other metal levels such as the first metal layer (Metal 1), top layer metallic layer (top metal).Fig. 1 shows the process flow diagram of the surface treatment method after the copper metal layer chemico-mechanical polishing of one embodiment of the present of invention.
As shown in Figure 1, execution in step S110 provides Semiconductor substrate, described semiconductor substrate surface has dielectric layer, be formed with opening in the described dielectric layer, be filled with metallic copper in the described opening, described metallic copper fills up described opening and covers on the described dielectric layer surface; Execution in step S120 carries out chemico-mechanical polishing to described Semiconductor substrate, to described opening interior metallic copper and described dielectric layer flush; Execution in step S130 uses basic formulations that described metallic copper and dielectric layer surface are cleaned; Execution in step S140 carries out the gaseous plasma preliminary treatment to described metal level and dielectric layer surface; Execution in step S150 forms etching stop layer on described metallic copper and dielectric layer surface.
Fig. 2 and Fig. 3 have provided the cross-sectional view of the surface treatment method after the copper metal layer chemico-mechanical polishing of one embodiment of the present of invention.
With reference to Fig. 2, Semiconductor substrate is provided, be formed with etching stop layer 210 and low dielectric coefficient medium layer 220 on the described Semiconductor substrate, be formed with oxide layer 230 on the described dielectric layer 220, in described dielectric layer 220 and oxide layer 230, there is groove, described groove is opened to etching stop layer below 210, exposes described Semiconductor substrate.Be formed with barrier layer 240 in the described groove, described barrier layer 240 can be tantalum (Ta), tantalum nitride (TaN), is tantalum nitride in the present embodiment.Its effect is to prevent the diffusion of drifting about in low dielectric coefficient medium layer 220 of metallic copper in the groove.In groove, fill metallic copper then, form copper metal layer 250, the formation method has physical vapor deposition (PVD), chemical vapor deposition (CVD), ionization PVD, plating, select physical vapor deposition for use at this, after copper metal layer 250 formed, the unnecessary copper that has part overflowed groove and covers on dielectric layer 220 surfaces.
With reference to Fig. 3, carry out chemico-mechanical polishing afterwards, remove unnecessary in addition copper of groove and barrier layer 240, oxide layer 230 and the part dielectric layer 220 that is positioned at groove two side roof parts, form copper metal layer 250 ', dielectric layer 220 ' and barrier layer 240 ', make the flush of metal copper layer 250 ' and described dielectric layer 220 ' in the described groove.Because pollutants such as polishing fluid, byproduct of reaction all can remain in polished surface in the CMP process, even can infiltrate in the dielectric layer 220 ', dielectric layer 220 ' is damaged, therefore be necessary after CMP technology, to clean to remove the pollutant of substrate surface.
In the prior art, mainly adopt acidic formulation to remove the pollutant of substrate surface, the pH value of described acidic formulation is about 1～2, and its active ingredient mainly is citric acid, and the consumption of single silicon chip is 38～42ml, and scavenging period is 160～170 seconds.
In theory, in sour environment, the oxidability of acid ion is stronger, has stronger oxidizability, and the copper with flute surfaces is oxidized to Cu easily
+Or Cu
2+,, can form cupric oxide (CuO) and cuprous oxide (Cu on the surface of copper metal layer 250 ' if there is oxygen element to exist
2O) mixture.In addition, can go up formation etching stop layer (stop layer) at copper metal layer 250 ' and dielectric layer 220 ' in the subsequent technique, its composition is generally silicon nitride (Si
3N
4), and one of reacting gas that forms silicon nitride is silane (SiH
4), in course of reaction, silane easily with the react silicide CuSi of formation copper of copper
xSo can there be the multiple physical forms such as silicide of cupric oxide, cuprous oxide, copper on the surface of copper metal layer 250 '.Copper ion (Cu in these materials
2+, Cu
+) be activated easily and diffusion in described dielectric layer 220.In addition, because the CMP process can cause certain damage to the lattice structure on dielectric layer 220 ' surface, have the chain link of some fractures, this has more aggravated the diffusion of copper ion in dielectric layer 220 '.
After CMP technology, carry out multinomial electrical parameter test, wherein main one is puncture voltage.As shown in Figure 4, when the puncture voltage of tested media layer 220 ', can be with the copper metal in adjacent two grooves as test electrode, one of them ground connection, another applies positive voltage, the puncture voltage of dielectric layer 220 ' between test trenches.Because there is the copper ion (Cu of different valence state in the surface of copper metal layer 250 '
+, Cu
2+), and be in the dielectric layer 220 ' surface between the groove because CMP technology has caused certain lattice damage, have the surface portion that the part copper ions diffusion enters described dielectric layer 220 '.Because there is copper ion in dielectric layer 220 ' surface, has reduced the puncture voltage of device, and device performance is caused adverse influence.
As mentioned above, for improving the breakdown characteristics of low dielectric coefficient medium layer, improve it and puncture the life-span, need reduce or eliminate the generation of copper ion as far as possible, thereby will reduce the generation of the oxide and the silicide of copper, also must repair the damage that CMP causes dielectric layer in addition.Therefore, it is particularly important that the cleaning behind the CMP seems, by cleaning fluid is replaced by basic formulations by original acidic formulation, reduces the oxide of copper and the generation of silicide among the present invention.The concrete composition of used alkaline reagent is: ammoniacal liquor, and BTA (BTA), hydrogen peroxide, surfactant (being specially perfluorooctane sulfonate in the present embodiment), PH buffer etc., its pH value is about 9～13, and preferred range is 12～13 in the present embodiment.The required basic formulations consumption of single silicon chip is about 30～32ml, and scavenging period is 145～150 seconds, and compared with prior art, scavenging period has shortened about 15sec, and this helps the raising of production capacity.Through measuring and calculating, the expense of required cleaning fluid expenditure also has decline to a certain degree, helps reducing production costs.
Use the surface clean after basic formulations carries out CMP, the activity of the acid ion in the alkaline environment is suppressed, and copper is difficult for oxidized, therefore is difficult for forming the oxide of copper, thereby can avoid the diffusion drift of copper ion in dielectric layer.In addition, the basic formulations cleaning fluid also helps to reduce the lattice damage on dielectric layer 220 ' and copper metal layer 250 ' surface, and this also helps improving the puncture voltage of dielectric layer 220 '.
After cleaning is finished, to go up the formation etching stop layer at dielectric layer 220 ' and copper metal layer 250 ' thereafter.Its material is selected from silicon nitride (Si
3N
4) or nitrogen-doped silicon carbide (NDC), present embodiment is selected silicon nitride for use.The formation method has low-pressure chemical vapor phase deposition (LPCVD), plasma enhanced CVD (PECVD), selects plasma enhanced CVD for use at this.Its reacting gas mainly contains ammonia (NH
3) and silane (SiH
4), as mentioned before, silane and copper effect meeting produce silicide, and this also is one of factor of copper ion drift, therefore need prevent the formation of the silicide of copper.
For avoiding silicide to form, need before forming, silicon nitride carry out certain pretreating process to the copper surface.For this reason more optimally, before silicon nitride deposition, add a processing step: with ammonia (NH
3) plasma carries out preliminary treatment to dielectric layer 220 ' and copper metal layer 250 ' surface.This step can directly be carried out in the reaction chamber that forms silicon nitride, and therefore the cost to technology does not have big influence.This pretreated related process parameter is: ammonia flow 100～200sccm is preferably 150sccm; Reaction pressure is 5torr; Reaction temperature is 360～400 ℃, is preferably 370 ℃; Process time is 15～20sec, is preferably 18sec.Because it is the process time is shorter, therefore less to the influence of production capacity.
Described semiconductor substrate surface is after the preliminary treatment of process ammonia plasmas, and the copper metal layer 250 ' of described flute surfaces and the nitrogen element in the plasma can form the nitride of copper.Its chemical bond bond energy is bigger than the silicide of cupric oxide and copper, is not easy to be ionized, and has prevented the drift diffusion of copper ion in dielectric layer.Cuprous nitride (the Cu of plasma pretreatment reaction generation simultaneously
3N) rete is equivalent to a barrier layer, can avoid copper metal layer 250 ' and silane reaction to generate metal silicide when follow-up formation silicon nitride, thereby avoid the generation of copper ion.On the other hand, in the plasma preprocessing process, plasma can also be done certain reparation to the lattice of impaired dielectric layer 220 ', improves the surface state of dielectric layer 220 ', weakens copper ion elegant diffusion therein.
Except that utilizing ammonia plasma treatment to carry out the preliminary treatment, the inactive gaseous plasma of other chemical property also can play the effect of repairing the dielectric layer surface characteristic, for example nitrogen (N
2), hydrogen (H
2) or inert gas, described inert gas can be helium (He).These gases can be repaired the impaired lattice structure of dielectric layer, weaken copper ion drift diffusion therein.
For assessing improved technique effect, the device that forms for prior art and the present invention carries out electrical performance testing respectively.Test structure is with reference to Fig. 3, test to as if be formed with the Semiconductor substrate of the first metal layer (M1), the dielectric layer gap length between two grooves is 0.12 μ m.Fig. 5 is the Weibull distribution (Weibull distribution) of the device aging test failure time of prior art gained, and Fig. 6 is the Weibull distribution figure of the device aging test failure time of gained of the present invention.The test environment temperature is 125 ℃, and the test bias voltage is chosen 54V, 56V, three kinds of conditions of 58V respectively, obtains the straight line of three matches.Transverse axis is represented the component failure time, longitudinal axis representative proportion in the full wafer chip.Relatively as seen two figure are example with the 54V test voltage, and prior art gained linear gradient is 2.99, are 4.04 and adopt gained linear gradient of the present invention, and the slope of correspondence of the present invention obviously increases, and this shows that the convergence of test point has bigger improvement.
In addition, the test to time correlation dielectric breakdown parameter (TDDB) has also shown improvements of the present invention.Testing length is 3.45cm, and the voltage accelerated factor is 0.42, calculates under the prior art with extrapolation, has probability silicon chip life-span of 1 ‰ to be lower than 3160, then has probability silicon chip life-span of 1 ‰ to be lower than 4780 years for the present invention.Be extrapolated to the long test result of 100m again: under the prior art, have probability silicon chip life-span of 1 ‰ to be lower than 227 years, then have probability silicon chip life-span of 1 ‰ to be lower than 658 years for the present invention.If it is long to be extrapolated to 225m, test result is respectively: under the prior art, have probability silicon chip life-span of 1 ‰ to be lower than 147 years, then have probability silicon chip life-span of 1 ‰ to be lower than 538 years for the present invention.This shows that than prior art, TDDB of the present invention has increased by 2～3 times, has obtained significant prolongation device lifetime.
The present invention is by the simple adjustment to technological process, cleaning fluid behind the CMP is replaced by basic formulations by acidity, carrying out ammonia plasma again before the etching stop layer silicon nitride deposition handles, the oxidation and the drift diffusion of copper ion in dielectric layer on copper surface have been avoided, and in the lattice of to a certain degree having repaired low dielectric coefficient medium layer and surface state, improve puncture voltage, time correlation dielectric breakdown parameter electric property parameters such as (TDDB), improved device performance.
Though the present invention with preferred embodiment openly as above; but be not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (9)
1. the surface treatment method after the copper metal layer chemico-mechanical polishing is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has dielectric layer, is formed with opening in the described dielectric layer, is filled with metallic copper in the described opening;
Described Semiconductor substrate is carried out chemico-mechanical polishing, to described opening interior metallic copper and dielectric layer flush;
Use basic formulations that the surface of described dielectric layer and metallic copper is cleaned;
Surface plasma preliminary treatment to described dielectric layer and metallic copper;
Surface at described dielectric layer and metallic copper forms etching stop layer.
2. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 1 is characterized in that, the pH value of described basic formulations is 9～13, and its main component comprises ammoniacal liquor, BTA, hydrogen peroxide, perfluorooctane sulfonate.
3. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 1 is characterized in that, the pretreated gas of described gaseous plasma is selected from ammonia, nitrogen, helium, hydrogen.
4. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 3 is characterized in that, the flow of described ammonia is 100～200sccm.
5. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 3 is characterized in that, the pretreated reaction temperature of described gaseous plasma is 360～400 ℃.
6. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 3 is characterized in that, the pretreated process time of described gaseous plasma is 15～20sec.
7. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 1 is characterized in that, the material of described dielectric layer is a medium with low dielectric constant.
8. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 1 is characterized in that described etching stop layer is selected from silicon nitride, nitrogen-doped silicon carbide.
9. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 8 is characterized in that, the formation method of described etching stop layer is low-pressure chemical vapor phase deposition, plasma enhanced CVD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197083.7A CN102044474B (en) | 2009-10-13 | 2009-10-13 | Surface treatment method of copper metal layer subjected to chemically mechanical polishing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197083.7A CN102044474B (en) | 2009-10-13 | 2009-10-13 | Surface treatment method of copper metal layer subjected to chemically mechanical polishing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102044474A true CN102044474A (en) | 2011-05-04 |
| CN102044474B CN102044474B (en) | 2015-04-29 |
Family
ID=43910486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910197083.7A Active CN102044474B (en) | 2009-10-13 | 2009-10-13 | Surface treatment method of copper metal layer subjected to chemically mechanical polishing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102044474B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420173A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Surface treatment method for improving copper interconnection reliability |
| CN102446821A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Method used for reducing copper interconnection structure material damage after chemical machinery polishing |
| CN102456568A (en) * | 2011-09-29 | 2012-05-16 | 上海华力微电子有限公司 | Method for deposition of nitrogen-doped silicon carbide film |
| CN102517594A (en) * | 2011-12-15 | 2012-06-27 | 西安北方捷瑞光电科技有限公司 | Method for cleaning cerium-based polishing solution residues |
| CN103839880A (en) * | 2012-11-27 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN104112699A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating bump effect in semiconductor structure |
| CN104157603A (en) * | 2013-05-15 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | Method for enhancing combination strength of metal copper and NDC interface |
| CN104451492A (en) * | 2014-11-14 | 2015-03-25 | 无锡阳工机械制造有限公司 | Surface treatment method for lead-tin alloy |
| CN104451493A (en) * | 2014-11-14 | 2015-03-25 | 无锡阳工机械制造有限公司 | Copper alloy surface treating method |
| CN104637863A (en) * | 2013-11-14 | 2015-05-20 | 盛美半导体设备（上海）有限公司 | Tungsten plug formation method |
| CN104900481A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Method for cleaning bonding pads |
| CN105845621A (en) * | 2015-01-17 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Method of forming semiconductor device and processing method for Q-time exceeding of semiconductor device |
| CN107895687A (en) * | 2017-11-15 | 2018-04-10 | 上海华虹宏力半导体制造有限公司 | A kind of method for improving metal capacitance TDDB performances |
| CN110158100A (en) * | 2019-04-20 | 2019-08-23 | 无锡天杨电子有限公司 | A method of cleaning silicon nitride ceramics copper-clad plate black surround |
| CN111029298A (en) * | 2019-12-11 | 2020-04-17 | 武汉新芯集成电路制造有限公司 | Manufacturing method of copper interconnection layer |
| CN112885709A (en) * | 2021-01-13 | 2021-06-01 | 中电化合物半导体有限公司 | Preparation method of silicon carbide epitaxial structure and semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6194366B1 (en) * | 1999-11-16 | 2001-02-27 | Esc, Inc. | Post chemical-mechanical planarization (CMP) cleaning composition |
| CN1299358C (en) * | 2003-04-02 | 2007-02-07 | 联华电子股份有限公司 | Inlay metal inner connecting structure possessong double protective layer |
| CN1242039C (en) * | 2003-09-29 | 2006-02-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor wafer cleaning liquid and cleaning method |
| CN101410503A (en) * | 2006-03-27 | 2009-04-15 | 乔治洛德方法研究和开发液化空气有限公司 | Improved alkaline solutions for post CMP cleaning processes |
-
2009
- 2009-10-13 CN CN200910197083.7A patent/CN102044474B/en active Active
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420173B (en) * | 2011-06-07 | 2015-04-08 | 上海华力微电子有限公司 | Surface treatment method for improving copper interconnection reliability |
| CN102420173A (en) * | 2011-06-07 | 2012-04-18 | 上海华力微电子有限公司 | Surface treatment method for improving copper interconnection reliability |
| CN102446821A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Method used for reducing copper interconnection structure material damage after chemical machinery polishing |
| CN102446821B (en) * | 2011-08-29 | 2014-07-23 | 上海华力微电子有限公司 | Method used for reducing copper interconnection structure material damage after chemical machinery polishing |
| CN102456568A (en) * | 2011-09-29 | 2012-05-16 | 上海华力微电子有限公司 | Method for deposition of nitrogen-doped silicon carbide film |
| CN102517594A (en) * | 2011-12-15 | 2012-06-27 | 西安北方捷瑞光电科技有限公司 | Method for cleaning cerium-based polishing solution residues |
| CN102517594B (en) * | 2011-12-15 | 2013-07-24 | 西安北方捷瑞光电科技有限公司 | Method for cleaning cerium-based polishing solution residues |
| CN103839880A (en) * | 2012-11-27 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN104112699A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating bump effect in semiconductor structure |
| CN104157603B (en) * | 2013-05-15 | 2017-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for enhancing combination strength of metal copper and NDC interface |
| CN104157603A (en) * | 2013-05-15 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | Method for enhancing combination strength of metal copper and NDC interface |
| CN104637863A (en) * | 2013-11-14 | 2015-05-20 | 盛美半导体设备（上海）有限公司 | Tungsten plug formation method |
| CN104900481A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Method for cleaning bonding pads |
| CN104451492A (en) * | 2014-11-14 | 2015-03-25 | 无锡阳工机械制造有限公司 | Surface treatment method for lead-tin alloy |
| CN104451493A (en) * | 2014-11-14 | 2015-03-25 | 无锡阳工机械制造有限公司 | Copper alloy surface treating method |
| CN105845621B (en) * | 2015-01-17 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices and processing method when beyond Q-time |
| CN105845621A (en) * | 2015-01-17 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Method of forming semiconductor device and processing method for Q-time exceeding of semiconductor device |
| CN107895687A (en) * | 2017-11-15 | 2018-04-10 | 上海华虹宏力半导体制造有限公司 | A kind of method for improving metal capacitance TDDB performances |
| CN110158100A (en) * | 2019-04-20 | 2019-08-23 | 无锡天杨电子有限公司 | A method of cleaning silicon nitride ceramics copper-clad plate black surround |
| CN110158100B (en) * | 2019-04-20 | 2021-01-15 | 无锡天杨电子有限公司 | Method for cleaning black edge of silicon nitride ceramic copper-clad plate |
| CN111029298A (en) * | 2019-12-11 | 2020-04-17 | 武汉新芯集成电路制造有限公司 | Manufacturing method of copper interconnection layer |
| CN112885709A (en) * | 2021-01-13 | 2021-06-01 | 中电化合物半导体有限公司 | Preparation method of silicon carbide epitaxial structure and semiconductor device |
| CN112885709B (en) * | 2021-01-13 | 2024-03-22 | 中电化合物半导体有限公司 | Preparation method of silicon carbide epitaxial structure and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102044474B (en) | 2015-04-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102044474B (en) | Surface treatment method of copper metal layer subjected to chemically mechanical polishing | |
| US8143162B2 (en) | Interconnect structure having a silicide/germanide cap layer | |
| JP4288251B2 (en) | Method for forming a semiconductor interconnect structure | |
| US7718548B2 (en) | Selective copper-silicon-nitride layer formation for an improved dielectric film/copper line interface | |
| US7557447B2 (en) | Semiconductor device and method for manufacturing same | |
| KR20080100153A (en) | Improving adhesion and minimizing oxidation on electroless co alloy films for integration with low k inter-metal dielectric and etch steo | |
| JPWO2008078649A1 (en) | Semiconductor device and manufacturing method thereof | |
| JP4548280B2 (en) | Manufacturing method of semiconductor device | |
| US7413985B2 (en) | Method for forming a self-aligned nitrogen-containing copper silicide capping layer in a microstructure device | |
| US20120070915A1 (en) | Method for copper hillock reduction | |
| US20090176367A1 (en) | OPTIMIZED SiCN CAPPING LAYER | |
| US20130309866A1 (en) | Method of manufacturing a semiconductor device | |
| JP4191692B2 (en) | Method for forming SiC-based film and method for manufacturing semiconductor device | |
| JP2006179948A (en) | Semiconductor device and method of manufacturing device | |
| JP4655725B2 (en) | Manufacturing method of semiconductor device | |
| CN1976020A (en) | Interconnection structure and forming method thereof | |
| Chhun et al. | Impact of introducing CuSiN self-aligned barriers in advanced copper interconnects | |
| Chhun et al. | Influence of SiH4 process step on physical and electrical properties of advanced copper interconnects | |
| US11289423B2 (en) | Ultra-thin diffusion barrier | |
| US6911378B2 (en) | Stabilization of fluorine-containing dielectric materials in a metal insulator wiring structure | |
| JP2006294679A (en) | Semiconductor apparatus and manufacturing method thereof | |
| Gosset et al. | Self aligned barrier approach: overview on process, module integration and interconnect performance improvement challenges | |
| KR100591183B1 (en) | Method for forming inter metal dielectric of semiconductor device using copper damascene process | |
| Goldberg et al. | Compatibilities of dielectric films | |
| Hohage et al. | A copper-dielectric cap interface with high resistance to electromigration for high performance semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING (BEIJING) INTERNATIONA Effective date: 20121029 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20121029 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |