CN102044474B - Surface treatment method of copper metal layer subjected to chemically mechanical polishing - Google Patents
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Abstract
The invention relates to a surface treatment method of a copper metal layer subjected to chemically mechanical polishing, which comprises the steps of: providing a semiconductor substrate, wherein a dielectric layer is arranged on the surface of the semiconductor substrate, an opening is formed in the dielectric layer, metal copper is filed in the opening; carrying out chemically mechanical polishing on the semiconductor substrate until the metal copper in the opening is level to the surface of the dielectric layer; cleaning the dielectric layer and the surface of the metal copper with an alkali preparation; preprocessing surface plasma on the dielectric layer and the surface of the metal copper; and forming an etching stopping layer on the dielectric layer and the surface of the metal copper. Through simple regulation of the process, the invention avoids oxidization of the surface of the copper and the diffusion of copper ions in the dielectric layer, repairs the crystal lattice and the surface state of the dielectric layer to be a certain extent, improves the electric performance parameters of breakdown voltage, TDDB (Time Dependent Dielectric Breakdown), and the like, and enhances the element performances.
Description
Technical field
The present invention relates to field of semiconductor technology, the surface treatment method particularly after a kind of copper metal layer chemico-mechanical polishing.
Background technology
Along with the development of semiconductor technology, the physical dimension of semiconductor device continues to reduce, and has reached 32nm magnitude at present, constantly reducing with dimensions of semiconductor devices, and new ghost effect constantly occurs.Wherein RC postpones is one of key factor affecting device reaction speed.For addressing this problem, needing to improve metal interconnect structure and postponing to reduce RC.Corresponding technical scheme comprises the conductivity improving interconnecting metal and dielectric constant (k) value reducing dielectric layer.In the technique of below 90nm, copper has replaced aluminium comprehensively becomes interconnecting metal.Copper has better conductivity than aluminium, and electromigration effect is also less.About dielectric layer material, new material (k < 2.7) the also extensive use of low-k (low k), to replace traditional oxide layer.But compared with oxide layer, advanced low-k materials is structurally usually loose porous, also slightly poor with the tack of packing material.
In integrated circuit fabrication, dual damascene (dual damascene) technique for forming copper interconnecting line on dielectric layer.One of them important step is chemico-mechanical polishing (CMP), for removing the unnecessary copper of dielectric layer surface, realizes planarization.But in a cmp process, the pollutant such as particle, byproduct of reaction of silicon chip surface meeting remaining slurry.Therefore usually all needing through cleaning to remove these pollutants after the cmp process, avoiding defect introduction means and causing integrity problem.
In dual-damascene technics, usually on channel bottom and sidewall deposit layer of metal barrier layer (barrier) fill copper in groove before, its composition is titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN).Its effect prevents copper to be diffused in dielectric layer.And also need similar dielectric barrier to prevent the diffusion of copper in copper line surface.For the structure that metal-insulator semiconductor in device (MIS) is such, usually select silicon nitride (Si
3n
4) or phosphorosilicate glass (PSG) diffuse in silicon and dielectric layer to prevent copper ion as diffusion impervious layer.Therefore, the reliability of surface state on low dielectric coefficient medium layer of copper and dielectric layer has larger impact, is mainly manifested in the parameter such as puncture voltage (VBD), time correlation dielectric breakdown (timedependent dielectric breakdown:TDDB).
Based on foregoing, in the semiconductor technology of below 65nm, the integrity problem of low dielectric coefficient medium layer is the key factor affecting device performance.Publication number be 20080047592 U.S. Patent application propose a kind of method using cleaning silicon chip surface after cmp, the method is applicable to the situation that dielectric layer is conventional oxidation layer or advanced low-k materials, for the situation of advanced low-k materials, then mainly inquire into the impact of this cleaning method on device topography, the not mentioned improvement to electrical parameter aspect.
Therefore, need to propose one and clean after the cmp process and surface-treated effective ways, improve the electric property of low dielectric coefficient medium layer.
Summary of the invention
The problem that the present invention solves is to provide the surface treatment method after a kind of copper metal layer chemico-mechanical polishing, can improve the reliability of low dielectric coefficient medium layer, and what extend dielectric layer punctures the life-span.
For solving the problem, the invention provides the surface treatment method after a kind of copper metal layer chemico-mechanical polishing, the cleaning fluid after CMP is basic formulations, before etching stop layer is formed, carry out gaseous plasma preliminary treatment.Comprise the following step:
There is provided Semiconductor substrate, described semiconductor substrate surface has dielectric layer, is formed with opening in described dielectric layer, is filled with metallic copper in described opening;
Carry out chemico-mechanical polishing to described Semiconductor substrate, the metallic copper to described opening flushes with dielectric layer surface;
The surface of basic formulations to described dielectric layer and metallic copper is used to clean;
To the surface plasma preliminary treatment of described dielectric layer and metallic copper;
Etching stop layer is formed on the surface of described dielectric layer and metallic copper.
Optionally, the pH value of described basic formulations is 9 ~ 13.
Optionally, the pretreated gas of described gaseous plasma is selected from ammonia (NH
3), nitrogen (N
2), helium (He), hydrogen (H
2).
Optionally, the flow of described ammonia is 100 ~ 200sccm.
Optionally, the pretreated reaction temperature of described gaseous plasma is 360 ~ 400 DEG C.
Optionally, the described gaseous plasma pretreated process time is 15 ~ 20sec.
Optionally, described dielectric layer is advanced low-k materials.
Optionally, described etching stop layer is silicon nitride (Si
3n
4), nitrogen-doped silicon carbide (NDC).
Optionally, the formation method of described etching stop layer is low-pressure chemical vapor phase deposition (LPCVD), plasma enhanced CVD (PECVD).
Compared with prior art, such scheme has the following advantages: by the simple adjustment to technological process, basic formulations is used to clean after CMP, the preliminary treatment of advance promoting the circulation of qi bulk plasmon is formed to again at etching stop layer, avoid oxidation and the copper ion Driftdiffusion in the dielectric layer on copper surface, and repaired lattice and the surface state of dielectric layer to a certain extent, improve the electric parameters such as puncture voltage, time correlation dielectric breakdown parameter (TDDB), improve device performance.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawing indicates identical part.The drafting of accompanying drawing, not deliberately according to actual ratio, focuses on purport of the present invention is shown.In the accompanying drawings, for cheer and bright, part layer and region are amplified.
Fig. 1 is the schematic flow sheet of the surface treatment method after the copper metal layer chemico-mechanical polishing of one embodiment of the present of invention;
Fig. 2 to Fig. 3 is the cross-sectional view of the surface treatment method after the copper metal layer chemico-mechanical polishing of one embodiment of the present of invention;
Fig. 4 is the structural representation that dielectric layer punctures test;
Fig. 5,6 is Weibull distribution figure of prior art and electric performance test result of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
Method provided by the invention is not only applicable to the copper metal layer CMP aftertreatment technology that dielectric layer is advanced low-k materials, is applicable to the situation that dielectric layer material is other material types yet.
First briefly introduce relevant technological process, what choose in the present embodiment is the dielectric layer of metallic intermediate layer (inter-metal).In addition, also correspondingly can be generalized to the CMP of other levels, to other metal levels as the dielectric layer of the first metal layer (Metal 1), top layer metallic layer (top metal) also therewith roughly the same.Fig. 1 shows the process flow diagram of the surface treatment method after the copper metal layer chemico-mechanical polishing of one embodiment of the present of invention.
As shown in Figure 1, perform step S110, Semiconductor substrate is provided, described semiconductor substrate surface has dielectric layer, be formed with opening in described dielectric layer, be filled with metallic copper in described opening, described metallic copper fills up described opening and covers on described dielectric layer surface; Perform step S120, carry out chemico-mechanical polishing to described Semiconductor substrate, the metallic copper to described opening flushes with described dielectric layer surface; Perform step S130, use basic formulations to clean described metallic copper and dielectric layer surface; Perform step S140, gaseous plasma preliminary treatment is carried out to described metal level and dielectric layer surface; Perform step S150, described metallic copper and dielectric layer surface form etching stop layer.
Fig. 2 and Fig. 3 gives the cross-sectional view of the surface treatment method after the copper metal layer chemico-mechanical polishing of one embodiment of the present of invention.
With reference to Fig. 2, Semiconductor substrate is provided, described Semiconductor substrate is formed with etching stop layer 210 and low dielectric coefficient medium layer 220, described dielectric layer 220 is formed with oxide layer 230, groove is there is in described dielectric layer 220 and oxide layer 230, described groove is opened to etching stop layer less than 210, exposes described Semiconductor substrate.Be formed with barrier layer 240 in described groove, described barrier layer 240 can be tantalum (Ta), tantalum nitride (TaN), is tantalum nitride in the present embodiment.Its effect prevents metallic copper in groove to Driftdiffusion in low dielectric coefficient medium layer 220.Then in groove, metallic copper is filled, form copper metal layer 250, formation method has physical vapor deposition (PVD), chemical vapor deposition (CVD), ionization PVD, plating, physical vapor deposition is selected at this, after copper metal layer 250 is formed, the copper spilling groove having part unnecessary covers dielectric layer 220 on the surface.
With reference to Fig. 3, carry out chemico-mechanical polishing afterwards, remove copper unnecessary beyond groove and be positioned at the barrier layer 240 of groove two side roof part, oxide layer 230 and certain media layer 220, form copper metal layer 250 ', dielectric layer 220 ' and barrier layer 240 ', the metal copper layer 250 ' in described groove is flushed with the surface of described dielectric layer 220 '.Because in CMP process, the pollutant such as polishing fluid, byproduct of reaction all can remain in polished surface, even can infiltrate in dielectric layer 220 ', dielectric layer 220 ' is damaged, therefore be necessary the pollutant carrying out cleaning to remove substrate surface after the cmp process.
In prior art, the main pollutant adopting acidic formulation to remove substrate surface, the pH value of described acidic formulation is about 1 ~ 2, and its active ingredient mainly citric acid, the consumption of single silicon chip is 38 ~ 42ml, and scavenging period is 160 ~ 170 seconds.
In theory, in sour environment, the oxidability of acid ion is comparatively strong, has stronger oxidizability, easily the copper of flute surfaces is oxidized to Cu
+or Cu
2+if there is oxygen element to exist, cupric oxide (CuO) and cuprous oxide (Cu can be formed on the surface of copper metal layer 250 '
2o) mixture.In addition, can form etching stop layer (stop layer) on copper metal layer 250 ' and dielectric layer 220 ' in subsequent technique, its composition is generally silicon nitride (Si
3n
4), and one of reacting gas forming silicon nitride is silane (SiH
4), in course of reaction, silane easily and copper react and form the silicide CuSi of copper
x.So the many kinds of substance form such as silicide of cupric oxide, cuprous oxide, copper can be there is on the surface of copper metal layer 250 '.Copper ion (Cu in these materials
2+, Cu
+) be easily activated and spread in described dielectric layer 220.In addition, because CMP process can cause certain damage to the lattice structure on dielectric layer 220 ' surface, there is the chain link of some fractures, this more exacerbates copper ion to the diffusion in dielectric layer 220 '.
After the cmp process, carry out multinomial electrical parameter test, wherein main one is puncture voltage.As shown in Figure 4, when the puncture voltage of tested media layer 220 ', can using the copper metal in adjacent two grooves as test electrode, one of them ground connection, another applies positive voltage, the puncture voltage of dielectric layer 220 ' between test trenches.There is the copper ion (Cu of different valence state in the surface due to copper metal layer 250 '
+, Cu
2+), and the dielectric layer 220 ' surface be between groove causes certain lattice damage due to CMP, has the surface portion that part copper ion diffuse enters described dielectric layer 220 '.Because dielectric layer 220 ' surface exists copper ion, reduce the puncture voltage of device, adverse influence is caused to device performance.
As mentioned above, for improving the breakdown characteristics of low dielectric coefficient medium layer, improving it and puncturing the life-span, need the generation as far as possible reducing or eliminating copper ion, thus will reduce the oxide of copper and the generation of silicide, and also must repair the damage that CMP causes dielectric layer in addition.Therefore, the cleaning after CMP seems particularly important, by cleaning fluid is replaced by basic formulations by original acidic formulation in the present invention, reduces the oxide of copper and the generation of silicide.The concrete composition of alkaline reagent used is: ammoniacal liquor, BTA (BTA), hydrogen peroxide, surfactant (being specially perfluorooctane sulfonate in the present embodiment), PH buffers etc., its pH value is about 9 ~ 13, and in the present embodiment, preferred scope is 12 ~ 13.Needed for single silicon chip, basic formulations consumption is about 30 ~ 32ml, and scavenging period is 145 ~ 150 seconds, and compared with prior art, scavenging period shortens about 15sec, and this is conducive to the raising of production capacity.Through measuring and calculating, the expense expenditure of required cleaning fluid also has decline to a certain degree, is conducive to reducing production cost.
Surface clean after using basic formulations to carry out CMP, the activity of the acid ion in alkaline environment is suppressed, and copper is not easily oxidized, therefore not easily forms the oxide of copper, thus can avoid copper ion Diffusion drift in the dielectric layer.In addition, basic formulations cleaning fluid also contributes to the lattice damage reducing dielectric layer 220 ' and copper metal layer 250 ' surface, and this is also conducive to the puncture voltage improving dielectric layer 220 '.
After cleaning completes, etching stop layer to be formed on dielectric layer 220 ' and copper metal layer 250 ' thereafter.Its material is selected from silicon nitride (Si
3n
4) or nitrogen-doped silicon carbide (NDC), the present embodiment selects silicon nitride.Formation method has low-pressure chemical vapor phase deposition (LPCVD), plasma enhanced CVD (PECVD), selects plasma enhanced CVD at this.Its reacting gas mainly contains ammonia (NH
3) and silane (SiH
4), as mentioned before, silane and copper effect can produce silicide, and this is also one of factor of copper ion drift, therefore needs the formation of the silicide preventing copper.
For avoiding Formation of silicide, need to carry out certain pretreating process to copper surface before silicon nitride is formed.For this reason more optimally, before silicon nitride deposition, a processing step is added: with ammonia (NH
3) plasma carries out preliminary treatment to dielectric layer 220 ' and copper metal layer 250 ' surface.This step can directly be carried out in the reaction chamber forming silicon nitride, does not therefore have large impact to the cost of technique.This pretreated related process parameters is: ammonia flow 100 ~ 200sccm, is preferably 150sccm; Reaction pressure is 5torr; Reaction temperature is 360 ~ 400 DEG C, is preferably 370 DEG C; Process time is 15 ~ 20sec, is preferably 18sec.Because the process time is shorter, therefore less on the impact of production capacity.
Described semiconductor substrate surface is after ammonia plasmas preliminary treatment, and copper metal layer 250 ' and the nitrogen element in plasma of described flute surfaces can form the nitride of copper.Its Chemical bond energy is larger than the silicide of cupric oxide and copper, is not easy to be ionized, prevents copper ion Driftdiffusion in the dielectric layer.Cuprous nitride (the Cu of plasma pretreatment reaction generation simultaneously
3n) rete is equivalent to a barrier layer, copper metal layer 250 ' and silane reaction can be avoided to generate metal silicide, thus avoid the generation of copper ion when follow-up formation silicon nitride.On the other hand, in plasma preprocessing process, plasma can also do certain reparation to the lattice of impaired dielectric layer 220 ', improves the surface state of dielectric layer 220 ', weakens copper ion elegant diffusion wherein.
Except utilizing ammonia plasma treatment to carry out except preliminary treatment, the inactive gaseous plasma of other chemical property also can play the effect of repairing dielectric layer surface characteristic, such as nitrogen (N
2), hydrogen (H
2) or inert gas, described inert gas can be helium (He).These gases can repair the impaired lattice structure of dielectric layer, weaken copper ion Driftdiffusion wherein.
For the technique effect that assessment improves, the device formed for prior art and the present invention carries out electrical performance testing respectively.Test structure with reference to Fig. 3, test to as if be formed with the Semiconductor substrate of the first metal layer (M1), the dielectric layer gap length between two grooves is 0.12 μm.Fig. 5 is the Weibull distribution (Weibull distribution) of the device aging test failure time of prior art gained, and Fig. 6 is the Weibull distribution figure of the device aging test failure time of gained of the present invention.Test environment temperature is 125 DEG C, and test bias voltage chooses 54V, 56V, 58V tri-kinds of conditions respectively, obtains the straight line of three matchings.Transverse axis represents the component failure time, longitudinal axis representative proportion in full wafer chip.Relatively two figure are visible, and for 54V test voltage, prior art gained linear gradient is 2.99, and adopts gained linear gradient of the present invention to be 4.04, and slope corresponding to the present invention obviously increases, and this shows that the convergence of test point has larger improvement.
In addition, improvements of the present invention be also show to the test of time correlation dielectric breakdown parameter (TDDB).Testing length is 3.45cm, and voltage accelerated factor is 0.42, under calculating prior art, has the probability silicon chip life-span of 1 ‰ lower than 3160, then has the probability silicon chip life-span of 1 ‰ lower than 4780 years for the present invention by extrapolation.Be extrapolated to the test result that 100m is long again: under prior art, have the probability silicon chip life-span of 1 ‰ lower than 227 years, then have the probability silicon chip life-span of 1 ‰ lower than 658 years for the present invention.If it is long to be extrapolated to 225m, test result is respectively: under prior art, has the probability silicon chip life-span of 1 ‰ lower than 147 years, then has the probability silicon chip life-span of 1 ‰ lower than 538 years for the present invention.As can be seen here, compared to prior art, TDDB of the present invention adds 2 ~ 3 times, and device lifetime obtains significant prolongation.
The present invention is by the simple adjustment to technological process, cleaning fluid after CMP is replaced by basic formulations by acidity, ammonia plasma process is carried out again before etching stop layer silicon nitride deposition, avoid oxidation and the copper ion Driftdiffusion in the dielectric layer on copper surface, and in the lattice to a certain degree repairing low dielectric coefficient medium layer and surface state, improve the electric parameters such as puncture voltage, time correlation dielectric breakdown parameter (TDDB), improve device performance.
Although the present invention with preferred embodiment openly as above; but be not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (8)
1. the surface treatment method after copper metal layer chemico-mechanical polishing, is characterized in that, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface has dielectric layer, and the material of described dielectric layer is medium with low dielectric constant, is formed with opening, is filled with metallic copper in described opening in described dielectric layer;
Carry out chemico-mechanical polishing to described Semiconductor substrate, the metallic copper to described opening flushes with dielectric layer surface;
Use the surface of basic formulations to described dielectric layer and metallic copper to clean, the pH value of described basic formulations is 9 ~ 13, and its main component comprises ammoniacal liquor, BTA, hydrogen peroxide, perfluorooctane sulfonate;
To the surface plasma preliminary treatment of described dielectric layer and metallic copper, in described plasma preliminary treatment, the flow of ammonia is 100 ~ 200sccm, reaction pressure is 5torr, reaction temperature is 360 ~ 400 DEG C, in addition, the pretreated gas of described plasma also comprises nitrogen, hydrogen or inert gas, generates cuprous nitride rete with the surface reaction at metallic copper;
Etching stop layer is formed on the surface of described dielectric layer and metallic copper.
2. the surface treatment method after copper metal layer chemico-mechanical polishing according to claim 1, is characterized in that, the pretreated gas of described plasma is selected from ammonia, nitrogen, helium, hydrogen.
3. the surface treatment method after copper metal layer chemico-mechanical polishing according to claim 1, is characterized in that, the flow of described ammonia is 150sccm.
4. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 1 or 3, is characterized in that, the pretreated reaction temperature of described plasma is 370 DEG C.
5. the surface treatment method after the copper metal layer chemico-mechanical polishing according to claim 1 or 2 or 3, is characterized in that, the described plasma pretreated process time is 15 ~ 20 seconds.
6. the surface treatment method after copper metal layer chemico-mechanical polishing according to claim 1, is characterized in that, the pretreated gas of described plasma comprises helium.
7. the surface treatment method after copper metal layer chemico-mechanical polishing according to claim 1, it is characterized in that, described etching stop layer is selected from silicon nitride, nitrogen-doped silicon carbide.
8. the surface treatment method after copper metal layer chemico-mechanical polishing according to claim 7, is characterized in that, the formation method of described etching stop layer is low-pressure chemical vapor phase deposition, plasma enhanced CVD.
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| CN102420173B (en) * | 2011-06-07 | 2015-04-08 | 上海华力微电子有限公司 | Surface treatment method for improving copper interconnection reliability |
| CN102446821B (en) * | 2011-08-29 | 2014-07-23 | 上海华力微电子有限公司 | Method used for reducing copper interconnection structure material damage after chemical machinery polishing |
| CN102456568A (en) * | 2011-09-29 | 2012-05-16 | 上海华力微电子有限公司 | Method for deposition of nitrogen-doped silicon carbide film |
| CN102517594B (en) * | 2011-12-15 | 2013-07-24 | 西安北方捷瑞光电科技有限公司 | Method for cleaning cerium-based polishing solution residues |
| CN103839880A (en) * | 2012-11-27 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
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| CN104157603B (en) * | 2013-05-15 | 2017-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for enhancing combination strength of metal copper and NDC interface |
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| CN104900481B (en) * | 2014-03-04 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | The method for cleaning pad |
| CN104451493A (en) * | 2014-11-14 | 2015-03-25 | 无锡阳工机械制造有限公司 | Copper alloy surface treating method |
| CN104451492A (en) * | 2014-11-14 | 2015-03-25 | 无锡阳工机械制造有限公司 | Surface treatment method for lead-tin alloy |
| CN105845621B (en) * | 2015-01-17 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices and processing method when beyond Q-time |
| CN107895687B (en) * | 2017-11-15 | 2020-07-17 | 上海华虹宏力半导体制造有限公司 | Method for improving TDDB performance of metal capacitor |
| CN110158100B (en) * | 2019-04-20 | 2021-01-15 | 无锡天杨电子有限公司 | Method for cleaning black edge of silicon nitride ceramic copper-clad plate |
| CN111029298A (en) * | 2019-12-11 | 2020-04-17 | 武汉新芯集成电路制造有限公司 | Manufacturing method of copper interconnection layer |
| CN112885709B (en) * | 2021-01-13 | 2024-03-22 | 中电化合物半导体有限公司 | Preparation method of silicon carbide epitaxial structure and semiconductor device |
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