JP2006294679A - Semiconductor apparatus and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a wiring structure for reducing damage to a low-dielectric-constant film generated when performing plasma treatment containing NH<SB>3</SB>, and reducing a wiring delay due to an increase in a relative dielectric constant before forming a barrier film on a wiring surface. <P>SOLUTION: The method of manufacturing a semiconductor apparatus comprises a process for forming an insulating film having a relative dielectric constant of 3 or smaller on a substrate, a process for forming wiring made of Cu in the insulating film, a process for supplying reducing gas on the wiring surface, and a process for forming the barrier film on the wiring after supplying the reducing gas. As a result, after the wiring structure is formed, no plasma is supplied to the wiring surface before forming the barrier film, thus preventing the low-dielectric-constant film from being damaged and preventing a gate oxide film, or the like from deteriorating. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a wiring forming technique having a Cu / low dielectric constant film wiring in order to suppress wiring delay.

  In a semiconductor device using a processing dimension of 0.25 μm or more, since the wiring interval has become narrower, the electric parasitic capacitance generated between the wirings has increased. The delay time due to the RC delay cannot be ignored compared to the time required for turning on and off the transistor. For this reason, it is necessary to reduce the electric parasitic capacitance between the wirings in order to achieve miniaturization.

  In order to reduce the electric parasitic capacitance between the wirings, it is necessary to reduce the relative dielectric constant of the insulating film between the wirings in the same layer and between different wiring layers. Therefore, the wiring resistance value is reduced by changing the wiring metal from Al to Cu.

  However, Cu tends to diffuse in the insulating film due to thermal diffusion and electric field diffusion, and thus may cause leakage between wirings. Therefore, in order to prevent Cu diffusion, it is necessary to cover the Cu wiring with a barrier film. Since a damascene process, which is a buried wiring structure, is generally used for Cu wiring, the side wall and the lower part of the Cu wiring are usually made of a conductive barrier metal such as TaN and Ta, and the upper part is made of a non-conductive SiN insulating film. It has been used as a barrier film.

  However, in the next generation device, for example, a device having a size of 0.09 μm or more, a reduction in electric parasitic capacitance is increasingly required. Therefore, in order to lower the dielectric constant of the SiN film having a relative dielectric constant of 7.0, instead of the SiN film, an SiC film having a relative dielectric constant of about 4.5 to 5.0, or an SiC film for preventing leakage current in the SiC film. An SiCN film or the like in which N is added to is used.

  Further, in the 45 nm device and later, in order to set the relative dielectric constant of the barrier film to 0, a change from the SiCN film to the conductive film is being studied. For example, introduction of a technique of covering only the Cu wiring with a conductive barrier film such as W or CoWP is under consideration.

  Here, a conventional method for manufacturing a semiconductor device will be described with reference to FIG.

  First, as shown in FIG. 6A, a groove is formed in a first low dielectric constant film 1 having a thickness of 600 nm formed on a silicon substrate (not shown) by using a lithography method. Thereafter, TaN barrier metal 2 is formed by sputtering, and subsequently Cu3 is formed in the wiring groove by using a plating method. Thereafter, the TaN barrier metal 2 and Cu3 protruding from the wiring trench are removed by CMP to form a trench wiring having a depth of 300 nm. When the TaN barrier metal 2 and Cu3 protruding from the wiring trench are removed by the CMP process, a liquid containing an abrasive is supplied to the Cu surface. Thereafter, when the CMP process ends and the abrasive is removed, the surface of Cu embedded in the wiring trench is exposed to the atmosphere and oxidized. If there is a Cu oxide layer on the surface of the wiring, Cu oxide is less dense than non-oxidized Cu, so Cu easily diffuses through this portion. As a result, electromigration tends to occur and the problem of reduced reliability occurs.

Therefore, next, as shown in FIG. 6B, before depositing a barrier film on the Cu wiring, the surface of the Cu wiring is exposed to plasma of a gas containing NH ₃ (Patent Document 1). As a result, the copper oxide formed on the Cu film surface can be removed.

Thereafter, as shown in FIG. 6C, a SiCN film 5 is formed as a barrier film on the Cu wiring. The above process is repeated to form a semiconductor device having a Cu wiring in the low dielectric constant film.
JP 11-330246 A TJDalton et al., IITC2004, paper 8.10 NIKKEI MICRODEVICES March 2005 P.53 J. Noguchi et al., Proc. Of IRPS (2000), p.339-343 M. Sekiguchi et al., Jpn. J. Appl. Phys. 35 (1996), p.1111-1114

However, when the dielectric constant of the low dielectric constant film is further reduced, for example, when a film having a relative dielectric constant of 3.0 or less is used, the low dielectric constant film may be a SiOCH film including a CH ₃ group or a hole, MSQ, SiLK, or the like. A membrane is mentioned. However, when the surface of such a low dielectric constant film is exposed to plasma containing NH ₃ , there is a problem that the C portion in the film is ashed and the dielectric constant of the low dielectric constant film eventually increases (
, See).

That is, in the step shown in FIG. 6B, when a SiOCH film including MS ₃ and vacancies, MSQ, or the like is used as the insulating film, when a plasma containing NH ₃ is supplied to the surface of the insulating film, a portion including C is included. Ashed. As a result, the dielectric constant on the surface of the insulating film increases and the wiring capacitance increases. Therefore, there is a problem that the speed of the wiring circuit is reduced and wiring delay occurs.

Further, the portion of the insulating film containing C that has been bonded to Si (CH ₃ or the like) is lost, so that the Si bond may bond to the OH group or the like. In addition, since the large volume of CH ₃ is eliminated, the vacancies in the insulating film are increased, so that the insulating film can easily store moisture and the like, and the film may be peeled off due to the release of water in a later process.

  Furthermore, since the density of the insulating film is further reduced due to the increase of the holes, Cu is more easily diffused in the insulating film. As a result, there is a problem that leakage current between wirings is increased.

  In addition, when plasma is supplied to the wiring surface, particularly in a pattern having a long wiring connected to the gate electrode, charged particles accumulate, and the charge flows into the gate oxide film. As a result, the gate insulating film is damaged, an increase in leakage current from the gate electrode, a shift in CV characteristics, and the like occur. There is also a problem that the voltage Vt necessary to turn on the transistor fluctuates and the variation in circuit characteristics increases.

As described above, the present invention reduces the damage of the low dielectric constant film generated during the plasma treatment containing NH ₃ before forming the barrier film on the wiring surface, and reduces the problem of wiring delay due to the increase of the relative dielectric constant. An object of the present invention is to provide a method for forming a wiring structure. It is another object of the present invention to provide a semiconductor device in which deterioration of the gate insulating film due to plasma damage and Vt fluctuation are suppressed.

  In order to achieve the above object, as a first invention, a step of forming an insulating film having a relative dielectric constant of 3 or less on a substrate, a step of forming a wiring made of Cu in the insulating film, and a wiring surface There is provided a method for manufacturing a semiconductor device, comprising: supplying a reducing gas to the substrate; and forming a barrier film on the wiring after supplying the reducing gas.

  In this method, plasma is not supplied to the surface of the wiring after forming the wiring structure and before forming the barrier film, so that charged particles can be prevented from entering the substrate. Therefore, the low dielectric constant film can be prevented from being damaged and the gate oxide film can be prevented from being deteriorated.

  Further, as a second invention, a low dielectric constant insulating film having a relative dielectric constant of 3 or less formed on a substrate, a Cu wiring formed in the low dielectric constant film, a barrier film formed on the surface of the Cu wiring, The semiconductor device is characterized in that the interface between the SiCN film and the low dielectric constant film has the same value in the low dielectric constant film and in terms of C concentration and relative dielectric constant. .

According to the conventional method, when plasma is supplied to a film such as MSQ containing holes having a relative dielectric constant of 2.5 or less, for example, Si—CH ₃ bond in the insulating film surface is broken, and the relative dielectric constant of the film increases. (Ref.
). On the other hand, in the present invention, since plasma is not supplied to the surface of the low dielectric constant film, it is possible to prevent the bond in the insulating film from being broken by NH + or the like.

  Further, as a third invention, a low dielectric constant insulating film having a relative dielectric constant of 3 or less formed on a substrate, a Cu wiring formed in the low dielectric constant film, a barrier film formed on the surface of the Cu wiring, There is no N peak at the interface between the barrier film and the Cu wiring surface, and the interface between the SiCN film and the low dielectric constant film is the same as the inside of the low dielectric constant film, in terms of C concentration and relative dielectric constant. A semiconductor device characterized by having the following values is provided.

It is known that when a Cu surface is exposed to plasma containing N, NH ⁺ or the like charged to ⁺ is incident on the substrate, so that Cu and N are combined (
See). Further, when plasma is irradiated, N also enters the SiOC on the surface of the low dielectric constant film, and is combined with Si to become SiN or the like, which may increase the relative dielectric constant of the low dielectric constant film. Therefore, in the present invention, since plasma is not supplied as a pretreatment before forming the barrier film on the low dielectric constant film and the wiring surface, it is possible to prevent charged particles from entering the substrate. As a result, since Cu on the wiring surface and C and N on the low dielectric constant film are not bonded, an increase in the conductivity of Cu and an increase in the relative dielectric constant on the surface of the low dielectric constant film can be prevented. In general, bonds such as CuN and SiN are difficult to be formed only by a thermal reaction at 400 ° C. or lower, and the addition of plasma energy has a great influence on the bond formation of CuN and SiN.

  Further, as a fifth invention, a low dielectric constant insulating film having a relative dielectric constant of 3 or less formed on a substrate, a Cu wiring formed in the low dielectric constant film, a barrier film formed on the surface of the Cu wiring, There is provided a semiconductor device characterized in that Cu on the surface of the Cu wiring is crystallized at the interface between the barrier film and the surface of the Cu wiring.

In general, when a plasma treatment containing N is performed on a metal, a high-resistance amorphous layer containing N is formed on the metal surface (
See). Although the thickness of this amorphous layer is considered to be 5 nm or less from the surface, there is a problem that in the future when the thickness of the wiring is about 100 nm, if the high resistance layer is 5 nm, the total wiring resistance will increase by 5%. . Therefore, if plasma is not used, ions do not exist, so that there is no phenomenon that ions such as NH + enter the substrate, and the problem that the surface of the Cu wiring becomes amorphous can be prevented.

Further, in the above invention, since plasma is not supplied as the surface treatment of the wiring surface, it can be seen that there is almost no deviation in CV characteristics due to plasma damage even when viewed in FIG. Incidentally, the NH ₃ Thermal Treatment condition in FIG. 7 is the case where the treatment is performed at 4.2 Torr, 345 ° C., NH ₃ : 760 sccm for 60 seconds. Here, the value of the gate voltage Vg indicating C = 6 pF shifts by 40 mV in the plasma processing, but it means that there is almost no deviation at 10 mV or less only by the heat treatment. As described above, it is effective to perform the heat treatment while supplying a reducing gas (for example, NH ₃ ) in a reduced pressure atmosphere even for the characteristic deviation of the gate oxide film.

According to the present invention, a Cu wiring having a low dielectric constant film having a relative dielectric constant of 3.0 or less is exposed to a reduced gas atmosphere of a reducing gas at 300 ° C. to 400 ° C. It is possible to avoid damage to the Si—CH ₃ group that becomes prominent in the low dielectric constant film, and to reduce the problem of wiring delay due to an increase in relative dielectric constant. In addition, it is possible to provide a semiconductor device in which the gate insulating film is not deteriorated due to plasma damage and the Vt variation is not caused, and a manufacturing method thereof.

  In addition, since the present invention does not use plasma as the surface treatment of the surface of the Cu wiring, the incident of charged particles to the substrate can be suppressed, and the bonding of Cu, a low dielectric constant film and N can be prevented. As a result, it is possible to prevent an increase in the conductivity of Cu and an increase in the relative dielectric constant of the surface of the low dielectric constant film.

In the present invention, since plasma is not supplied to the wiring surface before forming the barrier film after forming the wiring, the degree to which NH ⁺ or the like impairs the Si—CH ₃ bond can be reduced. As a result, it is possible to provide a semiconductor device in which the decrease in C concentration is small even on the surface of the low dielectric constant film.

  In the present invention, since the reducing gas is not supplied to the wiring surface in a plasma state, for example, ions containing N are not incident on the substrate, and the crystalline state of Cu at the interface between the barrier film and the Cu wiring surface becomes amorphous. Can be prevented. As a result, a semiconductor device in which the wiring resistance is unlikely to increase can be provided.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIG.

  First, as shown in FIG. 1A, a wiring groove (trench groove) is formed in a first low dielectric constant film 1 having a thickness of 600 nm formed on a silicon substrate (not shown). In this embodiment, a SiOC film having a relative dielectric constant of about 2.8 is used as the low dielectric constant film. Thereafter, the TaN barrier metal 2 and Cu3 formed on the substrate protruding from the wiring groove are removed by CMP, and a wiring (trench) having a depth of 300 nm made of TaN barrier metal 2 and Cu3 is formed in the wiring groove. .

Next, as shown in FIG. 1B, for example, the substrate is carried into a CVD apparatus at a pressure of 4.2 Torr and 345 ° C. Thereafter, NH ₃ gas is supplied onto the substrate at a flow rate of 760 sccm without plasma irradiation, and the substrate is held for 120 seconds.

The surface of the wiring formed on the substrate in the previous process is easily oxidized due to the influence of slurry or the like in the CMP process, and a Cu oxide layer may be formed during movement between devices. Since Cu oxide has a lower density than pure Cu, it is easier to electromigration. Therefore, the Cu oxide film is removed by supplying NH ₃ gas which is a reducing gas to the wiring surface. This process is a process that exhibits a particularly great effect in the present invention. This will be described in detail later.

Thereafter, as shown in FIG. 1C, when a wiring structure such as an insulating film is further laminated on the wiring, Cu of the lower wiring is diffused into the upper interlayer insulating film (for example, SiOC film). In order to prevent this, for example, a SiCN film 5 serving as a cap having a thickness of 50 nm is formed. For forming the SiCN film, a parallel plate type CVD apparatus is used, and the temperature is set to 300 to 400 ° C. and the pressure is set to 3.6 Torr. Further, a power of 0.58 W / cm ² is applied to the upper electrode at 13.56 MHz, and the semiconductor device is placed on the lower electrode side disposed at a position facing the upper electrode. Further, as a film forming gas, for example, a mixed gas of trimethylsilane (SiH (CH ₃ ) ₃ H / NH ₃ / He is used.

  Thus, a wiring structure made of a conductive film such as Cu is formed on the substrate. According to this method, a cap film that prevents the diffusion of the wiring metal is formed on the wiring surface, and unnecessary oxide films on the wiring surface are removed before the cap film is formed. The occurrence of defects can be reduced.

  The wiring surface treatment, which is a feature of the present invention, will be described below.

  First, FIG. 7 shows the result of studying the deviation of CV characteristics in the conventional method and the method of the present invention. Specifically, in the case of the capacitance C = 6 pF, the result of examining the voltage change when measuring 9 points in the wafer surface with the gate voltage Vg as the horizontal axis (V) and the cumulative frequency (%) as the vertical axis. It is shown in FIG. Here, the cumulative frequency is a mark for distinguishing different locations on the wafer surface. When there are nine measurement locations as in FIG. 7, the first is defined as 1/9. About 11%, the second is about 9%, or about 22%. In FIG. 7, since the statistics are changed so that the display of the gate voltage Vg is easy to see, the cumulative frequency at the ninth measurement location is not 100%, but the display method is shifted to the lower overall. It has become. However, since the deviation amount of each point of the cumulative frequency is equal, the change amount of Vg and the uniformity within the wafer surface can be read from FIG.

  Note that the results shown in FIG. 7 show that the pattern to be measured is a pattern in which a gate electrode having a gate film thickness of 7.0 nm and an area of 0.001 mm is connected to a gate electrode having an area 10 times larger by the conventional method and the method of the present invention The relationship between the gate voltage Vg and the cumulative frequency when the surface is processed is shown. Here, since the Vg value is shifted in accordance with the cumulative frequency, it is understood that the wafer surface is not completely uniform. The higher the in-plane uniformity of the wafer, the more constant the Vg value is, regardless of the cumulative frequency. Therefore, when the in-plane uniformity of the wafer is high, a graph perpendicular to the horizontal axis can be seen.

Next, the difference between the conventional method and the present invention will be described with reference to FIG. Here, the conventional method refers to the case where the wiring surface is installed in a reaction chamber set to 4.2 Torr, 345 ° C., and power 0.40 W / cm ² , and NH ₃ plasma is supplied to the substrate surface at a flow rate of 760 sccm for 60 seconds. ing. From the graph of FIG. 7, according to the conventional method, the curve of the cumulative frequency is translated by 40 mV as a whole compared to the case where the treatment using NH ₃ plasma is not performed, and the value of the gate voltage Vg is 40 mV in the NH ₃ plasma treatment. It shows that it shifts. In this study, an antenna composed of a gate electrode is used, but a result showing the same tendency can be obtained even if wiring is used instead. As described above, according to the conventional method, it is understood that the gate insulating film is damaged by plasma, changes the CV characteristics, and changes the Vt of the transistor.

On the other hand, in the method of the present invention, an NMOS capacitor: a pattern in which a gate electrode having a gate thickness of about 7.0 nm and an area of 0.001 mm is connected to a gate electrode having an area 10 times larger is set in a reaction chamber set to 4.2 Torr and 345 ° C. The value and change amount of the gate voltage Vg indicating C = 6 pF when NH ₃ gas is supplied to the substrate surface at a flow rate of 760 sccm for 60 seconds are shown. From the graph of FIG. 7, according to the method of the present invention, the curve of the cumulative frequency is 10 mV or less compared to the curve when the plasma treatment is not performed (Reference), and the deviation of the value of the gate voltage Vg is about 10 mV. It can be seen that it is suppressed. Therefore, it can be seen that in the present invention, damage to the gate insulating film is reliably reduced by not performing plasma irradiation.

In addition to the method of the present invention, a conventional SiO ₂ film or a SiOC film having a dielectric constant of about 3.0 or more with relatively high density and almost no voids is formed on a low dielectric constant film, and wiring after CMP is performed. A method of preventing the low dielectric constant film having holes on the surface from being exposed is also conceivable. However, the relative dielectric constant of the SiO ₂ film formed on the low dielectric constant film is 3.9, which reduces the effect of reducing the dielectric constant of the insulating film.

  Next, the adhesion of the Cu film and the SiCN film was improved by the method of the present invention, and the mechanism was verified.

  First, FIG. 2 shows the result of evaluating the adhesion at the SiCN / Cu interface by the nano scratch method. Here, the nano-scratch method scans the sample surface by applying a certain load to the probe of an atomic force microscope (AFM), so that the vertical load (critical load) at the time of interface destruction or deformation and horizontal The purpose is to monitor the direction force (horizontal load) and quantify the strength of adhesion at the interface. The greater the viewpoint, the higher the adhesion at the SiCN / Cu interface.

Specifically, FIG. 2 (a) (b), when forming a SiCN film without NH ₃ plasma process to the wiring surface (a conventional method 1), SiCN after the NH ₃ plasma process to the wiring surface When the film is formed (conventional method 2), the results of three measurements are shown for each case where the SiCN film is formed after the NH ₃ gas is simply supplied to the wiring surface instead of the plasma state (the present invention). . In particular, FIG. 2A shows the critical load (μN) on the vertical axis as an adhesion parameter, and the results of measurement under each condition are shown in FIG. 2B. The results of measurement under each condition with the load (μN) taken are shown.

2 (a) and 2 (b), it can be seen that the present invention shows numerical values between the conventional method 1 and the conventional method 2 for both the critical load and the horizontal load. Therefore, the adhesion between the SiCN film when the NH ₃ heat treatment of the present invention is performed and the Cu film as the wiring surface is intermediate between the case where the ammonia treatment is not performed and the case where the treatment is performed using the plasma ammonia gas. Value. In the case of plasma treatment, the adhesiveness is the highest. In the case of plasma, charged particles such as NH ⁺ are attracted to the electrode on the cathode side and are incident on the wiring surface, so that Cu and N bonds are likely to occur. Because.

It can also be seen that the adhesion of the method of the present invention is improved as compared with the case of the conventional method 1 in which the surface treatment is not performed. In particular, even when the second-layer wiring was formed, no film peeling was observed between the Cu wiring surface and the SiCN film, so that the adhesion between the SiCN film and the Cu wiring surface was sufficiently ensured. It is done. Furthermore, when NH ₃ gas is supplied to the Cu wiring surface in a reduced-pressure atmosphere, organic substances attached to the Cu surface after Cu-CMP are more likely to volatilize, and defects on the wiring surface can be further reduced.

Next, Table 1 summarizes the numerical values shown in the graph of FIG. Table 1 shows the values of the critical load and the horizontal load when the SiCN film is formed by two methods of the conventional method, and the values of the critical load and the horizontal load when the SiCN film is formed by the method of the present invention. Yes. In addition, as the plasma processing of the conventional method, specifically, processing of exposing to ammonia plasma for 30 seconds is performed before forming the SiCN film. Moreover, as a method of the present invention, a process of exposing the wiring surface to an ammonia stream for 120 seconds is performed. From Table 1, for no NH ₃ plasma process of the prior methods, the critical load is 1340MyuN, the horizontal load is 412MyuN, when forming a SiCN film after the plasma without NH ₃ gas treatment is a method of the present invention Is a critical load of 1700 μN and a horizontal load of 463 μN. Therefore, comparing the gas treatment according to the present invention and the case without the conventional method, the adhesion between the SiCN film and the Cu film is improved when the NH ₃ gas treatment according to the present invention is used. Recognize. When plasma-like NH ₃ plasma, which is another conventional method, is used, the critical load is 1970 μN, and the horizontal load is 596 μN. Therefore, it can be seen that, as a treatment of the Cu wiring surface, the use of plasma improves the adhesion in terms of improving the adhesion.

  Next, FIGS. 3A to 3C show Si and C at the interface between the SiCN film and the Cu film when the wiring structure formed using the conventional method and the method of the present invention is analyzed by Auger electron spectroscopy. , N, O, Cu element profiles are shown.

  FIG. 3A shows a SiCN film in the case where a SiCN film is continuously formed on the Cu wiring surface without processing the Cu wiring surface using ammonia plasma before forming the SiCN film on the Cu wiring surface. The element profile in the interface of Cu and Cu film is shown. According to this profile, it can be seen that, among the measured elements of Si, C, N, O, and Cu, O atoms have a peak indicating about 10% oxygen at the interface between the SiCN film and the Cu film.

Next, FIG. 3 (b) shows that the conventional method is used to supply NH ₃ plasma to the Cu wiring surface before forming the SiCN film on the Cu wiring surface to perform surface treatment, and then the SiCN film is applied to the Cu wiring surface. The element profile in the interface of a SiCN film | membrane and Cu film | membrane when formed in FIG. According to this profile, out of the measured Si, C, N, O, and Cu elements, the oxygen peak as shown in FIG. 3A disappears at the interface between the SiCN film and the Cu film. I understand that. That is, it can be seen that an oxide containing copper oxide or the like is sufficiently removed. It can also be seen that, unlike FIG. 3A, an N peak is shown at the interface between the SiCN film and the Cu film. This indicates that a mixed layer of Cu and N is formed at the interface due to the incidence of NH ⁺ during the NH ₃ plasma treatment. Thus, when N is large at the interface between the barrier film on the wiring surface and the wiring (Cu), there is a problem that the Cu resistance near the interface becomes high.

Further, FIG. 3 (c) shows that the method described in the first embodiment of the present invention is used to form NH ₃ on the Cu wiring surface in the form of mere gas instead of plasma before forming the SiCN film on the Cu wiring surface. 2 shows an element profile at the interface between the SiCN film and the Cu film when the SiCN film is formed on the surface of the Cu wiring. According to this profile, out of the measured Si, C, N, O, and Cu elements, the oxygen peak as shown in FIG. 3A disappears at the interface between the SiCN film and the Cu film. I understand that. In addition, regarding the Cu and N profiles, it can be seen that the amount of N injected into the film is reduced as compared with the state of FIG.

  From the above, it can be seen that according to the method of the present invention, the oxygen peak and the N content at the interface between the Cu wiring surface and the SiCN film can be reduced as compared with the conventional method.

  Next, FIG. 4 is a graph showing the pretreatment dependence of the oxygen concentration at the interface between the SiCN film and the Cu wiring surface. Here, when the analysis is performed on the horizontal axis, the Ar sputtering time (seconds) is taken to bring out the surface in the depth direction of the sample, and the oxygen content (%) at the interface between the SiCN film and the Cu wiring is plotted on the vertical axis. . Specifically, these relationships are based on the following four conditions: (1) depositing a SiCN film without pretreatment, (2) depositing a SiCN film after pretreatment with ammonia plasma, (3) not in a plasma state In each case of pretreatment using mere gaseous ammonia for 60 seconds, and (4) pretreatment using mere gaseous ammonia instead of plasma for 120 seconds, the oxygen content at the sputtering time It shows a change. From this graph, when there is no pretreatment which is the condition of (1), about 10% of oxygen is present at the interface between the SiCN film and the Cu wiring surface as shown in FIG. However, by supplying ammonia gas to the wiring surface for 60 seconds as in (3) or ammonia gas to the wiring surface for 120 seconds as in (4), the oxygen content at the interface is reduced to about 4%. be able to. It can be seen from FIG. 4 that even when plasma ammonia gas is used as in (2), the oxygen content can be reduced only to about 4%.

  In other words, when the surface treatment of the wiring surface is performed using a plasma gas such as ammonia plasma, there is a problem that the resistance becomes high near the interface between the SiCN film as a barrier film and the Cu wiring due to N. There is. Therefore, in the present invention, by supplying a simple gas instead of plasma, the amount of N injected into the interface can be reduced, and the content of O that is also injected into the interface can be reduced.

  As described above, according to the present invention, it is possible to prevent an increase in resistance caused by N at the interface between the SiCN film and the Cu film while maintaining high adhesion between the SiCN film and the Cu film. As a result, a low-resistance wiring structure can be formed while improving the stress migration resistance and electromigration resistance of the Cu wiring structure.

In the present embodiment, the SiOC film having a relative dielectric constant of 3 is used as the first low dielectric constant film, but other films can also be used. In particular, when a film such as MSQ containing holes having a relative dielectric constant of 2.5 or less is used, the Si—CH ₃ bond is impaired during NH ₃ plasma ashing, and the portion of the surface in contact with the SiCN film on the low dielectric constant surface is damaged. A phenomenon occurs in which the C concentration of the low dielectric constant film is lower than that inside the low dielectric constant film. In this case, there is a problem that the relative dielectric constant of the film increases and the wiring capacitance increases.

Therefore, according to the method of the present invention, O injected into the wiring surface can be reduced without using plasma, so that N implantation into the wiring surface by plasma can be avoided. Further, since the plasma state gas is not supplied to the wiring surface, the energy of the reactive particles supplied to the wiring surface is relatively low, and the degree of damage to the Si—CH ₃ bond in the insulating film can be reduced.

In this embodiment, trimethylsilane gas is used as a source gas for forming the SiCN film, but tetramethylsilane (Si (CH ₃ ) ₄ ) may be used.

In this embodiment, in order to remove the oxide film on the surface of the Cu wiring film, a gas containing NH ₃ is used as the reducing gas. However, a mixed gas with other non-oxidizing gas may be used. I can do it. For example, you may mix with He etc. which are inert gas.

(Second Embodiment)
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIG. The present embodiment describes a semiconductor device and a manufacturing method thereof according to claim 5.

  First, as shown in FIG. 5A, a wiring trench (trench trench) is formed in a first low dielectric constant film 1 having a thickness of 600 nm formed on a silicon substrate (not shown). In this embodiment, a SiOC film having a relative dielectric constant of about 2.8 is used as the low dielectric constant film. Thereafter, the TaN barrier metal 2 and Cu3 formed on the substrate protruding from the wiring groove are removed by CMP, and a wiring (trench) having a depth of 300 nm made of TaN barrier metal 2 and Cu3 is formed in the wiring groove. .

Next, as shown in FIG. 5B, for example, the substrate is carried into a CVD apparatus at a pressure of 4.2 Torr and 345 ° C. Then, without irradiating with plasma, NH ₃ gas is supplied onto the substrate at a flow rate of 760 sccm in a reduced pressure atmosphere, and the substrate is held for 120 seconds.

The surface of the wiring formed on the substrate in the previous process is easily oxidized due to the influence of slurry or the like in the CMP process, and a Cu oxide layer may be formed during movement between devices. Since Cu oxide has a lower density than pure Cu, it is easier to electromigration. Therefore, the Cu oxide film is removed by supplying NH ₃ gas which is a reducing gas to the wiring surface. This process is a process that exhibits a particularly great effect in the present invention.

  Thereafter, as shown in FIG. 5C, when a wiring structure such as an insulating film is further laminated on the wiring, Cu or the like of the lower layer wiring diffuses into the upper interlayer insulating film (for example, SiOC film). In order to prevent this, for example, a CoWP film 5 serving as a cap having a thickness of 50 nm is formed. The CoWP film is formed using a selective plating method.

  By repeating the manufacturing steps as described above (FIGS. 6A to 6C), a semiconductor device having high adhesion between the CoWP film and the Cu wiring can be formed. Further, according to this method, a cap film made of a CoWP film 6 that prevents diffusion of wiring metal is formed on the wiring surface, and a reducing gas is supplied to the wiring surface under reduced pressure, thereby being injected into the Cu surface. Therefore, it is possible to provide a film having good adhesion to W. As a result, the movement of Cu at the W and Cu interface due to stress migration and electromigration can be suppressed. Thereby, stress and electromigration resistance of the Cu wiring are improved.

  Next, the process of FIG. 5B, which is a feature of the present invention, will be verified in detail.

In general, when a metal surface is subjected to plasma treatment containing N, a high-resistance amorphous layer containing N is formed on the metal surface. Although the thickness of this amorphous layer is considered to be 5 nm or less from the surface, there is a problem that in the future when the thickness of the wiring is about 100 nm, if the high resistance layer is 5 nm, the total wiring resistance will increase by 5%. . Therefore, if the gas is supplied not as plasma but as mere gas in the surface treatment, there is no plasma ion, so that a phenomenon that ions such as NH ⁺ enter the substrate can be suppressed. As a result, the phenomenon that the surface of the Cu wiring becomes amorphous can be prevented. In addition, selective growth of CoWP is difficult on an amorphous layer containing a large amount of impurities such as N formed when plasma pretreatment is used, compared to a clean Cu surface. Therefore, the method of performing the surface treatment by introducing the reducing gas under reduced pressure as in the present invention can prevent N from being injected into the wiring surface. As a result, by providing a novel method for manufacturing a semiconductor device, formation of an amorphous layer that inhibits selective growth of CoWP or the like can be prevented.

In this embodiment, a W film can be used as a diffusion preventing film instead of the CoWP film. In this case, a W film is selectively grown only on the Cu wiring by using a selective CVD method using WF ₆ and H ₂ gases. Specifically, the semiconductor device is moved into another reaction chamber, the temperature is 345 ° C., the pressure is 3 Torr, and WF ₆ and H ₂ are flowed at a ratio of 1: 3. At this time, the W film can be selectively grown on the Cu wiring by the CVD reaction of WF ₆ + 3H ₂ → W + 6HF.

  As described above, the present invention reduces plasma damage, generates electromigration, etc., particularly in a wiring structure made of a metal such as Cu formed in an insulating film made of a low dielectric constant film having copper as a wiring material. It is suitable for a semiconductor device that can be prevented, a manufacturing method thereof, and the like.

Sectional drawing of the process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention The figure which shows the critical load evaluation of the SiCN film | membrane and Cu film | membrane formed by this invention and the conventional method, and the value of a horizontal load The figure which shows the element profile in the interface of the SiCN film | membrane of this invention, and Cu film | membrane The figure which shows the element profile in the interface of the SiCN film | membrane of this invention, and Cu film | membrane Sectional drawing of the process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention Process cross section of conventional method The figure explaining the CV characteristic in this invention and the conventional method

Explanation of symbols

1 First low dielectric constant film 2 TaN barrier metal 3 Cu
4 Low dielectric constant film with plasma damage 5 SiCN film 6 CoWP film

Claims (7)

Forming an insulating film having a relative dielectric constant of 3 or less on the substrate;
Forming a wiring made of Cu in the insulating film;
Supplying a reducing gas on the wiring surface;
A method of manufacturing a semiconductor device, comprising: forming a barrier film on the wiring after supplying the reducing gas. The method of manufacturing a semiconductor device according to claim 1, wherein the step of supplying the reducing gas to the wiring surface is performed at a temperature of 300 to 400 ° C. The method of manufacturing a semiconductor device according to claim 1, wherein the reducing gas does not contain a plasma component. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the barrier film is SiCN, W, or CoWP. A low dielectric constant insulating film having a relative dielectric constant of 3 or less formed on the substrate;
Cu wiring formed in the low dielectric constant film,
A barrier film formed on the Cu wiring surface;
The interface between the SiCN film and the low dielectric constant film has the same value as that of the inside of the low dielectric constant film in terms of C concentration and relative dielectric constant. 6. The semiconductor device according to claim 5, wherein there is no N peak at the interface between the barrier film and the Cu wiring surface. 6. The semiconductor device according to claim 5, wherein Cu on the surface of the Cu wiring is crystallized at an interface between the barrier film and the surface of the Cu wiring.