CN102024811A - Electrostatic discharge protection circuit - Google Patents
Electrostatic discharge protection circuit Download PDFInfo
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- CN102024811A CN102024811A CN 200910195957 CN200910195957A CN102024811A CN 102024811 A CN102024811 A CN 102024811A CN 200910195957 CN200910195957 CN 200910195957 CN 200910195957 A CN200910195957 A CN 200910195957A CN 102024811 A CN102024811 A CN 102024811A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
The invention relates to an electrostatic discharge protection circuit which comprises a plurality of NMOS (N-type metal-oxide semiconductor) tubes, and gates of the NMOS tubes are grounded and connected in parallel; a drain of each NMOS tube is connected with a bonding pad (Pad), the gates are grounded, sources are grounded, and substrates are grounded; the NMOS tubes are grouped, and each group comprises at least one NMOS tube; and the periphery of the NMOS tube of each group is surrounded by a P-well in a contact manner. The invention relates to the electrostatic discharge protection circuit which comprises a plurality of NFOD (N-type field oxide device) tubes connected in parallel; a drain of each NFOD tube is connected with the bonding pad (Pad), the sources are grounded, and the substrates are grounded; the NFOD tubes are grouped, and each group comprises at least one NFOD tube; and the periphery of the NFOD tube of each group is surrounded by the P-well in a contact manner. Therefore, the difference between parasitic NPN (negative-positive-negative) base resistance positioned at the middle and the parasitic NPN base resistance positioned on two sides in each group is smaller, when ESD (electrostatic discharge) pulses are added on a PAD (portable application description) for generating drain current which flows into the base resistance, all NPN base-emitters are positively biased, and all NPN are in uniform conduction.
Description
Technical field
The present invention relates to the static discharge technical field, design a kind of ESD protection circuit especially.
Background technology
Along with the integrated circuit fabrication process level enters the deep-submicron epoch of live width, the MOS element in the integrated circuit all adopts lightly doped drain (LDD, Lightly Doped Drain) structure, and silicide process has been widely used on the diffusion layer of MOS element.In order to reduce the diffusion series resistance of grid polycrystalline, adopted the manufacturing process of polycrystalline compounds simultaneously.Along with dwindling of integrated circuit component, the thickness of grid oxide layer of MOS element is more and more thinner, and the improvement of these manufacturing process can increase substantially the arithmetic speed of IC interior, and can improve the integrated level of circuit.But these improvement have brought a very big drawback, and promptly the easier static discharge (ESD, Electro Static Discharge) that is subjected to of deep submicron integrated circuit impacts and lost efficacy, thereby causes reliability of products to descend.
ESD is meant that a certain amount of electric charge transfers to the process of (for example chip) on another object from an object (for example human body).Anti-ESD harm requirement to integrated circuit all is based on body's static electricity preventing at present, and has set up manikin (HBM, Human Body Model).HMB sets up in the ESD model the earliest and one of topmost model.Its is described is the human body that takes place when a human hand that has static contacts the pin of the integrated circuit (IC) chip electric discharge phenomena to chip pin.Therefore, ESD is usually in the inner formation of input port, delivery outlet and the circuit from the power supply to ground of integrated circuit.This process can cause chip in a short period of time by a very large electric current, and the chip failure more than 35% is caused by ESD.
Referring to Fig. 1, this figure is a kind of esd protection circuit of the prior art.
A kind of esd protection circuit of the prior art is that (GGNMOS Gate-Ground-NMOS) composes in parallel by a plurality of grounded-grid NMOS.Fig. 1 only illustrates the connection diagram of a GGNMOS.The drain electrode connection pads Pad of GGNMOS promptly draws as the pin of circuit.The grid of GGNMOS and source grounding.
Referring to Fig. 2, this figure is the sectional view of the esd protection circuit that composes in parallel of a plurality of GGNMOS.
Esd protection circuit shown in Figure 2 is composed in parallel by 2nNMOS, and here, n is a natural number, grid G ground connection (not shown).B represents buck, i.e. p-well contact (general ground connection among the NMOS).
This circuit is when the esd protection, and the ESD electric current is by its parasitic NPN release (among the figure shown in the dotted line).The corresponding parasitic NPN of each NMOS.Be added in the drain electrode of NMOS as esd pulse, along with the rising of ESD voltage, have a leakage current that flows to p-well, the base stage of each parasitic NPN all contacts with p-well by a p-well resistance and is connected.When flowing through these p-well resistance, this leakage current just on resistance, produces pressure drop.B holds ground connection (0 current potential), and therefore ohmically pressure drop just equals the base potential of NPN.When the enough height of base potential of NPN make base-emitter generation positively biased, the NPN conducting ESD electric current that begins to release.Can find because the leakage current at each NMOS place is all the same under identical drain voltage, so the size of base resistance is just depended in the unlatching of NPN, and be in the NPN of the centre of domain more, its base resistance is big more, be R2+R1＞R1, R3+R2+R1＞R2+R1＞R1, by that analogy.The big more just easy more unlatching of the base resistance of NPN.Therefore when drain D added an esd pulse, the NPN in the middle of always being positioned at opened earlier, and the NPN on both sides does not open at this moment.As long as any one or several NPN open, just think that the esd protection circuit of this GGNMOS starts working, and the pairing voltage of this opening point is exactly trigger voltage.Referring to Fig. 3, the abscissa representative voltage, unit is V, and ordinate is represented electric current, and unit is A.Rightmost that point of curve A about 9.1V (for a certain 0.18um technology), this point is called the trigger point of esd protection device.In case one or several NPN opens; voltage can be dragged down rapidly; being reflected to has a voltage to return stagnant phenomenon among Fig. 3; along with ESD voltage continues to raise, the ESD electric current that flows through NPN is increasing subsequently, so voltage is also raising; be raised to second about 7.4V in breakover point place among the figure; claim this point to be that the second breakdown point of esd protection device, voltage diminish once more, the NPN of this moment of conducting just now will be burnt.
In sum; in the above-mentioned esd protection circuit; some NPN that open at first that have only mid portion are in discharge; because voltage can not exceed the trigger voltage (9.1V) of NPN always; therefore burnt up to these NPN; the NPN on both sides can not normally open, and then can not discharge, and does not also just have the esd protection effect.
Summary of the invention
The problem that the present invention solves provides a kind of esd protection circuit, and parasitic NPNs all in the ESD circuit is opened, and conducting homogeneity is good.
For addressing the above problem, the embodiment of the invention provides a kind of ESD protection circuit, comprising: the NMOS pipe of a plurality of grounded-grid parallel connections; The drain electrode connection pads Pad of each NMOS pipe, grounded-grid, source ground, substrate ground connection; With the grouping of described NMOS pipe, every group comprises at least one NMOS pipe; Surround with the P-well contact around every group of NMOS pipe.
Preferably, every group comprises two NMOS pipes.
Preferably, every group comprises the four NMOS pipe.
Preferably, every group comprises that six NMOS pipe or every group comprise eight NMOS pipes.
Preferably, described every group of NMOS pipe around and a circle n-well is set between the P-well of the outer ring contact.
The embodiment of the invention provides a kind of ESD protection circuit, comprising: the N type field oxide device NFOD pipe of a plurality of parallel connections; The drain electrode connection pads Pad of each NFOD pipe, source ground, substrate ground connection; With the grouping of described NFOD pipe, every group comprises at least one NFOD pipe; Surround with the P-well contact around every group of NFOD pipe.
Preferably, every group comprises two NFOD pipes.
Preferably, every group comprises four NFOD pipes.
Preferably, every group comprises that six NFOD pipe or every group comprise eight NFOD pipes.
Preferably, described every group of NFOD pipe around and a circle n-well is set between the P-well of the outer ring contact.
Compared with prior art, the present invention has the following advantages:
Esd protection circuit provided by the invention; esd protection circuit comprises referring to NMOS pipe esd protection circuit more and refer to NFOD pipe esd protection circuit more; no matter be the esd protection circuit of what type pipe; all pipe is divided into groups; and a circle P-well contact is set around every group; the base resistance that can make every group of parasitic NPN that is positioned at intermediate tube like this differs less with the base resistance of the parasitic NPN of the pipe that is positioned at both sides; like this because the uniformity of base resistance is better; therefore when esd pulse is added in the last generation of PAD leakage current inflow base resistance; can make the base-emitter positively biased of all NPN; the even conducting of all NPN, the ESD electric current of releasing.
Description of drawings
Fig. 1 is a kind of esd protection circuit of the prior art;
Fig. 2 is the sectional view of the esd protection circuit that composes in parallel of a plurality of GGNMOS;
Fig. 3 is the I-V curve chart of esd protection circuit in the prior art;
Fig. 4 is the domain of Fig. 2 correspondence in the prior art;
Fig. 5 is the present invention is managed the esd protection circuit of forming by many finger NMOS a domain;
Fig. 6 is the sectional view of one group of pipe correspondence among Fig. 5;
Fig. 7 is the present invention is managed the esd protection circuit of forming by many finger NMOS an another embodiment domain;
Fig. 8 is the sectional view of Fig. 7 correspondence;
Fig. 9 is the circuit diagram of the esd protection circuit that NFOD forms in the prior art;
Figure 10 is the domain that refers to the esd protection circuit that NFOD forms in the prior art more;
Figure 11 is the domain that the present invention refers to the esd protection circuit that NFOD forms more;
Figure 12 is the sectional view of one group of pipe correspondence among Figure 11;
Figure 13 is managed the sectional view of the another kind of embodiment correspondence of the ESD that forms by NFOD;
Figure 14 is the domain of Figure 13 correspondence.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Referring to Fig. 4, this figure is the domain of Fig. 2 correspondence in the prior art.
As can be seen from Figure 4, the circle of one around the domain is the B among Fig. 2.
Be that a plurality of NMOS pipes are in parallel in the middle of the domain.
Referring to Fig. 5, this figure is the present invention is managed the esd protection circuit of forming by many finger NMOS a domain.
Comparison diagram 5 and Fig. 4 can find out significantly, and with many finger NMOS pipes grouping of parallel connection, every group comprises at least one NMOS pipe during with respect to the difference of prior art in the present invention; Surround with the P-well contact around every group of NMOS pipe.
Need to prove that comprise several NMOS pipes in every group, the embodiment of the invention does not specifically limit, generally in order to save the manufacturing area, operated by rotary motion even number NMOS pipe in every group.For example every group can comprise two, four, six or eight or the like.Certainly for the base resistance that makes parasitic NPN differs less, can every group of NMOS pipe that less number is set.For example, when including only 2 NMOS pipes for every group, because the base stage of the parasitic NPN of two pipes is identical to the distance of B, therefore the resistance of two base resistances is also identical, two NPN conductings simultaneously, and conducting homogeneity is fine like this, the ESD electric current of can effectively releasing.
Present embodiment is that esd protection resistance is divided into four groups, is respectively first group 11, the second groups 12, the three groups 13 and the 4th groups 14, and every group comprises the four NMOS pipe.
In order more to be expressly understood the present invention, elaborate below in conjunction with the circuit diagram of one group of correspondence among Fig. 5.
Referring to Fig. 6, this figure is the sectional view of one group of pipe correspondence among Fig. 5.
It is that example is introduced that this embodiment is provided with the four NMOS pipe with every group.Only the drawn sectional view of one group of pipe of Fig. 6.
As can be seen from Figure 6, the base resistance of the parasitic NPN of two NMOS pipes is the resistance of R1+R2 in the middle of this group.The resistance of the base resistance of the NPN of both sides is R1.Therefore the base stage resistance of NPN and both sides NPN differs R2 in the middle of.Unlike prior art, the base resistance of the middle NPN base resistance and the NPN of both sides differs greatly.
Therefore when esd pulse is added in the last generation of PAD leakage current inflow base resistance, can make the base-emitter positively biased of all NPN, the even conducting of all NPN, the ESD electric current of releasing.
Referring to Fig. 7, this figure is the present invention is managed the esd protection circuit of forming by many finger NMOS an another embodiment domain.
The esd protection circuit that present embodiment provides is adding a circle n-well111 around every group of pipe on the basis of embodiment shown in Figure 5 and between the P-well of the outer ring contact.
For those skilled in the art understand technical scheme of the present invention better, below in conjunction with the sectional view detailed description of Fig. 7 correspondence.
Referring to Fig. 8, this figure is the sectional view of Fig. 7 correspondence.
As can be seen from Figure 8, the base stage of each NPN all can not directly be passed through P-well to the resistance of substrate contact, and a circle n-well who is added has blocked, and must be through one section P-sub substrate, because the resistance value ratio P-well's of unit of P-sub substrate is big, so so just increased the base resistance of all NPN, therefore when NPN has leakage current to flow through, because base resistance has increased, base voltage also increases like this, therefore, the easier conducting of NPN is discharged, so conducting homogeneity is better.
Above embodiment is the solution that proposes at the esd protection circuit of being made up of the NMOS pipe; can solve the esd protection circuit of forming by the NFOD pipe with same solution; NFOD is managed packet layout, and around every group, the P-well of outer ring contact inside is provided with a circle n-well.Introduce in detail below in conjunction with accompanying drawing.
Referring to Fig. 9, this figure is the circuit diagram of the esd protection circuit that NFOD forms in the prior art.
The drain electrode connection pads Pad of NFOD pipe, substrate ground connection, source ground.
Referring to Figure 10, this figure is the domain that refers to the esd protection circuit that NFOD forms in the prior art more.
Referring to Figure 11, this figure is the domain that the present invention refers to the esd protection circuit that NFOD forms more.
In conjunction with Figure 10 and Figure 11, can find out significantly, the esd protection circuit that many finger NFOD that the embodiment of the invention provides form, with the NFOD grouping, every group comprises a NFOD pipe at least, surrounds with the P-well contact around every group of NMOS pipe.
Need to prove that comprise several NMOS pipes in every group, the embodiment of the invention does not specifically limit, generally in order to save the manufacturing area, operated by rotary motion even number NMOS pipe in every group.For example every group can comprise two, four, six or eight or the like.Certainly for the base resistance that makes parasitic NPN differs less, can every group of NMOS pipe that less number is set.For example, when including only 2 NMOS pipes for every group, because the base stage of the parasitic NPN of two pipes is identical to the distance of B, therefore the resistance of two base resistances is also identical, two NPN conductings simultaneously, and conducting homogeneity is fine like this, the ESD electric current of can effectively releasing.
Present embodiment is that esd protection circuit is divided into four groups of as shown in figure 10 first group 21, the second groups 22, the three groups 23 and the 4th groups 24.Every group comprises four NFOD pipes.
In order more to be expressly understood the present invention, elaborate below in conjunction with the sectional view of one group of correspondence among Figure 12.
Referring to Figure 12, this figure is the sectional view of one group of pipe correspondence among Figure 11.
It is that example is introduced that this embodiment is provided with the four NMOS pipe with every group.Only the drawn sectional view of one group of pipe of Fig. 6.
The esd protection circuit of forming with the NMOS pipe is identical; the resistance of the base resistance of the base resistance of the parasitic NPN of middle NFOD pipe and the parasitic NPN pipe of both sides differs less; therefore when esd pulse is added in the last generation of PAD leakage current inflow base resistance; can make the base-emitter positively biased of all NPN; the even conducting of all NPN, the ESD electric current of releasing.
Referring to Figure 13, this figure is the sectional view of being managed the another kind of embodiment correspondence of the ESD that forms by NFOD.
Present embodiment is provided with a circle n-well around every group of pipe; the esd protection circuit of forming with NMOS pipe shown in Figure 7 is identical; owing to increased n-well; the base stage of each NPN all can not directly be passed through P-well to the resistance of substrate contact; a circle n-well who is added has blocked; and must be through one section P-sub substrate; because the unit organization of P-sub substrate is bigger than P-well's; so so just increased the base resistance of all NPN, therefore when NPN has leakage current to flow through, because base resistance has increased; base voltage also increases like this; therefore, the easier conducting of NPN is discharged, so conducting homogeneity is better.
Referring to Figure 14, this figure is the domain of Figure 13 correspondence.
As can be seen from Figure 14, around every group of pipe a circle n-well222 is set.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (10)
1. an ESD protection circuit comprises: the NMOS pipe of a plurality of grounded-grid parallel connections; The drain electrode connection pads Pad of each NMOS pipe, grounded-grid, source ground, substrate ground connection; It is characterized in that with the grouping of described NMOS pipe, every group comprises at least one NMOS pipe; Surround with the P-well contact around every group of NMOS pipe.
2. ESD protection circuit according to claim 1 is characterized in that, every group comprises two NMOS pipes.
3. ESD protection circuit according to claim 1 is characterized in that, every group comprises the four NMOS pipe.
4. ESD protection circuit according to claim 1 is characterized in that, every group comprises that six NMOS pipe or every group comprise eight NMOS pipes.
5. according to each described ESD protection circuit of claim 1 to 4, it is characterized in that, a circle n-well is set around described every group of NMOS pipe and between the P-well of the outer ring contact.
6. an ESD protection circuit comprises: the N type field oxide device NFOD pipe of a plurality of parallel connections; The drain electrode connection pads Pad of each NFOD pipe, source ground, substrate ground connection; It is characterized in that with the grouping of described NFOD pipe, every group comprises at least one NFOD pipe; Surround with the P-well contact around every group of NFOD pipe.
7. ESD protection circuit according to claim 6 is characterized in that, every group comprises two NFOD pipes.
8. ESD protection circuit according to claim 6 is characterized in that, every group comprises four NFOD pipes.
9. ESD protection circuit according to claim 6 is characterized in that, every group comprises that six NFOD pipe or every group comprise eight NFOD pipes.
10. according to each described ESD protection circuit of claim 6 to 9, it is characterized in that, a circle n-well is set around described every group of NFOD pipe and between the P-well of the outer ring contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910195957 CN102024811A (en) | 2009-09-17 | 2009-09-17 | Electrostatic discharge protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910195957 CN102024811A (en) | 2009-09-17 | 2009-09-17 | Electrostatic discharge protection circuit |
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| CN102024811A true CN102024811A (en) | 2011-04-20 |
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| CN 200910195957 Pending CN102024811A (en) | 2009-09-17 | 2009-09-17 | Electrostatic discharge protection circuit |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790050A (en) * | 2011-12-12 | 2012-11-21 | 钜泉光电科技(上海)股份有限公司 | Chip with static protecting function |
| CN104143549A (en) * | 2013-05-10 | 2014-11-12 | 炬力集成电路设计有限公司 | Electrostatic discharge protective circuit layout and integrated circuit |
| CN104269440A (en) * | 2014-09-30 | 2015-01-07 | 武汉新芯集成电路制造有限公司 | Stack N-type transistor and electrostatic protection circuit |
| CN108879634A (en) * | 2018-06-30 | 2018-11-23 | 唯捷创芯(天津)电子技术股份有限公司 | Chip, the communication terminal of a kind of device of surge protector and its composition |
| CN109449156A (en) * | 2018-12-20 | 2019-03-08 | 上海艾为电子技术股份有限公司 | A kind of port static release protection circuit |
| CN110060997A (en) * | 2019-04-15 | 2019-07-26 | 长江存储科技有限责任公司 | A kind of ESD-protection structure and preparation method thereof |
| CN112133698A (en) * | 2020-11-30 | 2020-12-25 | 珠海市杰理科技股份有限公司 | ESD protection device |
| US20240030215A1 (en) * | 2022-07-25 | 2024-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strap technology to improve esd hbm performance |
-
2009
- 2009-09-17 CN CN 200910195957 patent/CN102024811A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790050A (en) * | 2011-12-12 | 2012-11-21 | 钜泉光电科技(上海)股份有限公司 | Chip with static protecting function |
| CN102790050B (en) * | 2011-12-12 | 2016-01-20 | 钜泉光电科技(上海)股份有限公司 | Possesses the chip of antistatic protection function |
| CN104143549A (en) * | 2013-05-10 | 2014-11-12 | 炬力集成电路设计有限公司 | Electrostatic discharge protective circuit layout and integrated circuit |
| CN104143549B (en) * | 2013-05-10 | 2017-07-18 | 熠芯(珠海)微电子研究院有限公司 | A kind of static release protection circuit domain and integrated circuit |
| CN104269440A (en) * | 2014-09-30 | 2015-01-07 | 武汉新芯集成电路制造有限公司 | Stack N-type transistor and electrostatic protection circuit |
| CN104269440B (en) * | 2014-09-30 | 2017-10-17 | 武汉新芯集成电路制造有限公司 | Stacking-type N-type transistor and electrostatic discharge protective circuit |
| CN108879634A (en) * | 2018-06-30 | 2018-11-23 | 唯捷创芯(天津)电子技术股份有限公司 | Chip, the communication terminal of a kind of device of surge protector and its composition |
| CN108879634B (en) * | 2018-06-30 | 2022-03-04 | 唯捷创芯(天津)电子技术股份有限公司 | Surge protection device and chip and communication terminal formed by same |
| CN109449156A (en) * | 2018-12-20 | 2019-03-08 | 上海艾为电子技术股份有限公司 | A kind of port static release protection circuit |
| CN109449156B (en) * | 2018-12-20 | 2024-03-22 | 上海艾为电子技术股份有限公司 | Port electrostatic discharge protection circuit |
| CN110060997A (en) * | 2019-04-15 | 2019-07-26 | 长江存储科技有限责任公司 | A kind of ESD-protection structure and preparation method thereof |
| CN110060997B (en) * | 2019-04-15 | 2020-04-17 | 长江存储科技有限责任公司 | Electrostatic discharge protection structure and manufacturing method thereof |
| CN112133698A (en) * | 2020-11-30 | 2020-12-25 | 珠海市杰理科技股份有限公司 | ESD protection device |
| US20240030215A1 (en) * | 2022-07-25 | 2024-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strap technology to improve esd hbm performance |
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Open date: 20110420 |