CN102024701A - P-channel metal oxide semiconductor transistor source-drain injection method - Google Patents
P-channel metal oxide semiconductor transistor source-drain injection method Download PDFInfo
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- CN102024701A CN102024701A CN2009101954088A CN200910195408A CN102024701A CN 102024701 A CN102024701 A CN 102024701A CN 2009101954088 A CN2009101954088 A CN 2009101954088A CN 200910195408 A CN200910195408 A CN 200910195408A CN 102024701 A CN102024701 A CN 102024701A
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- pmos
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Abstract
The invention discloses a p-channel metal oxide semiconductor transistor (PMOS) source-drain injection method, which comprises: performing low-concentration B ion injection in PMOS source and drain regions on a semiconductor substrate on two sides of the side wall of a PMOS grid structure; performing F ion injection in the PMOS source and drain regions on the semiconductor substrate on two sides of the side wall of the PMOS grid structure; performing high-concentration BF2 ion injection in the PMOS source and drain regions on the semiconductor substrate on two sides of the side wall of the PMOS grid structure; and performing high-concentration B ion injection in the PMOS source and drain regions on the semiconductor substrate on two sides of the side wall of the PMOS grid structure. The method weakens the short channel effect of the PMOS.
Description
Technical field
The present invention relates to the semiconductor fabrication techniques field, be specifically related to P-channel metal-oxide-semiconductor transistor (PMOS) source and leak method for implanting.
Background technology
In existing complementary metal oxide semiconductors (CMOS) (CMOS) integrated circuit technique, inject from, ion and form N trap and P trap finishing shallow trench isolation, and finish after the making of gate oxide and polysilicon gate construction, need carry out the manufacturing of source-drain area.
The manufacture process of existing PMOS source-drain area mainly may further comprise the steps:
Step 101: utilize the silicon nitride of dry etch process etching silicon chip surface, form the side wall of the grid structure of PMOS.
In etching process, the silicon dioxide and the silicon nitride that need to keep all around gate structure, so that form side wall, side wall can be used for preventing that the follow-up source of carrying out from leaking that ion too leaks break-through near raceway groove so that generation source when injecting, promptly thereby diffusion reduction threshold voltage takes place in the impurity that injects, and increases leakage current.
Step 102: on the Semiconductor substrate of the side wall both sides of PMOS grid structure, carry out the photoetching of PMOS source-drain area.
Utilize photoetching to determine to carry out the PMOS source and drain areas that ion injects earlier; Then, carry out p according to the zone of determining
+The source is leaked and is injected, and the side wall that forms in the step 101 can be used in the ion that stops injection and too spreads to raceway groove one side.
Step 103: low concentration boron (B) ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects.
Step 104: the high concentration BF that on the Semiconductor substrate of the side wall both sides of PMOS grid structure, carries out the PMOS source-drain area
2Ion injects.
Step 105: the high concentration B ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects.
The concentration sum of the ions that step 104,105 is injected is about 100 times of the ion concentration injected of step 103.
Step 106: silicon chip is placed in the short annealing device anneals.
By above-mentioned flow process as can be seen, carrying out source-drain area when injecting, second and the ion concentration injected of the third level be far longer than the ion concentration that the first order is injected.The ion of this high concentration injects and causes the PN junction between source-drain area and the well region to advance to well region one thruster, and especially when drain electrode added work voltage, depletion region can advance to well region one thruster, causes short-channel effect to become serious, makes that the electric leakage rheology is big.
In addition, for transistor, improving constantly performance is the requirement of integrated circuit development.In order to obtain high-performance, ultra-thin gate oxide is used.But ultra-thin gate oxide can worsen negative pressure temperature instability (NBTI, Negative Bias Temperature Instability) effect, and concrete reason is as follows:
The NBTI effect is because the positive charge trap attract electrons in the gate oxide causes.PMOS has a large amount of electronics and passes gate oxide by tunnel effect when work, and these electronics are caught and stayed in the gate oxide by the positive charge trap, causes the PMOS threshold voltage to raise, and operating current reduces.These positive charge traps in the gate oxide may be movable positive charge for example: foreign metal ion, fixed positive charge (some defectives by gate oxide inside cause) or interfacial state are as dangling bonds.Gate oxide is thin more, and big more by the tunnelling current of gate oxide during transistor work, the electronics that just passes through is many more, and the electronics in the gate oxide that is captured like this is also just many more, and the NBTI effect is serious more.
Dangling bonds in the gate oxide are often occupied by the H ion, because Si ion and H ion in the gate oxide all are cation, the covalent chemical bond that forms between them a little less than, as electronics through out-of-date, this chemical bond key is interrupted and is captured electronics probably, worsen NBTI, cause the NBTI lifetime.The NBTI life-span is a key index weighing the PMOS reliability, and the quality of NBTI life-span and gate oxide is closely related, and the NBTI life-span is high more, shows that the quality of gate oxide is high more.At present, one of standard of IC industry circle is that life-span of the NBTI of PMOS must not be less than 5 years.
Summary of the invention
The invention provides the PMOS source and leak method for implanting, to weaken the short-channel effect of PMOS.
Technical scheme of the present invention is achieved in that
Method for implanting is leaked in a kind of P-channel metal-oxide-semiconductor transistor PMOS source, and this method comprises:
The low concentration boron ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects;
The fluorine F ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects;
On the Semiconductor substrate of the side wall both sides of PMOS grid structure, carry out the high concentration boron fluoride BF of PMOS source-drain area
2Ion injects;
The high concentration boron ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects.
After injecting, the high concentration boron ion that carries out the PMOS source-drain area on the Semiconductor substrate of described side wall both sides at the PMOS grid structure further comprises:
Silicon chip is placed in the short annealing device anneals.
The energy range that described F ion injects is: 5～10 kiloelectron-volts of Kev.
The dosage range that described F ion injects is: 5E14～3E15 number of ions/centimetre
2Cm
-2
The angle that described F ion injects is 0～30 degree.
Compared with prior art, the present invention carries out the injection of low concentration B ion and the high concentration BF of PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure
2Between ion injects, carry out the F ion and inject, the F ion is infused in and makes PMOS source and drain areas surface form amorphous layer to a certain extent, has suppressed follow-up high concentration BF
2Channeling effect when injecting with the B ion has been controlled the degree of depth that the source-drain area ion injects, and has weakened high concentration BF2 and B ion to the diffusion of well region one side, so weakened the short-channel effect of PMOS.
In addition, the F ion diffuses to gate oxide after short annealing, has substituted the H-Si key in the gate oxide, form comparatively stable F-Si key, thereby reduced the probability of gate oxide seizure electronics, suppressed the NBTI effect of PMOS, thereby improved the NBTI life-span of PMOS.
Description of drawings
Fig. 1 is an existing P MOS source-drain area manufacture method flow chart;
Fig. 2 leaks the method for implanting flow chart for the PMOS source that the embodiment of the invention provides.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
Fig. 2 leaks the method for implanting flow chart for the PMOS source that the embodiment of the invention provides, and as shown in Figure 2, its concrete steps are as follows:
Step 201: utilize the silicon nitride of dry etch process etching silicon chip surface, form the side wall of the grid structure of PMOS.
Step 202: on the Semiconductor substrate of the side wall both sides of PMOS grid structure, carry out the photoetching of PMOS source-drain area.
Step 203: the first order low concentration ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects.
The ion that injects in this step is the B ion.
Step 204: the F ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects.
Implant angle scope 0～30 degree of F ion is generally chosen 0 degree; The injection energy range of F ion can be: 5～10 kiloelectron-volts (Kev); The implantation dosage scope of F ion can be: 5E14～3E15 number of ions/centimetre
2(cm
-2).
Step 205: the second level high concentration BF that on the Semiconductor substrate of the side wall both sides of PMOS grid structure, carries out the PMOS source-drain area
2Ion injects.
Step 206: the third level high concentration B ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects.
Step 207: silicon chip is placed in the short annealing device anneals.
In the embodiment of the invention, before injecting, injects second and third grade high concentration ion the F ion, because the decrystallized characteristic of F ion, like this, the F ion can form non-product layer at PMOS source-drain area silicon face, and the channeling effect when having avoided second and third grade ion to inject makes the high concentration ion of second and third grade injection concentrate on more shallow zone, thereby reduced the degree of depth that PN junction advances to well region one thruster, thereby weakened short-channel effect.
It is one of important parameter of weighing the short-channel effect power that drain-induced barrier reduces (DIBL, Drain Induction Barrier Lower) value.DIBL=Vthi-Vtsat, wherein Vthi adds small voltage in drain electrode, the threshold voltage when making transistor be in linear zone work, Vtsat adds work voltage promptly in drain electrode: high voltage, the threshold voltage when making transistor be in saturation condition work.The DIBL value is big more, and short-channel effect is strong more; The DIBL value is more little, and short-channel effect is weak more, promptly controls well more to the short effect of linking up.
In addition, in the embodiment of the invention, inject the F ion at source-drain area, like this, the F ion diffuses to gate oxide after short annealing, because the Si ion is a cation, and F is an anion, therefore the F-Si key is more stable, when PMOS worked, when grid added work voltage, electronics by gate oxide, electronics was reduced by the probability that the F-Si key captures, therefore, the NBTI life-span is improved.
When table 1 has provided employing the inventive method and existing method, the comparison of DIBL:
The comparison table of DIBL when table 1 adopts the inventive method and existing method
As can be seen from Table 1: adopt the inventive method, can reduce DIBL, promptly can weaken short-channel effect.
When table 2 has provided employing the inventive method and existing method, the comparison in NBTI life-span:
The comparison table in NBTI life-span when table 2 adopts the inventive method and existing method
As can be seen from Table 2: adopt the inventive method, can with the NBTI life-span from bringing up to greater than 5 years less than 1 year, reached the NBTI life standard of IC industry circle.
The above only is process of the present invention and method embodiment, in order to restriction the present invention, all any modifications of being made within the spirit and principles in the present invention, is not equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. method for implanting is leaked in a P-channel metal-oxide-semiconductor transistor PMOS source, and this method comprises:
The low concentration boron ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects;
The fluorine F ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects;
On the Semiconductor substrate of the side wall both sides of PMOS grid structure, carry out the high concentration boron fluoride BF of PMOS source-drain area
2Ion injects;
The high concentration boron ion that carries out the PMOS source-drain area on the Semiconductor substrate of the side wall both sides of PMOS grid structure injects.
2. the method for claim 1 is characterized in that, further comprises after the high concentration boron ion that carries out the PMOS source-drain area on the Semiconductor substrate of described side wall both sides at the PMOS grid structure injects:
Silicon chip is placed in the short annealing device anneals.
3. method as claimed in claim 1 or 2 is characterized in that, the energy range that described F ion injects is: 5～10 kiloelectron-volts of Kev.
4. method as claimed in claim 1 or 2 is characterized in that, the dosage range that described F ion injects is: 5E14～3E15 number of ions/centimetre
2Cm
-2
5. method as claimed in claim 1 or 2 is characterized in that, the angle that described F ion injects is 0～30 degree.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009101954088A CN102024701B (en) | 2009-09-09 | 2009-09-09 | P-channel metal oxide semiconductor transistor source-drain injection method |
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| CN2009101954088A CN102024701B (en) | 2009-09-09 | 2009-09-09 | P-channel metal oxide semiconductor transistor source-drain injection method |
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| CN102024701A true CN102024701A (en) | 2011-04-20 |
| CN102024701B CN102024701B (en) | 2012-02-08 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103111A (en) * | 2018-09-27 | 2018-12-28 | 武汉新芯集成电路制造有限公司 | A kind of forming method of PMOS structure |
| CN110176402A (en) * | 2019-06-21 | 2019-08-27 | 上海华力集成电路制造有限公司 | A kind of shallow Doped ions method for implanting of FDSOI PMOS |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1056471C (en) * | 1996-02-15 | 2000-09-13 | 台湾茂矽电子股份有限公司 | Method for making complementary MOS field-effect transistor |
| US6320204B1 (en) * | 1997-12-25 | 2001-11-20 | Seiko Epson Corporation | Electro-optical device in which an extending portion of a channel region of a semiconductor layer is connected to a capacitor line and an electronic apparatus including the electro-optical device |
| CN1167113C (en) * | 2001-07-17 | 2004-09-15 | 旺宏电子股份有限公司 | Process for preparing MOS device with ultra-shallow junction extending area |
| US7018880B2 (en) * | 2003-12-22 | 2006-03-28 | Texas Instruments Incorporated | Method for manufacturing a MOS transistor having reduced 1/f noise |
| US20070037326A1 (en) * | 2005-08-09 | 2007-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Shallow source/drain regions for CMOS transistors |
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2009
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103111A (en) * | 2018-09-27 | 2018-12-28 | 武汉新芯集成电路制造有限公司 | A kind of forming method of PMOS structure |
| CN109103111B (en) * | 2018-09-27 | 2022-05-31 | 武汉新芯集成电路制造有限公司 | Forming method of PMOS structure |
| CN110176402A (en) * | 2019-06-21 | 2019-08-27 | 上海华力集成电路制造有限公司 | A kind of shallow Doped ions method for implanting of FDSOI PMOS |
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| CN102024701B (en) | 2012-02-08 |
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