CN117766468A - Method for forming semiconductor structure - Google Patents
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- CN117766468A CN117766468A CN202410077877.4A CN202410077877A CN117766468A CN 117766468 A CN117766468 A CN 117766468A CN 202410077877 A CN202410077877 A CN 202410077877A CN 117766468 A CN117766468 A CN 117766468A
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 150000002500 ions Chemical class 0.000 claims abstract description 221
- 239000000758 substrate Substances 0.000 claims abstract description 101
- 238000000137 annealing Methods 0.000 claims abstract description 13
- -1 boron ions Chemical class 0.000 claims description 32
- 229910052796 boron Inorganic materials 0.000 claims description 12
- 229910052785 arsenic Inorganic materials 0.000 claims description 10
- 229910001449 indium ion Inorganic materials 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 239000011574 phosphorus Substances 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 abstract description 31
- 230000000694 effects Effects 0.000 abstract description 17
- 238000005468 ion implantation Methods 0.000 abstract description 10
- 230000009286 beneficial effect Effects 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 18
- 238000002347 injection Methods 0.000 description 14
- 239000007924 injection Substances 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate; forming a gate structure on a substrate; forming a threshold voltage adjustment region within the substrate, the threshold voltage adjustment region having threshold voltage adjustment ions; and forming a lightly doped drain region in the substrate, wherein the lightly doped drain region is provided with lightly doped ions. The threshold voltage adjusting ion implantation is performed after the grid so that the threshold voltage adjusting ion has deeper implantation depth outside the channel region. The lightly doped ions are implanted after the threshold voltage adjusting ions are implanted, and the threshold voltage adjusting ions have deeper implantation depth outside the channel region, so that the implanted lightly doped ions are beneficial to forming deeper and more layered junction depths in the source-drain region, and the hot carrier implantation effect is improved. In the process, the damage to the structural performance of the device is effectively reduced without increasing the implantation energy and annealing heat of lightly doped ions. Meanwhile, non-self-aligned mask ion implantation is not needed, so that the process is effectively simplified.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
In integrated circuits, input/output (I/O) devices are an important component. The input/output device has characteristics of high operating voltage and high driving capability compared to the core device. However, under a high operating voltage environment, a strong lateral electric field is stored in the channel of the input/output device, so that a hot carrier injection (Hot Carrier Injection, HCI) effect is easily generated.
In advanced CMOS processes, the hot carrier injection effect of the input/output devices is increasingly challenging, for the following reasons: the working voltage of the input/output device is usually 2.5V, the hot carrier injection effect caused by 2.5V is serious, and the working voltage of the device can reach 3.3V, so that a higher requirement is put on the reliability of the hot carrier injection effect; if the core device and the input/output device share a well region, the input/output device has heavier well region doping, which is unfavorable for forming a layered lightly doped drain region (Light Doped Drain, LDD), and is unfavorable for improving the hot carrier injection effect; in advanced CMOS analog applications and embedded processes, the input/output device typically operates at 5V, with a hot carrier injection effect that is stronger than that of a 2.5V device; with the advancement of process nodes, the thickness of the polysilicon gate of the CMOS device is greatly reduced, and the implantation depth of source and drain ions of the device is greatly limited, so that the improvement of hot carrier implantation effect is more unfavorable.
However, the prior art still has problems in improving the hot carrier injection effect.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure, which can improve the hot carrier injection effect, simplify the process steps and reduce the damage to the structural performance of a device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a gate structure on the substrate; implanting threshold voltage adjusting ions into the substrate after forming the gate structure, the threshold voltage adjusting ions penetrating the gate structure to form a threshold voltage adjusting region within the substrate; after the threshold voltage adjusting region is formed, lightly doped ions are implanted into the substrate by taking the gate structure as a mask, and lightly doped drain regions are formed in the substrate, wherein the electrical types of the lightly doped ions and the threshold voltage adjusting ions are opposite; forming a side wall on the side wall of the grid structure; and injecting source and drain ions into the substrate by taking the grid structure and the side wall as masks, and forming a source and drain doped region in the substrate, wherein the electrical types of the source and drain ions are the same as those of the lightly doped ions.
Optionally, before forming the gate structure, the method further includes: and forming a well region in the substrate, wherein well region ions are arranged in the well region, and the well region ions have the same electrical type as the threshold voltage adjusting ions.
Optionally, the forming method of the well region includes: and implanting the well region ions into the substrate, and forming the well region in the substrate.
Optionally, after forming the gate structure and before forming the lightly doped drain region, the method further includes: and forming a well region in the substrate, wherein well region ions are arranged in the well region, and the well region ions have the same electrical type as the threshold voltage adjusting ions.
Optionally, the forming method of the well region includes: and implanting the well region ions into the substrate, wherein the well region ions penetrate through the gate structure, and the well region is formed in the substrate.
Optionally, the threshold voltage adjusting region, the lightly doped drain region and the source-drain doped region are located in the well region.
Optionally, the threshold voltage adjusting ion includes: p-type ions or N-type ions; the P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions.
Optionally, the gate structure includes: the gate electrode comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer.
Optionally, the method for forming the side wall includes: forming initial side walls on the side walls and the top surface of the grid structure and the surface of the substrate; and etching the initial side wall until the top surface of the grid electrode structure and the surface of the substrate are exposed, so as to form the side wall.
Optionally, the forming method of the lightly doped drain region includes: implanting lightly doped ions into the substrate by taking the gate structure as a mask, and forming an initial lightly doped drain region in the substrate; and performing first annealing treatment on the initial lightly doped drain region to form the lightly doped drain region.
Optionally, the method for forming the source-drain doped region includes: injecting source and drain ions into the substrate by taking the grid structure and the side wall as masks, and forming an initial source and drain doping region in the substrate; and performing second annealing treatment on the initial source-drain doped region to form the source-drain doped region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor structure, the threshold voltage adjusting ions are implanted after the gate structure is formed, so that the implantation energy required by the threshold voltage adjusting ions is larger to ensure that the threshold voltage adjusting ions penetrate through the gate structure to enter the channel region, and further the threshold voltage is adjusted. And outside the channel region, the threshold voltage adjusting ion implantation depth is deeper because the gate structure is not shielded. The lightly doped ions are implanted after the threshold voltage adjusting ions are implanted, and the threshold voltage adjusting ions have deeper implantation depth outside the channel region, so that the implanted lightly doped ions are beneficial to forming deeper and more layered junction depths in the source and drain regions, and the hot carrier implantation effect is improved. In the process, the implantation energy and annealing heat of the lightly doped ions do not need to be increased, and the damage to the structural performance of the device is effectively reduced. Meanwhile, non-self-aligned mask ion implantation is not needed, so that the process is effectively simplified, and the process efficiency is improved.
Further, after forming the gate structure and before forming the lightly doped drain region, the method further comprises: and forming a well region in the substrate, wherein well region ions are arranged in the well region, and the well region ions have the same electrical type as the threshold voltage adjusting ions. Because the well region ions need to penetrate the gate structure, the energy of the well region ions implanted after the gate structure is formed is higher than the energy of the well region ions implanted before the gate structure is formed. Because the well region ions are implanted in a non-mask manner, the well region ions finally implanted into the channel region have shallower implantation depth due to the shielding of the gate structure. And outside the channel region, the implantation depth of the ions in the well region is deeper because the gate structure is not shielded, which is favorable for forming deeper and more layered junction depths of lightly doped ions implanted outside the channel region and further improves the hot carrier implantation effect.
Drawings
FIGS. 1-3 are schematic views of steps of a method for forming a semiconductor structure;
fig. 4 to 10 are schematic views illustrating the structure of each step of the method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 11 to 17 are schematic views illustrating the structure of each step of a method for forming a semiconductor structure according to another embodiment of the present invention.
Detailed Description
As described in the background, the prior art still has problems in improving the hot carrier injection effect. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1 to 3 are schematic views illustrating the structure of each step of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided; implanting well region ions into the substrate 100, and forming a well region 101 in the substrate 100; threshold voltage adjusting ions are implanted into the substrate 100, and a threshold voltage adjusting region 102 is formed in the well region 101, wherein the electrical type of the well region ions and the threshold voltage adjusting ions are the same.
Referring to fig. 2, a gate structure 103 is formed on the substrate 100; lightly doped ions are implanted into the substrate 100 by using the gate structure 103 as a mask, and lightly doped drain regions 104 are formed in the well region 101, wherein the lightly doped ions have an opposite electrical type to the well region ions.
Referring to fig. 3, a sidewall 105 is formed on a sidewall of the gate structure 103; and implanting source and drain ions into the substrate 100 by taking the gate structure 103 and the side wall 105 as masks, and forming source and drain doped regions 106 in the well region 101, wherein the electrical types of the source and drain ions are the same as those of the lightly doped ions.
At present, conventional technological means for improving the hot carrier injection effect have certain problems, and the technical means specifically comprise: increasing the implantation energy of the lightly doped ions, but penetrating the thinner gate structure; increasing the anneal after the lightly doped ion implantation, but changing the channel doping profile of the core device; the implantation of the lightly doped ions, which is not self-aligned, is employed prior to forming the gate structure, but can produce large device performance fluctuations that are particularly unsuitable for analog circuit applications.
On the basis, the invention provides a method for forming a semiconductor structure, which is characterized in that the threshold voltage adjusting ions are implanted after the grid structure is formed, so that the implantation energy required by the threshold voltage adjusting ions is larger to ensure that the threshold voltage adjusting ions penetrate through the grid structure to enter a channel region, and further the adjustment of the threshold voltage is completed. The lightly doped ions are injected after the threshold voltage adjusting ions are injected, and the injection energy of the threshold voltage adjusting ions is larger, so that the lightly doped ions have deeper injection depth in the source drain region, and the lightly doped drain region junction depth with higher layering is formed, so that the hot carrier injection effect is improved. In the process, the implantation energy and annealing heat of the lightly doped ions do not need to be increased, and the damage to the structural performance of the device is effectively reduced. Meanwhile, non-self-aligned mask ion implantation is not needed, so that the process is effectively simplified, and the process efficiency is improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 10 are schematic views illustrating the structure of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided.
The materials of the substrate 200 include: monocrystalline silicon, polycrystalline silicon or amorphous silicon; the material of the substrate 200 may further include: semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, and the like.
In this embodiment, the material of the substrate 200 is monocrystalline silicon.
Referring to fig. 5, well ions are implanted into the substrate 200, and a well 201 is formed in the substrate 200.
In this embodiment, the device structure formed is an NMOS device, so that the corresponding well ions use P-type ions; in other embodiments, if the device structure is a PMOS device, the corresponding well ions are N-type ions.
The P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions.
Referring to fig. 6, a gate structure 202 is formed on the substrate 200.
The gate structure 202 includes: a gate dielectric layer, and a gate layer (not labeled) on the gate dielectric layer.
The method for forming the gate structure 202 includes: forming a gate dielectric material layer (not shown) on the substrate 200; forming a gate material layer (not shown) over the gate dielectric material layer; and carrying out patterning treatment on the gate dielectric layer material layer and the gate material layer to form the gate dielectric layer and a gate layer positioned on the gate dielectric layer, wherein the gate dielectric layer and the gate layer form the gate structure 202.
The gate dielectric layer comprises the following materials: silicon oxide, hafnium oxide and hafnium silicon oxide. In this embodiment, the gate dielectric layer is made of silicon oxide.
And the gate electrode layer is made of polysilicon.
Referring to fig. 7, after forming a dormitory gate structure 202, threshold voltage adjusting ions are implanted into the substrate 200, the threshold voltage adjusting ions penetrate the gate structure 202, and a threshold voltage adjusting region 203 is formed within the substrate 200.
The electrical type of the threshold voltage adjusting ions is the same as that of the well region ions.
In this embodiment, the formed device structure is an NMOS device, so the electrical type of the threshold voltage adjusting ion corresponding to the NMOS device is P-type; in other embodiments, if the device structure is a PMOS device, the electrical type of the threshold voltage adjusting ion is N-type.
The P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions. In this embodiment, the threshold voltage adjusting ion is boron ion.
The threshold voltage adjustment region 203 is located within the well region 201.
Since the threshold voltage adjusting ions need to penetrate the gate structure 202, the energy of the threshold voltage adjusting ions injected after the gate structure 202 is formed is higher than the energy of the threshold voltage adjusting ions injected before the gate structure 202 is formed, and the magnitude of the energy of the threshold voltage adjusting ions injected penetrating the gate structure 202 is determined by the thickness of the gate dielectric layer and the gate layer.
Since the threshold voltage adjusting ions are implanted in a maskless manner, the implantation depth of the threshold voltage adjusting ions in the channel region (i.e., the region of the substrate 200 covered by the gate structure 202) is shallower due to the shielding of the gate structure 202. Outside the channel region, the gate structure 202 is not shielded, so that the implantation depth of the threshold voltage adjusting ions is deeper, which is beneficial for the formation of deeper and more layered junction depths of the lightly doped ions implanted outside the channel region.
Referring to fig. 8, after the threshold voltage adjusting region 203 is formed, lightly doped ions are implanted into the substrate 200 by using the gate structure 202 as a mask, and lightly doped drain regions 204 are formed in the substrate 200, wherein the lightly doped ions have an opposite electrical type to the threshold voltage adjusting ions.
By implanting the threshold adjustment ions after forming the gate structure 202, the threshold adjustment ions require a greater implantation energy to ensure penetration of the gate structure 202 into a channel region (i.e., the region of the substrate 200 covered by the gate structure 202), thereby completing the adjustment of threshold voltage. And outside the channel region, the threshold voltage adjusting ion implantation depth is deeper because there is no shielding of the gate structure 202. The lightly doped ions are implanted after the threshold voltage adjusting ions are implanted, and the threshold voltage adjusting ions have deeper implantation depth outside the channel region, so that the implanted lightly doped ions are beneficial to forming deeper and more layered junction depths in the source-drain region (region outside the channel region), and the hot carrier implantation effect is improved. In the process, the implantation energy and annealing heat of the lightly doped ions do not need to be increased, and the damage to the structural performance of the device is effectively reduced. Meanwhile, non-self-aligned mask ion implantation is not needed, so that the process is effectively simplified, and the process efficiency is improved.
The method for forming the lightly doped drain 204 includes: implanting lightly doped ions into the substrate 200 by using the gate structure 202 as a mask, and forming an initial lightly doped drain region in the substrate 200; and performing a first annealing treatment on the initial lightly doped drain region to form the lightly doped drain region 204.
Note that, the lightly doped ions are implanted into the substrate 200 using the gate structure 202 as a mask, i.e., the lightly doped ions do not penetrate the gate structure 202.
The lightly doped ions are of opposite electrical type to the well region ions.
In this embodiment, the device structure formed is an NMOS device, so the corresponding lightly doped ion is an N-type ion; in other embodiments, if the device structure is a PMOS device, the corresponding lightly doped ion is a P-type ion.
The P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions.
The lightly doped drain region 204 is located within the well region 201.
Referring to fig. 9, a sidewall 205 is formed on a sidewall of the gate structure 202.
The method for forming the side wall 205 includes: forming initial sidewalls (not shown) on the sidewalls and top surface of the gate structure 202 and the surface of the substrate 200; and etching the initial side wall until the top surface of the gate structure 202 and the surface of the substrate 200 are exposed, thereby forming the side wall 205.
The materials of the side wall 205 include: one or more of silicon oxide and silicon nitride.
Referring to fig. 10, source and drain ions are implanted into the substrate 200 by using the gate structure 202 and the sidewall 205 as masks, and source and drain doped regions 206 are formed in the substrate 200, wherein the electrical types of the source and drain ions are the same as those of the lightly doped ions.
The method for forming the source-drain doped region 206 includes: implanting source and drain ions into the substrate 200 by using the gate structure 202 and the side wall 205 as masks, and forming initial source and drain doped regions in the substrate 200; and performing a second annealing treatment on the initial source-drain doped region to form the source-drain doped region 206.
Note that, source and drain ions are implanted into the substrate 200 using the gate structure 202 and the sidewall 205 as masks, that is, the source and drain ions do not penetrate through the gate structure 202 and the sidewall 205.
The source-drain ions are of opposite electrical type to the lightly doped ions.
In this embodiment, the device structure formed is an NMOS device, so the corresponding source-drain ions are N-type ions; in other embodiments, if the device structure is a PMOS device, the corresponding source-drain ions are P-type ions.
The P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions.
The source-drain doped region 206 is located in the well region 201.
Fig. 11 to 17 are schematic views illustrating the structure of each step of a method for forming a semiconductor structure according to another embodiment of the present invention.
The embodiment of the invention also provides a method for forming a semiconductor structure, which is different from the above embodiment in that: the well region is formed after forming the gate structure and before forming the lightly doped drain region. The specific process is shown in fig. 11 to 17.
Referring to fig. 11, a substrate 300 is provided.
The materials of the substrate 300 include: monocrystalline silicon, polycrystalline silicon or amorphous silicon; the material of the substrate 300 may further include: semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, and the like.
In this embodiment, the material of the substrate 300 is monocrystalline silicon.
Referring to fig. 12, a gate structure 302 is formed on the substrate 300.
The gate structure 302 includes: a gate dielectric layer, and a gate layer (not labeled) on the gate dielectric layer.
The method for forming the gate structure 302 includes: forming a gate dielectric material layer (not shown) on the substrate 300; forming a gate material layer (not shown) over the gate dielectric material layer; and carrying out patterning treatment on the gate dielectric layer material layer and the gate material layer to form the gate dielectric layer and a gate layer positioned on the gate dielectric layer, and forming the gate structure 302 by the gate dielectric layer and the gate layer.
The gate dielectric layer comprises the following materials: silicon oxide, hafnium oxide and hafnium silicon oxide. In this embodiment, the gate dielectric layer is made of silicon oxide.
And the gate electrode layer is made of polysilicon.
Referring to fig. 13, after the gate structure 302 is formed, well ions are implanted into the substrate 300, and a well 301 is formed in the substrate 300.
In this embodiment, the device structure formed is an NMOS device, so that the corresponding well ions use P-type ions; in other embodiments, if the device structure is a PMOS device, the corresponding well ions are N-type ions.
The P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions.
Note that, since the well ions need to penetrate the gate structure 302, the energy of the well ions injected after the gate structure 302 is formed is higher than the energy of the well ions injected before the gate structure 302 is formed, and the amount of the well ions injected penetrating the gate structure 302 is determined by the thicknesses of the gate dielectric layer and the gate layer.
Because the well region ions are implanted in a non-masking manner, the well region ions finally implanted into the channel region (i.e., the region of the substrate 300 covered by the gate structure 302) have a shallower implantation depth due to the shielding of the gate structure 302. Outside the channel region, the implantation depth of the well region ions is deeper because the gate structure 302 is not blocked, which is beneficial for the formation of deeper and more layered junction depths of the lightly doped ions implanted outside the channel region.
Referring to fig. 14, after the gate structure 302 is formed, threshold voltage adjusting ions are implanted into the substrate 300, the threshold voltage adjusting ions penetrate through the gate structure 302, and a threshold voltage adjusting region 303 is formed in the substrate 300.
The electrical type of the threshold voltage adjusting ions is the same as that of the well region ions.
In this embodiment, the formed device structure is an NMOS device, so the electrical type of the threshold voltage adjusting ion corresponding to the NMOS device is P-type; in other embodiments, if the device structure is a PMOS device, the electrical type of the threshold voltage adjusting ion is N-type.
The P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions. In this embodiment, the threshold voltage adjusting ion is boron ion.
The threshold voltage adjustment region 303 is located within the well region 301.
Since the threshold voltage adjusting ions need to penetrate the gate structure 302, the energy of the threshold voltage adjusting ions injected after the gate structure 302 is formed is higher than the energy of the threshold voltage adjusting ions injected before the gate structure 302 is formed, and the magnitude of the energy of the threshold voltage adjusting ions injected penetrating the gate structure 302 is determined by the thickness of the gate dielectric layer and the gate layer.
Since the threshold voltage adjusting ions are implanted in a non-masked manner, the threshold voltage adjusting ions finally implanted in the channel region (i.e., the region of the substrate 300 covered by the gate structure 302) have a shallower implantation depth due to the shielding of the gate structure 302. Outside the channel region, the gate structure 302 is not shielded, so that the implantation depth of the threshold voltage adjusting ions is deeper, which is beneficial to forming deeper and more layered junction depths of the lightly doped ions implanted outside the channel region.
Referring to fig. 15, after the threshold voltage adjusting region 303 is formed, lightly doped ions are implanted into the substrate 300 by using the gate structure 302 as a mask, and lightly doped drain regions 304 are formed in the substrate 300, wherein the lightly doped ions have an opposite electrical type to the threshold voltage adjusting ions.
By implanting the threshold adjustment ions after the gate structure 302 is formed, the threshold adjustment ions require a greater implantation energy to ensure penetration of the gate structure 302 into a channel region (i.e., the region of the substrate 300 covered by the gate structure 302) and thus complete adjustment of the threshold voltage. And outside the channel region, the threshold voltage adjusting ion implantation depth is deeper because there is no shielding of the gate structure 302. The lightly doped ions are implanted after the threshold voltage adjusting ions are implanted, and the threshold voltage adjusting ions have deeper implantation depth outside the channel region, so that the implanted lightly doped ions are beneficial to forming deeper and more layered junction depths in the source-drain region (region outside the channel region), and the hot carrier implantation effect is improved. In the process, the implantation energy and annealing heat of the lightly doped ions do not need to be increased, and the damage to the structural performance of the device is effectively reduced. Meanwhile, non-self-aligned mask ion implantation is not needed, so that the process is effectively simplified, and the process efficiency is improved.
The method for forming the lightly doped drain region 304 includes: implanting lightly doped ions into the substrate 300 by using the gate structure 302 as a mask, and forming an initial lightly doped drain region in the substrate 300; and performing a first annealing treatment on the initial lightly doped drain region to form the lightly doped drain region 304.
It should be noted that, the lightly doped ions are implanted into the substrate 300 by using the gate structure 302 as a mask, i.e., the lightly doped ions do not penetrate the gate structure 302.
The lightly doped ions are of opposite electrical type to the well region ions.
In this embodiment, the device structure formed is an NMOS device, so the corresponding lightly doped ion is an N-type ion; in other embodiments, if the device structure is a PMOS device, the corresponding lightly doped ion is a P-type ion.
The P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions.
The lightly doped drain region 304 is located within the well region 301.
Referring to fig. 16, a sidewall 305 is formed on a sidewall of the gate structure 302.
The method for forming the side wall 305 includes: forming initial sidewalls (not shown) on the sidewalls and top surface of the gate structure 302 and the surface of the substrate 300; and etching the initial side wall until the top surface of the gate structure 302 and the surface of the substrate 300 are exposed, thereby forming the side wall 305.
The materials of the side wall 305 include: one or more of silicon oxide and silicon nitride.
Referring to fig. 17, source and drain ions are implanted into the substrate 300 by using the gate structure 302 and the sidewall 305 as masks, and source and drain doped regions 306 are formed in the substrate 300, wherein the electrical types of the source and drain ions are the same as those of the lightly doped ions.
The method for forming the source-drain doped region 306 includes: implanting source and drain ions into the substrate 300 by using the gate structure 302 and the side wall 305 as masks, and forming initial source and drain doped regions in the substrate 300; and performing a second annealing treatment on the initial source-drain doped region to form the source-drain doped region 306.
Note that, source and drain ions are implanted into the substrate 300 with the gate structure 302 and the sidewall 305 as masks, that is, the source and drain ions do not penetrate through the gate structure 302 and the sidewall 305.
The source-drain ions are of opposite electrical type to the lightly doped ions.
In this embodiment, the device structure formed is an NMOS device, so the corresponding source-drain ions are N-type ions; in other embodiments, if the device structure is a PMOS device, the corresponding source-drain ions are P-type ions.
The P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions.
The source-drain doped region 306 is located in the well region 301.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (11)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a gate structure on the substrate;
implanting threshold voltage adjusting ions into the substrate after forming the gate structure, the threshold voltage adjusting ions penetrating the gate structure to form a threshold voltage adjusting region within the substrate;
after the threshold voltage adjusting region is formed, lightly doped ions are implanted into the substrate by taking the gate structure as a mask, and lightly doped drain regions are formed in the substrate, wherein the electrical types of the lightly doped ions and the threshold voltage adjusting ions are opposite;
forming a side wall on the side wall of the grid structure;
and injecting source and drain ions into the substrate by taking the grid structure and the side wall as masks, and forming a source and drain doped region in the substrate, wherein the electrical types of the source and drain ions are the same as those of the lightly doped ions.
2. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the gate structure: and forming a well region in the substrate, wherein well region ions are arranged in the well region, and the well region ions have the same electrical type as the threshold voltage adjusting ions.
3. The method of forming a semiconductor structure of claim 2, wherein the method of forming a well region comprises: and implanting the well region ions into the substrate, and forming the well region in the substrate.
4. The method of forming a semiconductor structure of claim 1, further comprising, after forming the gate structure and before forming the lightly doped drain region: and forming a well region in the substrate, wherein well region ions are arranged in the well region, and the well region ions have the same electrical type as the threshold voltage adjusting ions.
5. The method of forming a semiconductor structure of claim 4, wherein the method of forming a well region comprises: and implanting the well region ions into the substrate, wherein the well region ions penetrate through the gate structure, and the well region is formed in the substrate.
6. The method of forming a semiconductor structure of claim 2 or 4, wherein the threshold voltage adjustment region, the lightly doped drain region, and the source drain doped region are located within the well region.
7. The method of forming a semiconductor structure of claim 1, wherein the threshold voltage adjusting ions comprise: p-type ions or N-type ions; the P-type ions include: boron ions, BF2 - Ions or indium ions; the N-type ions include: phosphorus ions or arsenic ions.
8. The method of forming a semiconductor structure of claim 1, wherein the gate structure comprises: the gate electrode comprises a gate dielectric layer and a gate electrode layer positioned on the gate dielectric layer.
9. The method for forming a semiconductor structure according to claim 1, wherein the method for forming a sidewall comprises: forming initial side walls on the side walls and the top surface of the grid structure and the surface of the substrate; and etching the initial side wall until the top surface of the grid electrode structure and the surface of the substrate are exposed, so as to form the side wall.
10. The method of forming a semiconductor structure of claim 1, wherein said method of forming a lightly doped drain comprises: implanting lightly doped ions into the substrate by taking the gate structure as a mask, and forming an initial lightly doped drain region in the substrate; and performing first annealing treatment on the initial lightly doped drain region to form the lightly doped drain region.
11. The method of forming a semiconductor structure of claim 1, wherein the method of forming source drain doped regions comprises: injecting source and drain ions into the substrate by taking the grid structure and the side wall as masks, and forming an initial source and drain doping region in the substrate; and performing second annealing treatment on the initial source-drain doped region to form the source-drain doped region.
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