CN101996979A - 中介层、包括该中介层的模块及电子装置 - Google Patents

中介层、包括该中介层的模块及电子装置 Download PDF

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Publication number
CN101996979A
CN101996979A CN201010241077XA CN201010241077A CN101996979A CN 101996979 A CN101996979 A CN 101996979A CN 201010241077X A CN201010241077X A CN 201010241077XA CN 201010241077 A CN201010241077 A CN 201010241077A CN 101996979 A CN101996979 A CN 101996979A
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substrate
intermediary layer
wiring
semiconductor chip
layer
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CN201010241077XA
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CN101996979B (zh
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秋叶朗
御手洗俊
池田浩一
盛田伸也
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Sony Corp
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Sony Corp
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Priority claimed from JP2009184674A external-priority patent/JP2011040882A/ja
Priority claimed from JP2010130266A external-priority patent/JP5641202B2/ja
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Abstract

本发明公开了中介层、包括该中介层的模块及电子装置。所述中介层包括：基板，它具有正面和背面；布线，它形成在所述基板的正面侧上并且与半导体芯片电连接；电气元件，它与所述布线连接；以及凹部，它在对应于所述电气元件的位置处从所述基板的背面侧形成。所述模块包括上述中介层和安装在该中介层上的半导体芯片。所述电子装置包括上述中介层、安装在该中介层上的半导体芯片以及用于安装该中介层的安装基板。利用本发明实施例的中介层，能够简化制造步骤，并且该中介层表现出较好的高频特性。对于本发明实施例的包括上述中介层的模块及电子装置，能够提高可靠性和产率。

Description

中介层、包括该中介层的模块及电子装置
相关申请的交叉参考
本申请包含与2009年8月7日和2010年6月7日向日本专利局提交的日本优先权专利申请JP2009-184674和JP2010-130266所公开的内容相关的主题，在此将这两个日本优先权专利申请的全部内容以引用的方式并入本文中。
技术领域
本发明涉及一种用于对各自布线规则互不相同的多个电子装置中的电连接及机械连接起到中继作用的中介层，还涉及包括该中介层的模块及电子装置。
背景技术
在微细化方面已急速改进的半导体芯片的焊盘间距与用于安装该半导体芯片的基板(安装基板)的焊盘间距之间存在着个位数(single-digit)以上的间隙。这种间隙导致难以将由于半导体技术的进步而得到的高性能以及高功能芯片的性能反映到器件或系统上。例如，实际使用的半导体芯片的焊盘间距已经改进到50μm以下，而安装基板(例如，印刷电路板(Print Circuit Board，PCB))的焊盘间距为大约500μm。将来，可以预期半导体芯片的焊盘间距的微细化还会根据定标规则(scaling rule)来得以改进。而在此期间，PCB的焊盘间距的微细化会相对缓慢地改进。
过去，作为用于补偿上述焊盘间距间隙并将半导体芯片与安装基板电连接且机械连接的手段，已经使用了由金(Au)或铝(Al)制成的导线。具体地，半导体芯片被贴晶接合(die-bond)(机械连接)到具有500μm级布线规则的有机基板上，并且该有机基板的布线焊盘和该半导体芯片的布线焊盘是通过导线连接(电连接)的。
在信号线中，随着载波频率的提高，长度的影响也变大。对于数字电路的载波，使用了具有400MHz级时钟频率的信号。同时，对于收发电路的载波，使用了高频带(从GHz至毫米频带)。高频率具有短波长。例如，60GHz的半波长在真空下为2.5mm，而在PCB上为1.2mm。在特定信号线的物理长度等于或者大于载波频率的电长度的一半的情况下，在该信号线中会显示出有问题的信号谐振现象。因此，为了保证信号质量，期望制造出这样一种布局：该布局中，信号线的长度小于所传送的载波信号的电长度的一半。于是，近年来，开始采用比通过导线而实现的安装模式更小的封装。硅中介层引起了关注，利用该硅中介层，可预期通过很短布线来减少电力损耗并提高信号质量，而且已经积极地取得了硅中介层的技术发展(例如，日本专利公开公报特开2008-42904号)。
在日本专利公开公报特开2008-42904号中，硅中介层由用于变换布线间距的布线(包括硅贯通孔(Through Silicon Via，TSV))以及用于后述天线元件的腔部(凹部)构成。该硅中介层具有如下结构：在中介层基板上集成有设于另外一硅基板(上侧硅部分)内的天线图形。这样，与作为高频模拟电路的半导体芯片相距的连接距离有所减小，并且能够提高信号质量。
然而，在上述举例说明的中介层中，存在的一个缺点是它的制造步骤(例如，设有天线图形的硅基板的接合步骤、以及对天线部分和半导体芯片部分的图形化加工步骤等)变得复杂，因而降低了可靠性和产率。
发明内容
鉴于上述缺点，在本发明中，期望提供一种能够简化制造步骤的中介层，并提供包括该中介层的模块及电子装置。
本发明实施例提供了一种中介层，其包括：基板，它具有正面和背面；布线，它形成在所述基板的正面侧上并与半导体芯片电连接；电气元件，它与所述布线连接；以及凹部，它在对应于所述电气元件的位置处从所述基板的背面侧形成。
在本例中，“凹部”除了可以是在该凹部的底部处留有基板的形状之外，也可以是通过完全除去该凹部底部处的基板而得到的贯穿形状。
此外，“凹部，它在对应于所述电气元件的位置处从所述基板的背面侧形成”指的是该凹部位于如下位置的状态：设置在所述基板上的所述电气元件的至少一部分处于该位置的上方。
本发明另一实施例提供了一种模块，其包括上述本发明实施例的中介层以及安装在所述中介层上的半导体芯片。
本发明又一实施例提供了一种电子装置，其包括上述本发明实施例的中介层、安装在所述中介层上的半导体芯片以及用于安装所述中介层的安装基板。
在本发明实施例的中介层、包括该中介层的模块及电子装置中，由于在基板上预先设有布线和电气元件，因此，不需要基板与布线之间的接合步骤，也不需要诸如天线等电气元件和半导体芯片等的图形化步骤等。于是，简化了制造步骤。
在本发明实施例的中介层、包括该中介层的模块及电子装置中，由于在基板上设有布线和电气元件，于是，简化了制造步骤。因此，能够提高可靠性和产率。
根据下面的说明，将会更全面地显示出本发明的其他及进一步的目的、特征和优点。
附图说明
图1是本发明实施例的模块的截面图。
图2是图1所示的模块的平面图。
图3是图示了另一示例的模块的截面图。
图4A和图4B是图1所示模块的无线电发射的特性图。
图5A～图5C是按步骤顺序图示了图1所示模块的制造方法的图。
图6A～图6C是图示了在图5A～图5C之后的步骤的图。
图7是比较例的模块的截面图。
图8A～图8C是按步骤顺序图示了图7所示模块的制造方法的图。
图9A～图9C是图示了在图8A～图8C之后的步骤的图。
图10A～图10B是图示了在图9A～图9C之后的步骤的图。
图11是本发明变形例的模块的截面图。
图12图示了图11所示的模块的平面图。
图13是图示了另一示例的模块的截面图。
图14是作为模块的应用例的电子装置的功能框图。
具体实施方式
下面参照附图来说明本发明的实施例，进行说明的顺序如下：
(1)整体结构
(2)制造方法
(1)整体结构
图1图示了本发明实施例的包括中介层10A和半导体芯片20的模块1A的截面结构。图2图示了该模块1A的平面结构。图1是沿图2中的线I-I得到的截面结构。在中介层10A中，介电层14形成在包括凹部19A的基板11上。在介电层14中设有布线层16和电气元件17(在本例中是天线)。在介电层14上方，设有与布线层16相连的半导体芯片20。中介层10A以如下方式把半导体芯片20连接到安装基板30(在本例中是印制板)上：该中介层10A与安装基板30二者之间隔着设在基板11中的贯通电极12。
作为基板11，例如优选使用厚度在50～400μm范围内的硅(Si)基板或碳化硅(SiC)基板，以便与稍后说明的半导体芯片20的材料相匹配。通过与半导体芯片20的材料相匹配，各热膨胀系数就变成大体上相同，从而提高了半导体芯片20与中介层10A之间接合的可靠性。基板11的材料不限于上述材料，而是也可以使用其他半导体材料或介电材料。其他半导体材料的例子包括：SiGe和GaAs。介电材料的例子包括：陶瓷、玻璃(例如，耐热玻璃(Pyrex)、SD2、石英等)、树脂(玻璃环氧树脂、BT树脂等)、以及有机聚合物。
基板11在与设在介电层14中的天线17的至少一部分对应的位置处设有凹部19A，该凹部19A具有在基板11背面侧的凹陷。考虑到信号损失的抑制效果的关系，优选将凹部19A形成在与后述的天线17相对的位置处，即，在如图2所示的俯视图中，优选将凹部19A形成得覆盖整个天线17。在本实施例中，在凹部19A的底部处留有基板11。然而，基板11不是必须留在凹部19A的底部处，如图3所示也可以采用通过完全除去基板11而形成的贯通开口19B。此外，可以不完全除去基板11，而是留着基板11的一部分。具体地，能够以栅栏状或以格子图形来形成凹部19A。此外，凹部19A(开口19B)的平面图形例如是环形或矩形。然而，凹部19A(开口19B)的平面图形不限于此，而是根据与布置在该凹部19A(开口19B)上方的电气元件的形状和尺寸的关系来确定。
此外，基板11包括具有例如50μm直径的贯通电极12。贯通电极12由例如铜(Cu)形成。在贯通电极12的上方和下方分别设有焊盘13A和13B。
在基板11与介电层14之间设有绝缘层11A。在绝缘层11A中，在具有例如0.01～4μm厚度的氧化硅膜(SiO2)上形成有具有例如0.01～0.3μm厚度的例如氮化硅膜(SiN)。如稍后所述，当在基板11中设置凹部19A(开口19B)时，绝缘层11A用作蚀刻停止层。然而，对于用来获得具有凹部19A(开口19B)的所谓膜片构件(例如本实施例的中介层10A)的性能的结构而言，绝缘层11A是可有可无的。
介电层14由对于高频信号而言具有很小损耗的低介电常数材料(例如，苯环丁烯(BCB))形成。介电层14的厚度由电气特性和机械强度这二者来确定，并且例如是在1μm～20μm范围内。然而，介电层14的最佳膜厚度是根据布线布局规则而变化的。例如，根据电气特性的需要，按照布线阻抗匹配的观点来确定该膜厚度范围。具体地，例如，当在60GHz的布线、线宽/间距为50μm/50μm的高频布线以及微带线的条件下实现50Ω匹配时，需要20μm的膜厚度。此外，考虑到与加速进行了窄间距化和多管脚化的互补型金属氧化物半导体(Complementary Metal OxideSemiconductor，CMOS)的焊盘相对应的线宽/间距，在如下情况下得到了50Ω匹配：当线宽/间距为30μm/30μm时，厚度为12μm的情况；当线宽/间距为15μm/15μm时，厚度为6μm的情况；以及当线宽/间距为5μm/5μm时，厚度为3μm的情况。因此，优选通过BCB膜(它可以是几微米以下的薄膜～几十微米的厚膜)形成技术以及多层膜技术来制造介电层14。此外，作为介电层14，能够使用通常用作介电材料的那些材料之外的其他材料，只要这种材料对于高频信号而言具有很小损耗并且具有即使在如上所述有凹部19A(开口19B)设在基板11中的情况下也能够保持桥结构的强度即可。具体地，除了可以使用诸如SiO2等无机材料之外，还可以使用类金刚石碳(diamond-like carbon，DLC)。
在介电层14中，设有布线层16和天线17。布线层16由一层以上的多层布线层(在本例中为一层：布线16A和布线16B)与层间连接布线层(贯通接触部15A)的组合构成。布线层16由导电材料(例如，Al(铝)、AlCu(铝铜)等金属材料)制成。在本例中，天线17是由Al布线制成的仿真八木天线。不用说，这种元件不限于此，而是也可使用诸如贴片天线(patch antenna)或缝隙天线(slot antenna)等无源器件。此外，也可以使用Al之外的其他金属材料。为了保证信号质量，优选把天线17和后述的半导体芯片20布置成彼此接近。通过减小天线17与半导体芯片20之间的距离，能够减小收发电路的累积损失。例如，在通过导线将半导体芯片20和天线17连接起来的情况下，例如长度约为1.5mm且直径为20μm的金(Au)导线具有0.8nH寄生电感，且在60GHz处会产生约1dB的信号损失。然而，在按照本实施例来布置天线17和半导体芯片20的情况下，天线17和半导体芯片20之间的距离变为200μm，并且信号损失大幅度降低到0.1dB。此外，如上所述通过把天线17形成在凹部19A(开口19B)上方，减小了由基板引起的信号损失，并且得到了更高的天线增益。如图1、图3、图5A、图5B和图5C所示，通过在介电层14A中形成通孔14a并用金属材料填充该通孔14a，来获得层间连接布线层。然而，层间连接布线层的形式不限于此，可以采用任何形状，只要让不同层中的布线相互连接起来即可。
图4A图示了中心频率为60GHz的仿真八木天线的反射特性(S11)的特性图。图4B图示了远场的无线电发射特性的计算结果(三维图示)。在该发射特性的主瓣中，膜片天线(membrane antenna)的天线增益计算结果为-5dBi，不是膜片天线的参考天线的计算结果为-10dBi。因此，在本实施例中通过将凹部19A(开口19B)设在与天线17相对的位置处，能够得到较高的天线增益。
半导体芯片20是RFIC(射频集成电路)。在本例中，半导体芯片20是这样的器件：它把从例如基带芯片输入的几百MHz频带的信号上变频(up-convert)成例如作为毫米频带信号的高频频带信号。半导体芯片20以如下方式与布线16A及16B连接：半导体芯片20与布线16A及16B二者之间隔着焊盘21A及21B和焊料层22A及22B。布线16A隔着贯通接触部15A和焊盘13A与贯通电极12连接。同时，布线16B与天线17连接。
印制板30是这样的安装基板：它上面除了安装有模块1A(1B)之外还安装有诸如电阻器和电容器等许多电子部件，并且通过用布线把这些电子部件相互连接起来而构成了电子电路。
例如，通过图5A～图5C及图6A～图6C所示的方法能够制造出模块1A(1B)。
(2)制造方法
首先，如图5A所示，在基板11中形成通孔11B之后，形成绝缘层11A。具体地，在具有例如400μm厚度的基板11的正面上图形化地形成蚀刻掩模。接着，在真空条件下利用深反应离子蚀刻(Deep Reactive IonEtching，DRIE)装置沿厚度方向对基板11进行蚀刻，从而形成通孔11B。随后，在例如1000℃下加热基板11，从而通过在水蒸汽环境下进行的热氧化来形成具有3μm厚度的SiO2膜。接着，在基板11正面的SiO2膜上，例如通过化学气相沉积(Chemical Vapor Deposition，CVD)方法形成具有0.1～0.3μm厚度的SiN膜，由此得到绝缘膜11A。
随后，如图5B所示形成贯通电极12。具体地，例如，在通孔11B的表面上，例如通过物理气相沉积(Physical Vapor Deposition，PVD)方法形成具有例如50nm厚度的底层钛(Ti)和具有例如300nm厚度的铜(Cu)薄膜，以此作为晶种层(未图示)。接着，在通过电解铜镀敷工艺将Cu填充到通孔11B之后，通过化学机械研磨(Chemical Mechanical Polishing，CMP)法对基板11进行研磨，从而形成贯通电极12。随后，通过例如光刻以及例如DRIE等干式蚀刻来形成例如100μm直径和100nm厚度的AlCu薄膜，以此作为焊盘13A、焊盘13B和焊盘13C。
接着如图5C所示，形成介电层14A、贯通接触部15A、布线16A、布线16B和天线17。具体地，首先，在基板11的顶面上，利用作为低介电常数材料的BCB通过旋转涂敷法形成介电层14A。在介电层14A中形成到达焊盘13A的通孔14a。此后，用AlCu填充通孔14a从而形成贯通接触部15A。接着，在介电层14A上，通过光刻和干式蚀刻形成布线16A、布线16B及天线17。接着，利用同样的方法，在基板11的底面上形成介电层14B、贯通接触部15B、贯通接触部15C、焊盘16C以及焊盘16D。
随后，如图6A所示，在基板11的顶面上形成介电层14C之后，形成用于将半导体芯片20与布线16A和布线16B相连接的开口18A和开口18B。具体地，利用例如BCB通过旋转涂敷法在基板11的顶面上形成介电层14C之后，通过光刻及干式蚀刻除去用于安装半导体芯片20的区域中的介电层14C。接着，例如在基板11的底面上形成硬掩模。此后，通过例如DRIE对基板11进行蚀刻来形成凹部19A(开口19B)，由此完成了具有所需膜片结构的中介层10A。作为蚀刻条件，使用了采用SF6/C4H8进行的垂直加工(本领域中所知晓的Bosch工艺过程)或者采用XeF2进行的干式处理工艺。此外，可以使用采用四甲基氢氧化铵(TMAH)或氢氧化钾(KOH)的湿式处理工艺。此时，由于设在基板11与介电层14之间的绝缘层11A用作蚀刻停止层，因而蚀刻在绝缘层11A中停止。在绝缘层11A的厚度很小的情况下，可能会发生过蚀刻(overetching)。
接着，如图6B所示，在中介层10A的顶面上安装半导体芯片20。具体地，在例如150℃和100kPa下将设置在半导体芯片20底面上的焊盘21A和21B热压接合到中介层10A的顶面上。于是，完成了半导体芯片20与中介层10A之间的接合。
最后，如图6C所示，隔着凸块32A和32B将中介层10A的焊盘16C和16D与形成在印制板30上的焊盘31A和31B连接在一起，因而把设有半导体芯片20的中介层10A安装到印制板30上。这样，完成了模块1A。
在本实施例的中介层10A(10B)中，在基板11上形成有介电层14，并且布线层16和天线17被包含在介电层14中。此外，在基板11上设置有贯通电极12。中介层10A将印制板30与设在中介层10A上的半导体芯片20隔着贯通电极12连接在一起。如上所述，通过使用中介层10A，能够以电及机械的方式对各自布线间距互不相同的半导体芯片20和印制板30起到中继作用。
此外，在基板11的对应于天线17的位置处，设有从基板11的背面侧形成的凹部19A(开口19B)。因此，抑制了基板11与天线17之间的寄生电容和涡电流(eddy current)。
如上所述，半导体芯片20和印制板30是基于半导体芯片20侧的连接部中的窄布线间距并基于印制板30侧的连接部中的宽布线间距而连接起来的。构成上述连接部的焊盘以及用于连接这些焊盘的布线是：设置在中介层10A的基板11上的介电层14中的布线层16；贯通电极12；以及基板11背面侧上的布线层16(焊盘13B和16C以及贯通接触部15B)。它们的线宽和间距是通过使用半导体芯片的加工方式而形成的。因此，与一般的安装基板相比，能够通过个位数以上的精细加工技术或者基于与半导体芯片的布线加工规则等同的规则来进行加工。图1(图3)中的中介层10A(10B)的基板11背面侧的右侧布线层16(焊盘13C和16D以及贯通接触部15C)是在印制板30上进行安装的过程中用于实现机械平衡的假连接层、或者是基板11的GND(接地)连接层。
图7图示了比较例的现有模块100的截面结构。在该模块的中介层100A中，第二Si基板211通过接合金属与具有凹部119的第一Si基板(中介层)111接合，该第二Si基板211具有位于底面上的布线216A和天线217并具有半导体芯片(集成电路芯片)220。凹部119被设计成容纳着半导体芯片220。
为了实际得到这种模块100，可以使用图8A～图8C、图9A～图9C以及图10A～图10B所示的制造步骤。下面简述这些制造步骤中的各个步骤。首先，如图8A所示，对第一Si基板111进行加工，从而形成通孔111B。此后，形成绝缘膜(未图示)。接着，如图8B所示，在形成贯通电极112A和112B之后，形成焊盘113A、113B、113C和113D。随后，如图8C所示，形成凹部119，由此形成了要作为中介层的第一Si基板111。接着，如图9A所示，在第二Si基板211上形成包括布线216A、布线216B及天线217的介电层214。此后，如图9B所示，通过CMP法将第二Si基板211加工成薄膜。随后，如图9C所示，在第二Si基板211中设置凹部219，以便得到膜片结构。之后，将半导体芯片220连接过来，由此形成了设有半导体芯片220的第二Si基板211。接着，如图10A所示，通过热压接合使第一Si基板111与第二Si基板211接合起来。然后，最终如图10B所示，通过使用焊料将所得到的半成品安装到印制板130上，从而完成了模块100。
在上面得到的模块100及其制造方法中存在以下缺点。首先，由于使用了两个Si基板，这自然就增大了模块尺寸。因此，为了对这种增大的尺寸进行弥补，必须有用于获得薄膜的步骤(图9B)。此外，除了在第一Si基板111中形成凹部119之外，为了来自天线217的无线电发射，还需要在第二Si基板211的与天线217相对的位置处设置凹部219。此时，由于如上所述已将第二Si基板211加工成薄膜，因而存在着第二Si基板211容易破裂的可能性。另外，在将第二Si基板211安装到第一Si基板111上的过程中，第一Si基板111的贯通电极112A和112B与设在第二Si基板211底面上的布线层216接合。由于该接合步骤的对准精度很低，从而导致了对微细化的制约。另外，在传送频率很高的情况下，会呈现出由于布线不匹配等所致的信号损失。此外，必须有用于将第一Si基板111与第二Si基板211接合起来的布线步骤。如上所述，制造步骤变得复杂。
然而，在本实施例的中介层10A(10B)中，由于布线层16被设置在直接形成于基板11上的介电层14中，因而无需前述的那几个步骤。因此，能够简化制造步骤。
如上所述，在本实施例的中介层10A(10B)及包含该中介层10A(10B)的模块1A(1B)中，由于在基板11上形成有介电层14，并且布线层16和天线17被设在介电层14中，因此，通过将基板11和布线层16一体化，简化了制造步骤，并能够提高产率。
此外，由于省去了会引起对准精度的降低的接合步骤，因而提高了模块1A(1B)的特性。此外，由于减少了制造步骤，从而能够降低成本。
另外，由于半导体芯片20与印制板30是隔着贯通电极12连接起来的，因而能够减小布线面积。也就是说，能够减小模块1A(1B)的尺寸。此外，通过使用贯通电极12，能够在模块1A(1B)上层叠其他的模块。
此外，在本实施例的中介层10A(10B)及包含该中介层10A(10B)的模块1A(1B)中，在基板11背面侧的与天线17的至少一部分对应的位置处设有凹部19A(或贯穿基板11的开口19B)。这样，抑制了该基板与该元件之间的寄生电容和涡电流。因此，能够抑制信号损失。
变形例
下面根据上述实施例的中介层10A(10B)及包含该中介层10A(10B)的模块1A(1B)的变形例，说明中介层10C(10D)及包含该中介层10C(10D)的模块2A(2B)。图11图示了包括中介层10C的模块2A的截面结构，该中介层10C具有在基板11中的凹部19A，图12图示了模块2A的平面结构。图13图示了包括中介层10D的模块2B的截面结构，该中介层10D具有在基板11中的开口19B。图11和图13是沿图12中的线II-II得到的截面结构。与第一实施例中相同的构件被赋予相同的附图标记，并省略对它们的说明。
中介层10C(10D)通过导线33将布线层16与印制板30连接起来。在基板11上，除了设有其中形成有上述实施例中所说明的布线层16和电气元件17的介电层14之外，还设有用于与印制板30实现导线连接的导线焊盘以及用于除去布线噪声的去耦电容器(MIM电容器)(未图示)，同时还设置有芯片用连接部23。
在该变形例的中介层10C(10D)及包含该中介层10C(10D)的模块2A(2B)中，由于通过导线33将布线层16与印制板30连接起来，因此，除了具有上述实施例的效果之外，还具有这样的效果：能够将模块2A(2B)自由地布置在印制板30上。此外，在管脚数量少且元件占用面积的差异比球栅阵列封装(Ball Grid Array，BGA)等中的差异小的情况下，与制造贯通电极12相比，采用由导线33实现的布线则更便宜。因此，还存在能够降低成本的效果。
应用例
下面，参照图14来说明使用了本发明实施例的中介层10A的通信装置的结构。图14图示了作为电子装置的通信装置的结构框图。
图14所示的通信装置的示例包括：移动电话、个人数字助理(personaldigital assistant，PDA)和无线LAN(局域网)装置。例如，如图14所示，该通信装置包括发送电路300A(模块)、接收电路300B(模块)、用于切换发送/接收路径的发送/接收切换器301、高频滤波器302和发送/接收天线303。
发送电路300A包括：分别与I通道的发送数据和Q通道的发送数据对应的两个数字模拟转换器(digital/analog converter，DAC)311I和311Q以及两个带通滤波器312I和312Q；调制器320；发送用锁相环(Phase-Locked Loop，PLL)电路313；和功率放大器314。调制器320包括：分别与上述两个带通滤波器312I和312Q对应的两个缓冲放大器321I和321Q以及两个混频器322I和322Q；移相模块(phase module)323；加法器324；和缓冲放大器325。
接收电路300B包括：高频部330；带通滤波器341；通道选择用PLL电路342；中频电路350；带通滤波器343；解调器360；中频用PLL电路344；分别与I通道的接收数据和Q通道的接收数据对应的两个带通滤波器345I和345Q以及两个模拟数字转换器(analog/digital converter，ADC)346I和346Q。高频部330包括：低噪声放大器331；缓冲放大器332和334；以及混频器333。中频电路350包括：缓冲放大器351和353；以及自动增益控制(Auto Gain Controller，AGC)电路352。调制器360包括：缓冲放大器361；分别与上述两个带通滤波器345I和345Q对应的两个混频器362I和362Q以及两个缓冲放大器363I和363Q；和移相模块364。
在该通信装置中，在I通道的发送数据和Q通道的发送数据被输入给发送电路300A的情况下，在后面的步骤中对各个发送数据进行处理。也就是，首先，在DAC 311I和311Q中将该发送数据转换成模拟信号。随后，在带通滤波器312I和312Q中将该发送信号频带之外的其他信号成分除去，然后将所得到的信号提供给调制器320。之后，在调制器320中，通过缓冲放大器321I和321Q将该信号提供给混频器322I和322Q，该所得到的信号与对应于由发送用PLL电路313提供的发送频率的频率信号进行混合，然后被调制。之后，这两个混合信号在加法器324中进行加法运算，于是得到了一个系统的发送信号。其间，对于被提供给混频器322I的频率信号，在移相模块323中已将该信号相位移动了90度。这样，I通道信号和Q通道信号相互正交地进行调制。最后，通过缓冲放大器325把信号提供给功率放大器314。于是，对该信号进行放大从而得到给定的发送功率。已在功率放大器314中放大的该信号经由发送/接收切换器301和高频滤波器302被提供给天线303，从而经由天线303以无线方式发送。高频滤波器302用作这样的带通滤波器：其用于除去该通信装置中所发送或接收到的信号中的在频带之外的其他信号成分。
另一方面，在接收电路300B经由高频滤波器302和发送/接收切换器301从天线303接收信号的情况下，在后面的步骤中对该信号进行处理。也就是，首先，在高频部330中，在低噪声放大器331处对所接收到的信号进行放大。随后，通过带通滤波器341除去所接收频带之外的其他信号成分。之后，通过缓冲放大器332把该信号提供给混频器333。接着，让该信号与由通道选择用PPL电路342提供的频率信号进行混合，并将给定的发送通道的信号设定为中频信号。因此，经由缓冲放大器334把该信号提供给中频电路350。随后，在中频电路350中，经由缓冲放大器351把该信号提供给带通滤波器343。于是，除去了中频信号频带之外的其他信号成分。所得到的信号随后在AGC电路352中变成基本恒定的增益信号。此后，经由缓冲放大器353将该信号提供给解调器360。随后，在解调器360中，经由缓冲放大器361把该信号提供给混频器362I和362Q。之后，让该信号与由中频用PPL电路344提供的频率信号进行混合。对I通道信号成分和Q通道信号成分进行解调。其间，对于被提供给混频器362I的频率信号，在移相模块364中已将该信号相位移动了90度。这样，对相互正交地进行了调制的I通道信号成分和Q通道信号成分进行解调。最后，分别将I通道信号和Q通道信号提供给带通滤波器345I和345Q，从而除去了I通道信号和Q通道信号之外的其他信号成分。之后，把该信号提供给ADC 346I和346Q，从而得到数字数据。因此，得到了I通道接收数据和Q通道接收数据。
在该通信装置中，应用了前述实施例和前述变形例中所述的中介层10A～10D来将天线303、高频滤波器302、带通滤波器341和343、调制器320以及解调器360与安装基板连接起来。因此，由于前述实施例中所述的作用，得到了较好的高频特性。
在图14所示的通信装置中，已经说明了将前述实施例和前述变形例中所述的中介层10A～10D应用于上述各构件与安装基板之间的连接的情况。然而，应用方式不总限于此。例如，中介层10A～10D可以应用于由各自微细化程度互不相同的CMOS器件和MEMS传感器构成的集成元件内的布线连接。在本例中，也能够得到与前述效果相同的效果。此外，中介层10A～10D能够应用于模拟电路器件和数字电路器件的集成化。
虽然已经参照实施例和变形例说明了本发明，但本发明不限于前述实施例等，并且可以做出各种变形。例如，在前述实施例中，使用贯通电极12来连接半导体芯片20与印制板30。然而，如果使用通孔布线来进行连接，也能得到同样的效果。
此外，在前述实施例等中，使用天线17作为电气元件(无源器件)。然而，该元件不限于此，而是也可以使用电感器或耦合器。此外，可以使用无源器件之外的其他电气元件(例如高频开关，用作高频传送线路的耦合电容器的变容二极管(varicap diode)，等等)，或者可以使用与电气元件结合的滤波器或可变滤波器。
本领域技术人员应当理解，依据设计要求和其它因素，可以在本发明所附的权利要求或其等同物的范围内进行各种修改、组合、次组合及改变。

Claims (12)

1.一种中介层，其包括：
基板，它具有正面和背面；
布线，它形成在所述基板的正面侧上并且与半导体芯片电连接；
电气元件，它与所述布线连接；以及
凹部，它在对应于所述电气元件的位置处从所述基板的背面侧形成。
2.如权利要求1所述的中介层，其中，所述电气元件是无源器件。
3.如权利要求2所述的中介层，其中，所述无源器件是天线、电感器或耦合器。
4.如权利要求1所述的中介层，其中，在所述基板上设有介电层，并且所述布线以至少一层的方式设在所述介电层中或所述介电层上。
5.如权利要求4所述的中介层，其中，所述介电层包含有机材料。
6.如权利要求4所述的中介层，其中，在所述基板与所述介电层之间设有绝缘层。
7.如权利要求1所述的中介层，其中，在所述基板中设有与所述布线连接的贯通电极。
8.如权利要求1所述的中介层，其中，所述基板是半导体基板或介电基板。
9.如权利要求8所述的中介层，其中，所述基板是硅基板。
10.一种模块，其包括：
中介层；以及
安装在所述中介层上的半导体芯片，
其中，所述中介层包括：
基板，它具有正面和背面，所述半导体芯片安装在所述基板的正面侧上；
布线，它形成在所述基板的正面侧上并与所述半导体芯片电连接；
电气元件，它与所述布线连接；以及
凹部，它在对应于所述电气元件的位置处从所述基板的背面侧形成。
11.如权利要求10所述的模块，其中，所述半导体芯片以如下方式与安装基板电连接：在所述半导体芯片和所述安装基板二者之间隔着所述布线和设置在所述基板中的贯通电极。
12.一种电子装置，其包括：
中介层；
安装在所述中介层上的半导体芯片；以及
与所述中介层电连接的安装基板，
其中，所述中介层包括：
基板，它具有正面和背面，所述半导体芯片安装在所述基板的正面侧上；
布线，它形成在所述基板的正面侧上并与所述半导体芯片电连接；
电气元件，它与所述布线连接；以及
凹部，它在对应于所述电气元件的位置处从所述基板的背面侧形成。
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