CN101965610A - 跨越高速外围互连总线的视频渲染 - Google Patents

跨越高速外围互连总线的视频渲染 Download PDF

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Publication number
CN101965610A
CN101965610A CN2008801258634A CN200880125863A CN101965610A CN 101965610 A CN101965610 A CN 101965610A CN 2008801258634 A CN2008801258634 A CN 2008801258634A CN 200880125863 A CN200880125863 A CN 200880125863A CN 101965610 A CN101965610 A CN 101965610A
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CN
China
Prior art keywords
graphics
memory
frame buffer
frame
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2008801258634A
Other languages
English (en)
Chinese (zh)
Inventor
J·程
T·拉维奥莱特
J·黄
R·扎布聚茨
J·朗
X·翁
S·马林科维奇
P·穆玛
M·简
M·特里西德
R·萨尔特切瓦
G·谢
I·利特奇马诺夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ATI Technologies ULC
Original Assignee
ATI Technologies ULC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATI Technologies ULC filed Critical ATI Technologies ULC
Priority to CN201710860732.1A priority Critical patent/CN107845374B/zh
Publication of CN101965610A publication Critical patent/CN101965610A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Information Transfer Systems (AREA)
CN2008801258634A 2007-11-30 2008-12-01 跨越高速外围互连总线的视频渲染 Pending CN101965610A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710860732.1A CN107845374B (zh) 2007-11-30 2008-12-01 跨越高速外围互连总线的视频渲染

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/987,559 US20080143731A1 (en) 2005-05-24 2007-11-30 Video rendering across a high speed peripheral interconnect bus
US11/987,559 2007-11-30
PCT/US2008/085160 WO2009073617A1 (en) 2007-11-30 2008-12-01 Video rendering across a high speed peripheral interconnect bus

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201710860732.1A Division CN107845374B (zh) 2007-11-30 2008-12-01 跨越高速外围互连总线的视频渲染

Publications (1)

Publication Number Publication Date
CN101965610A true CN101965610A (zh) 2011-02-02

Family

ID=40383655

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2008801258634A Pending CN101965610A (zh) 2007-11-30 2008-12-01 跨越高速外围互连总线的视频渲染
CN201710860732.1A Active CN107845374B (zh) 2007-11-30 2008-12-01 跨越高速外围互连总线的视频渲染

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201710860732.1A Active CN107845374B (zh) 2007-11-30 2008-12-01 跨越高速外围互连总线的视频渲染

Country Status (6)

Country Link
US (1) US20080143731A1 (https=)
EP (1) EP2225752B1 (https=)
JP (1) JP5529748B2 (https=)
KR (1) KR101545682B1 (https=)
CN (2) CN101965610A (https=)
WO (1) WO2009073617A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105389768A (zh) * 2015-10-21 2016-03-09 努比亚技术有限公司 图片处理方法及装置

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090027383A1 (en) 2003-11-19 2009-01-29 Lucid Information Technology, Ltd. Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition
US20080074429A1 (en) 2003-11-19 2008-03-27 Reuven Bakalash Multi-mode parallel graphics rendering system (MMPGRS) supporting real-time transition between multiple states of parallel rendering operation in response to the automatic detection of predetermined operating conditions
US8085273B2 (en) * 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US8497865B2 (en) * 2006-12-31 2013-07-30 Lucid Information Technology, Ltd. Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
US7961194B2 (en) 2003-11-19 2011-06-14 Lucid Information Technology, Ltd. Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US7808499B2 (en) * 2003-11-19 2010-10-05 Lucid Information Technology, Ltd. PC-based computing system employing parallelized graphics processing units (GPUS) interfaced with the central processing unit (CPU) using a PC bus and a hardware graphics hub having a router
EP1846834A2 (en) * 2005-01-25 2007-10-24 Lucid Information Technology, Ltd. Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US7861013B2 (en) * 2007-12-13 2010-12-28 Ati Technologies Ulc Display system with frame reuse using divided multi-connector element differential bus connector
US8890876B1 (en) * 2007-12-21 2014-11-18 Oracle America, Inc. Microprocessor including a display interface in the microprocessor
US9336752B1 (en) * 2007-12-21 2016-05-10 Oracle America, Inc. Microprocessor including a display interface in the microprocessor
CN101639930B (zh) * 2008-08-01 2012-07-04 辉达公司 一连串绘图处理器处理绘图数据的方法及系统
US9324294B2 (en) * 2009-04-07 2016-04-26 Nvidia Corporation Graphics system for supporting multiple digital display interface standards
US8316255B2 (en) * 2009-09-09 2012-11-20 Ati Technologies Ulc Method and apparatus for responding to signals from a disabling device while in a disabled state
US8482574B2 (en) * 2009-10-06 2013-07-09 Nvidia Corporation System, method, and computer program product for calculating statistics associated with a surface to be rendered utilizing a graphics processor
WO2011049881A2 (en) * 2009-10-19 2011-04-28 Barnes & Noble, Inc. Apparatus and method for control of multiple displays from a single virtual frame buffer
US8760459B2 (en) * 2009-12-30 2014-06-24 Intel Corporation Display data management techniques
US8963797B2 (en) * 2010-01-06 2015-02-24 Apple Inc. Display driving architectures
JP2011141707A (ja) 2010-01-07 2011-07-21 Sony Corp 情報処理装置、情報処理方法及びプログラム
US8659616B2 (en) * 2010-02-18 2014-02-25 Nvidia Corporation System, method, and computer program product for rendering pixels with at least one semi-transparent surface
JP2011188364A (ja) * 2010-03-10 2011-09-22 Xgi Technology Inc 多画面信号処理装置及び多画面システム
US20110242115A1 (en) * 2010-03-30 2011-10-06 You-Ming Tsao Method for performing image signal processing with aid of a graphics processing unit, and associated apparatus
US9164646B2 (en) * 2010-08-31 2015-10-20 Ati Technologies Ulc Method and apparatus for accommodating display migration among a plurality of physical displays
US10817043B2 (en) * 2011-07-26 2020-10-27 Nvidia Corporation System and method for entering and exiting sleep mode in a graphics subsystem
US9251552B2 (en) * 2012-06-28 2016-02-02 Intel Corporation Method and apparatus for managing image data for presentation on a display
JP2017097066A (ja) * 2015-11-19 2017-06-01 ルネサスエレクトロニクス株式会社 画像処理装置及び画像処理方法
US11074666B2 (en) * 2019-01-30 2021-07-27 Sony Interactive Entertainment LLC Scalable game console CPU/GPU design for home console and cloud gaming
US12488764B1 (en) * 2023-02-06 2025-12-02 Amazon Technologies, Inc. Compressing images for display on electronic labels

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1922596A (zh) * 2004-06-25 2007-02-28 恩维迪亚公司 分立的图形系统与方法

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0727556B2 (ja) * 1990-02-09 1995-03-29 富士通株式会社 バスアクセス方式
US5485562A (en) * 1993-09-14 1996-01-16 International Business Machines Corporation System and method for clipping pixels drawn in one of plurality of windows in a computer graphics system
US5712664A (en) * 1993-10-14 1998-01-27 Alliance Semiconductor Corporation Shared memory graphics accelerator system
US5488385A (en) * 1994-03-03 1996-01-30 Trident Microsystems, Inc. Multiple concurrent display system
JPH0922339A (ja) * 1995-07-05 1997-01-21 Matsushita Electric Ind Co Ltd 遠隔操作装置
US5896141A (en) * 1996-07-26 1999-04-20 Hewlett-Packard Company System and method for virtual device access in a computer system
WO1998032068A1 (en) * 1997-01-17 1998-07-23 Intergraph Corporation Multiple display synchronization apparatus and method
US6018340A (en) * 1997-01-27 2000-01-25 Microsoft Corporation Robust display management in a multiple monitor environment
US5949437A (en) * 1997-02-19 1999-09-07 Appian Graphics Corp. Dual video output board with a shared memory interface
US6104414A (en) * 1997-03-12 2000-08-15 Cybex Computer Products Corporation Video distribution hub
JPH1165719A (ja) * 1997-08-21 1999-03-09 Toshiba Corp コンピュータおよび画像表示方法
JPH11109937A (ja) * 1997-09-29 1999-04-23 Casio Comput Co Ltd 表示制御装置
US6040845A (en) * 1997-12-22 2000-03-21 Compaq Computer Corp. Device and method for reducing power consumption within an accelerated graphics port target
US6208361B1 (en) * 1998-06-15 2001-03-27 Silicon Graphics, Inc. Method and system for efficient context switching in a computer graphics system
US6532019B1 (en) * 1998-06-17 2003-03-11 Advanced Micro Devices, Inc. Input/output integrated circuit hub incorporating a RAMDAC
US6573905B1 (en) * 1999-11-09 2003-06-03 Broadcom Corporation Video and graphics system with parallel processing of graphics windows
US6624816B1 (en) * 1999-09-10 2003-09-23 Intel Corporation Method and apparatus for scalable image processing
US6760031B1 (en) * 1999-12-31 2004-07-06 Intel Corporation Upgrading an integrated graphics subsystem
US7079149B2 (en) * 2001-10-09 2006-07-18 Texas Instruments Incorporated System, method, and device for accelerated graphics port linking
US20030158886A1 (en) * 2001-10-09 2003-08-21 Walls Jeffrey J. System and method for configuring a plurality of computers that collectively render a display
US6864891B2 (en) * 2002-01-31 2005-03-08 Hewlett-Packard Development Company L.P. Switching between internal and external display adapters in a portable computer system
US6700580B2 (en) * 2002-03-01 2004-03-02 Hewlett-Packard Development Company, L.P. System and method utilizing multiple pipelines to render graphical data
US6886057B2 (en) * 2002-06-06 2005-04-26 Dell Products L.P. Method and system for supporting multiple bus protocols on a set of wirelines
US7102645B2 (en) * 2003-12-15 2006-09-05 Seiko Epson Corporation Graphics display controller providing enhanced read/write efficiency for interfacing with a RAM-integrated graphics display device
US7289125B2 (en) * 2004-02-27 2007-10-30 Nvidia Corporation Graphics device clustering with PCI-express
US7265759B2 (en) * 2004-04-09 2007-09-04 Nvidia Corporation Field changeable rendering system for a computing device
US6985152B2 (en) * 2004-04-23 2006-01-10 Nvidia Corporation Point-to-point bus bridging without a bridge controller
US20050237329A1 (en) * 2004-04-27 2005-10-27 Nvidia Corporation GPU rendering to system memory
JP2005316176A (ja) * 2004-04-28 2005-11-10 Toshiba Corp 電子機器及び表示制御方法
TWM261751U (en) * 2004-07-09 2005-04-11 Uniwill Comp Corp Switching display processing architecture for information device
US7721118B1 (en) * 2004-09-27 2010-05-18 Nvidia Corporation Optimizing power and performance for multi-processor graphics processing
US7545380B1 (en) * 2004-12-16 2009-06-09 Nvidia Corporation Sequencing of displayed images for alternate frame rendering in a multi-processor graphics system
US7730336B2 (en) * 2006-05-30 2010-06-01 Ati Technologies Ulc Device having multiple graphics subsystems and reduced power consumption mode, software and methods
US7817155B2 (en) * 2005-05-24 2010-10-19 Ati Technologies Inc. Master/slave graphics adapter arrangement
US7698579B2 (en) * 2006-08-03 2010-04-13 Apple Inc. Multiplexed graphics architecture for graphics power management

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1922596A (zh) * 2004-06-25 2007-02-28 恩维迪亚公司 分立的图形系统与方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105389768A (zh) * 2015-10-21 2016-03-09 努比亚技术有限公司 图片处理方法及装置
CN105389768B (zh) * 2015-10-21 2019-06-28 努比亚技术有限公司 图片处理方法及装置

Also Published As

Publication number Publication date
EP2225752B1 (en) 2016-03-23
JP5529748B2 (ja) 2014-06-25
EP2225752A1 (en) 2010-09-08
CN107845374A (zh) 2018-03-27
KR20100114496A (ko) 2010-10-25
CN107845374B (zh) 2021-10-01
KR101545682B1 (ko) 2015-08-19
WO2009073617A1 (en) 2009-06-11
JP2011509445A (ja) 2011-03-24
US20080143731A1 (en) 2008-06-19

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Application publication date: 20110202