JP5529748B2 - 高速周辺相互接続バスにおけるビデオレンダリング - Google Patents

高速周辺相互接続バスにおけるビデオレンダリング Download PDF

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Publication number
JP5529748B2
JP5529748B2 JP2010536221A JP2010536221A JP5529748B2 JP 5529748 B2 JP5529748 B2 JP 5529748B2 JP 2010536221 A JP2010536221 A JP 2010536221A JP 2010536221 A JP2010536221 A JP 2010536221A JP 5529748 B2 JP5529748 B2 JP 5529748B2
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Japan
Prior art keywords
graphics
memory
display
processor
graphics subsystem
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JP2010536221A
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English (en)
Japanese (ja)
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JP2011509445A (ja
JP2011509445A5 (https=
Inventor
チェン ジェフリー
ラヴィオレット テリー
フアン ジェームス
ザブルジッキ ロバート
ロン ジェイソン
ウェン シアンチュエン
マリンコヴィック ササ
ムンマー フィル
チェン ミンウェイ
トレシッダー マイケル
サルチェフ ルーメン
シエ ジョージ
リチマノフ ユーリ
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ATI Technologies ULC
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ATI Technologies ULC
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Publication of JP2011509445A5 publication Critical patent/JP2011509445A5/ja
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Information Transfer Systems (AREA)
JP2010536221A 2007-11-30 2008-12-01 高速周辺相互接続バスにおけるビデオレンダリング Active JP5529748B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/987,559 US20080143731A1 (en) 2005-05-24 2007-11-30 Video rendering across a high speed peripheral interconnect bus
US11/987,559 2007-11-30
PCT/US2008/085160 WO2009073617A1 (en) 2007-11-30 2008-12-01 Video rendering across a high speed peripheral interconnect bus

Publications (3)

Publication Number Publication Date
JP2011509445A JP2011509445A (ja) 2011-03-24
JP2011509445A5 JP2011509445A5 (https=) 2012-01-26
JP5529748B2 true JP5529748B2 (ja) 2014-06-25

Family

ID=40383655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010536221A Active JP5529748B2 (ja) 2007-11-30 2008-12-01 高速周辺相互接続バスにおけるビデオレンダリング

Country Status (6)

Country Link
US (1) US20080143731A1 (https=)
EP (1) EP2225752B1 (https=)
JP (1) JP5529748B2 (https=)
KR (1) KR101545682B1 (https=)
CN (2) CN101965610A (https=)
WO (1) WO2009073617A1 (https=)

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Also Published As

Publication number Publication date
EP2225752B1 (en) 2016-03-23
EP2225752A1 (en) 2010-09-08
CN107845374A (zh) 2018-03-27
KR20100114496A (ko) 2010-10-25
CN107845374B (zh) 2021-10-01
CN101965610A (zh) 2011-02-02
KR101545682B1 (ko) 2015-08-19
WO2009073617A1 (en) 2009-06-11
JP2011509445A (ja) 2011-03-24
US20080143731A1 (en) 2008-06-19

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