CN101964635A - Automatic gain control method for digital signal - Google Patents
Automatic gain control method for digital signal Download PDFInfo
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- CN101964635A CN101964635A CN2010105218565A CN201010521856A CN101964635A CN 101964635 A CN101964635 A CN 101964635A CN 2010105218565 A CN2010105218565 A CN 2010105218565A CN 201010521856 A CN201010521856 A CN 201010521856A CN 101964635 A CN101964635 A CN 101964635A
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Abstract
The invention discloses an automatic gain control method for a multichannel signed N-digit digital signal expressed by two's complement. The method comprises the following steps of: converting each signed N-digit digital signal into a corresponding absolute value signal; performing bit orient exclusive disjunction on the absolute value signal so as to obtain an or signal; generating a corresponding locking index signal for a specified position of the or signal; controlling a plurality of cascaded multiplexers by using the locking index signal; acquiring a signal S of an output end of the last multiplexer; and shifting each signed N-digit digital signal leftwards according to the signal S and outputting the signal. The method of the invention can be used for measuring a beam position and has the advantages of high beam position resolution, quick automatic gain control and the like.
Description
Technical field
The present invention relates to the auto gain control method of digital signal, particularly be used for the digital signal auto gain control method of accelerator numeral line position monitoring system (DBPM).
Background technology
It is the important component part of accelerator beam diagnostics system that (BPM) system is measured in the beam position.By this system, except direct measurement beam position, can also indirect calculation go out important parameters such as working point, damping time, phasor.This system also is the important component part of accelerator track reponse system simultaneously.
On the accelerator position of electron beam in the line vacuum pipe as shown in Figure 1, its direction is inside perpendicular to paper, and four button type BPM probes of A, B, C, D are arranged in addition.Adopt difference ratio and signal processing method by four detected signals of probe, position X, the Y of calculated level and vertical direction, computing formula is as follows:
X＝k
X((V
A+V
D)-(V
B+V
C))/∑
Y＝k
Y((V
A+V
B)-(V
C+V
D))/∑
Wherein:
V
A, V
B, V
C, V
DThe electrode signal intensity of representing A, B, C, four probe places of D respectively;
∑＝V
A+V
B+V
C+V
D；
k
XAnd k
YBe the probe calibration coefficient, only relevant with the geometry of probe, have the length dimension, when X, Y hour,
Wherein a is a probe radius.
In order to obtain higher resolution, BPM has the gain-adjusted function.Usually, the adjusting of the automatic gain of digital BPM (DBPM) is the radiofrequency signal of regulating input by the amplifying circuit of the digital signal FEEDBACK CONTROL rf analog front-end after sampling, processing.This mode at first needs rf gain and adjusts circuit, and complex structure can't be realized in some commercial digital signal panel cards.Because be based on feedback principle, certain hysteresis is arranged simultaneously.
RF front-end module and digital signal processing module that the at present conventional DBPM system that uses is all integrated has the gain-adjusted function.Wherein, radio-frequency front-end partly has amplification and attenuation device, finishes the gain-adjusted to radiofrequency signal, guarantees that its amplitude is within the dynamic range of follow-up ADC.And many general commercial digital signal-processing boards based on the FPGA complicated radio-frequency front-end not like this on the market does not possess the function of regulating radiofrequency signal.Therefore, digital signal processing module is under the situation that the input radio frequency signal amplitude changes, can't guarantee that the signal of exporting can obtain maximum significance bits, position resolution is lower, and the application that general commercial digital signal-processing board is detected in the accelerator beam position has been subjected to very big restriction.
Summary of the invention
Technical problem to be solved by this invention provides the auto gain control method that a kind of multichannel of representing with the complement of two's two's complement has symbol N position digital signal, make still have enough significance bits in a high position, and overcome the complexity of rf gain adjustment circuit and the hysteresis that causes by feedback through the digital signal after handling.
For solving the problems of the technologies described above, technical scheme of the present invention is as follows:
A kind of auto gain control method of digital signal, described digital signal are with the multichannel that the complement of two's two's complement is represented symbol N position digital signal to be arranged, and this symbol N position digital signal is arranged is to be the periodic signal of T in the cycle, N=8 * 2 wherein
n, n is a nonnegative integer, T＞0, and this method may further comprise the steps: with each described absolute value signal that has symbol N position digital signal to convert correspondence to; Exclusive disjunction is made in described absolute value signal step-by-step, obtained or signal; Generate the lock indication signal of correspondence for i to the j position of described or signal, make described lock indication signal have initial value for " 0 ", and when the k position of described or signal was " 1 ", lock indication signal set that will be corresponding with this in the next clock cycle also kept, and wherein i, j are integer, and 0≤i≤j-1, j≤N-2, k are integer, and i≤k≤j, clock cycle is t, t＞0; Control j-i+1 multiplexer respectively with the lock indication signal corresponding with i to the j position of described or signal, described multiplexer has first input end respectively, second input and output, and the output of the multiplexer of the lock indication signal corresponding with the m position of described or signal control connects the first input end of the multiplexer of controlling with the corresponding lock indication signal in the m+1 position of described or signal, wherein m is an integer, and i≤m≤j-1, second input of the multiplexer of the lock indication signal control corresponding with the k position of described or signal has second input end signal that predefined value is j-k, the first input end of the multiplexer of the lock indication signal control corresponding with the i position of described or signal also has predefined first input end signal j-i+1, when lock indication signal is " 1 ", the multiplexer of this lock indication signal control is exported the signal of second input in the next clock cycle, otherwise, the signal of output first input end; G clock cycle, obtain the signal S of output of the multiplexer of the lock indication signal corresponding control with the j position of described or signal, g=T/t, and g is an integer; Each is describedly had symbol N position digital signal to shifting left and exporting, and the figure place of displacement is the represented decimal number of signal S.
Described step can realize in FPGA.
The present invention can be used for the beam position and measures, under the situation of not using RF front-end module with gain-adjusted function, utilize the commercial digital signal-processing board that the narrow band signal on the storage rings is handled, make it to carry out automatically the gain amplification of numeric field with the power of beam current signal, still have enough significance bits through the signal after a series of processing in a high position, improve beam position resolution, efficiently solve general commercial digital signal-processing board because of lacking the application limitation of measuring in the beam position that special-purpose radio-frequency front-end brings.In addition, owing to directly utilize the ADC sampled signal, rather than, therefore can carry out automatic gain control fast based on feedback principle.For SSRF, storage rings signals sampling rate is 169 times of cyclotron frequencies, can think constant by force at the stream of the short time of signal processing internal beam current, and therefore 169 clock cycle of the longest needs can obtain stable displacement figure place under partially filled pattern.At last, the Digital Logic that the present invention is based on FPGA realizes, parallel, high speed and stable.
Description of drawings
Fig. 1 is a line schematic diagram in the accelerator;
Fig. 2 is the digital addition schematic diagram;
Fig. 3 is digital addition, multiplication schematic diagram;
Fig. 4 is to digital addition, multiplication schematic diagram after the input signal displacement;
Fig. 5 is four-way sampling back signal schematic representation;
Fig. 6 is the Realization of Automatic Gain Control schematic diagram;
Fig. 7 is four-way digital signal and its absolute value signal sectional drawing;
Fig. 8 is a four-way absolute value signal sectional drawing mutually or afterwards;
Fig. 9 is or signal and lock indication signal sectional drawing;
Figure 10 is the output sectional drawing of each ring on the shift chain;
Figure 11 is for exporting through each passage of displacement back;
Figure 12 is a schematic diagram behind the four-way data shift.
Embodiment
Below with reference to the accompanying drawings, provide preferred embodiment of the present invention, and described in detail, enable to understand better function of the present invention, characteristics.
Measure for carrying out the beam position, the common commercial digital signal panel needs four ADC chips that correspond respectively to four passages, the detected electrode signal intensity of popping one's head in of sampling respectively four.
Position signalling for different rates such as obtaining from coil to coil on the accelerator storage rings, obtain soon, completely obtain need be further processed the digital signal after the ADC sampling, and this carries out in FPGA.
FPGA is widely used in the various fields of Digital Signal Processing because of multifrequency natures such as its user-programmable, high-speed parallel and low-power consumption.Problem is blocked in the position that inevitably causes because of the position expansion in Digital Signal Processing.With the addition is example, establishes two four figures that symbol is arranged according to x=7, y=7, then x+y=14.Calculating process in FPGA such as Fig. 2.As seen, expanded one through data after the add operation.If multiplying, then the data bit expansion is one times.And the combination of a series of multiply-add operation etc. often of Signal Processing process, if the significance bit of every grade of computing all keeps, last operation result figure place is appreciable.But in fields such as communications, major concern be the signal frequency domain part, to signal fixedly the amplitude increase and decrease that causes of the displacement of figure place can't influence its frequency domain characteristic.
With domain class such as communication seemingly, in the beam position signal of accelerator is handled, be to reduce the output result length, tend to after every grade of computing, the result to be carried out low level block, keep high-order input as subordinate's computing.
But if input signal strength is lower, the significance bit after the AD sampling is fewer, may not have useful signal through the high position data that keeps behind the multistage operations, or seldom.With Fig. 3 is example, and four signed number is according to x=3, y=3, and the result is 6 after the computing through adding, and carries out multiplying 6 * 6=36 again, then expands to 10 bit data 0000100100, high 4 have not had significance bit.If need obtain valid data, must make the high position of operation result that more significance bits be arranged to the input signal gain-adjusted that is shifted at Gao Siwei.
As shown in Figure 4, after displacement, operation result also has the useful signal position at high four.
With 16 ADC is example, and the data hypothesis of four-way radiofrequency signal behind over-sampling as shown in Figure 5.Electron beam with near light velocity operation, is an example with the SSRF in track, and a second, general operation 700,000 was enclosed.In a second, can think that signal strength signal intensity is constant, so the signal significance bit basic fixed of ADC.Because of the skew of beam position, the signal strength signal intensity that each probe is sensed has nothing in common with each other simultaneously, may be also variant through the signal significance bit of their 16 bit data after the ADC sampling.
Present embodiment has four-way input, and each passage has 16 ADC chips of a slice, and other has the commercial digital signal-processing board of a slice high-performance FPGA to gather on the accelerator storage rings signal as input signal.Carry out emulation under ModelSim, for ease of observing, have only A, C two-way to connect signal, B, D two-way are unsettled.
As shown in Figure 6, at first each the passage signed number word signal represented with the complement of two's two's complement after the ADC sampling is taken absolute value, obtain corresponding absolute value signal.This signed number word signal is to be the periodic signal of T in the cycle, T＞0.For the purpose of convenient the description, suppose that digital signal is the N position, from a high position to the low level, be followed successively by the N-1 position, the N-2 position ..., the 0th, N=8 * 2
n, n is a nonnegative integer.As shown in Figure 7, what rx_a_16b, rx_b_16b, rx_c_16b, rx_d_16b were respectively the A, the B that represent with the complement of two's two's complement after the ADC sampling, C, four passages of D has 16 integers of symbol, and its corresponding absolute value signal is respectively rx_a_16b_abs, rx_b_16b_abs, rx_c_16b_abs, rx_d_16b_abs.It is certain zero that the high position of rx_a_16b_abs, rx_b_16b_abs, rx_c_16b_abs, rx_d_16b_abs all has, and wherein public invalid bit is exactly the figure place that we need move to left.
Secondly, exclusive disjunction is made in each absolute value signal step-by-step, obtained or signal, the result as shown in Figure 8.As seen from Figure 8, high 4 of signal never has data after the exclusive disjunction.It is directly perceived that upward we can judge and move to left three (the 4th then should keep as sign bit) to input signal.
Once more, for or i to the j position of signal generate corresponding lock indication signal, i, j are integer, and 0≤i≤j-1, j≤N-2.Because N=16 (being n=1) in the present embodiment, the 15th of highest order is 0 when taking absolute value as sign bit certainly, therefore needn't detect.In addition, under the situation that does not insert signal, the noise signal level also can reach tens level, and therefore, low level also needn't detect.Detection range in the present embodiment is the 14th to 4, i.e. i=4, j=14.As shown in Figure 9, inp_mod_check (14:4) is or the 14th to 4 of signal, and inp_lock (10:0) is its corresponding lock indication signal, and rx_clk is a clock signal, and the clock cycle is t, t＞0.Wherein corresponding with inp_mod_check (k) lock indication signal is inp_lock (j-k), and k is an integer, and i≤k≤j.As shown in Figure 9, described lock indication signal has the initial value for " 0 ", in case and certain the position appearance " 1 " among the inp_mod_check (14:4), lock indication signal set that will be corresponding with this in the next clock cycle also keeps.As shown in Figure 9, second clock cycle, or signal inp_mod_check (11), inp_mod_check (6), inp_mod_check (5), inp_mod_check (4) are " 1 ", therefore the 3rd clock cycle, inp_lock (3), inp_lock (8), inp_lock (9), inp_lock (10) set also keep.Similarly, the 4th clock cycle, inp_lock (4:7) set also keeps.But inp_lock (2:0) does not have set all the time.
Then, utilize lock indication signal to determine the displacement figure place.As shown in Figure 6, with with or the corresponding lock indication signal in i to the j position of signal control j-i+1 multiplexer respectively, each multiplexer has first input end respectively, second input and output, and with or the output of the multiplexer inp_mov_r (m-i) of corresponding lock indication signal inp_lock (j-m) control in the m position of signal connect with or the first input end of the multiplexer inp_mov_r (m-i+1) that controls of the corresponding lock indication signal inp_lock (j-m-1) in the m+1 position of signal, wherein m is an integer, and i≤m≤j-1, with or second input of the multiplexer inp_mov_r (k-i) of corresponding lock indication signal inp_lock (j-k) control in the k position of signal have second input end signal that predefined value is j-k, with or the first input end of the multiplexer inp_mov_r (0) of corresponding lock indication signal inp_lock (j-i) control in the i position of signal also have predefined first input end signal j-i+1, when lock indication signal is " 1 ", the multiplexer of this lock indication signal control is exported the signal of second input in the next clock cycle, otherwise, the signal of output first input end.G clock cycle, obtain with or the signal S of the output of the multiplexer inp_mov_r (j-i) of corresponding lock indication signal inp_lock (0) control in the j position of signal, the represented decimal number of this signal S figure place that is shifted exactly, g=T/t, and g is an integer.Because inp_lock (0)=0, so the multiplexer inp_mov_r (10) of its control is output as the signal of its first input end, the i.e. output signal of inp_mov_r (9).By this analysis, because inp_lock (1) equals 0 with inp_lock (2), then the output of inp_mov_r (10) is finally determined by the output of inp_mov_r (7).Owing to, therefore export the signal of second input, i.e. " 0011 " at the 4th clock cycle inp_mov_r (7) at the 3rd clock cycle inp_lock (3)=1.After transmitting three clock cycle, also promptly the 7th clock cycle, the output signal S of inp_mov_r (10) is " 0011 ".Inp_lock (3)=1 illustrates inp_mod_check (14-3)=1, and promptly inp_mod_check (11)=1 that is to say that original signal begins that at the 11st signal is arranged.From Figure 10, can see the cascade process of whole output shift chain.Final output inp_mov_r (10)=" 0011 " (promptly should move to left 3) also keeps, and the result is consistent with our the displacement figure place of intuitive judgment.
According to the displacement figure place to the digital signal before taking absolute value to shifting left and exporting.From Figure 11 as seen, low three after the displacement all is 0, and shifting purposes realizes.Figure 12 is a schematic diagram behind the four-way data shift.
For the beam position computing, the four-way signal is differed from than carrying out the numerical value that unified shift operation causes with, four-way increase 2 because be
s(s is the figure place that moves to left) is to not influence of result.
Obviously, in the above teachings, may carry out multiple correction and modification to the present invention.For example, the digital signal after the ADC sampling can be 8,32,64 etc., also can adjust according to application with generating specific bit lock indication signal or signal.Within the scope of the appended claims, the present invention can implement to be different from specifically described mode.
Claims (4)
1. the auto gain control method of a digital signal, described digital signal is with the multichannel that the complement of two's two's complement is represented symbol N position digital signal to be arranged, and this symbol N position digital signal is arranged is to be the periodic signal of T in the cycle, N=8 * 2 wherein
n, n is a nonnegative integer, T＞0, and this method may further comprise the steps:
With each described absolute value signal that has symbol N position digital signal to convert correspondence to;
Exclusive disjunction is made in described absolute value signal step-by-step, obtained or signal;
Generate the lock indication signal of correspondence for i to the j position of described or signal, make described lock indication signal have initial value for " 0 ", and when the k position of described or signal was " 1 ", lock indication signal set that will be corresponding with this in the next clock cycle also kept, and wherein i, j are integer, and 0≤i≤j-1, j≤N-2, k are integer, and i≤k≤j, clock cycle is t, t＞0;
Control j-i+1 multiplexer respectively with the lock indication signal corresponding with i to the j position of described or signal, described multiplexer has first input end respectively, second input and output, and the output of the multiplexer of the lock indication signal corresponding with the m position of described or signal control connects the first input end of the multiplexer of controlling with the corresponding lock indication signal in the m+1 position of described or signal, wherein m is an integer, and i≤m≤j-1, second input of the multiplexer of the lock indication signal control corresponding with the k position of described or signal has second input end signal that predefined value is j-k, the first input end of the multiplexer of the lock indication signal control corresponding with the i position of described or signal also has predefined first input end signal j-i+1, when lock indication signal is " 1 ", the multiplexer of this lock indication signal control is exported the signal of second input in the next clock cycle, otherwise, the signal of output first input end;
G clock cycle, obtain the signal S of output of the multiplexer of the lock indication signal corresponding control with the j position of described or signal, g=T/t, and g is an integer;
Each is describedly had symbol N position digital signal to shifting left and exporting, and the figure place of displacement is the represented decimal number of signal S.
2. multichannel digital signal auto gain control method as claimed in claim 1 is characterized in that n=1.
3. multichannel digital signal auto gain control method as claimed in claim 2 is characterized in that, i=4, j=14.
4. as each described multichannel digital signal auto gain control method in the claim 1 to 3, it is characterized in that described step realizes in FPGA.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104166152A (en) * | 2014-08-18 | 2014-11-26 | 中国科学院上海应用物理研究所 | Self-triggering method for detecting abnormal beams of particle accelerator |
| CN104506293A (en) * | 2014-12-30 | 2015-04-08 | 中国科学院上海应用物理研究所 | Carrier suppression radio frequency front end, carrier suppression method, and beam position measurement system and method |
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| CN104506293A (en) * | 2014-12-30 | 2015-04-08 | 中国科学院上海应用物理研究所 | Carrier suppression radio frequency front end, carrier suppression method, and beam position measurement system and method |
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