CN101951243B

CN101951243B - Full digital phase modulation and amplitude modulation clock generating circuit for switch power amplifier

Info

Publication number: CN101951243B
Application number: CN2010105035013A
Authority: CN
Inventors: 孙立崇; 葛敏; 闵昊
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2010-10-12
Filing date: 2010-10-12
Publication date: 2012-05-30
Anticipated expiration: 2030-10-12
Also published as: CN101951243A

Abstract

The invention belongs to the technical field of clock generating circuits, and particularly relates to a multi-order phase modulation and amplitude modulation clock generating circuit for a switch power amplifier. The circuit comprises a multi-channel same-frequency clock generating circuit, an initial phase clock processing circuit, an end phase clock processing circuit, an output clock selecting circuit and the like. The multi-channel same-frequency clock generating circuit is used for providing a clock source for a phase modulation and amplitude modulation control circuit; the initial phase clock processing circuit and the end phase clock processing circuit generate clock signals with required phases and duty ratio changes by combination of clocks of two channels; and the output clock selecting circuit provides the required phase and duty ratio requirement. The circuit can generate the required phase modulation and amplitude modulation clock and ensure safe operation of the switch power amplifier.

Description

The digital phase-modulation and amplitude-modulation clock forming circuit that is used for switch power amplifier

Technical field

The invention belongs to the clock forming circuit technical field, be specifically related to a kind of multistage phase-modulation and amplitude-modulation clock forming circuit that is used for switch power amplifier.

Background technology

Usually D class switch power amplifier adopts pulse width modulation (PWM) to realize that power output follows control signal and change.The generation of traditional P WM signal adopts the method for analog circuit to realize mostly.Constitute a high-speed comparator with operational amplifier, add the positive input terminal that is placed on comparator behind certain direct current biasing to control signal, generate the negative input end that a triangular wave is added to amplifier through self-oscillation in addition.Through the current potential generation PWM waveform as shown in Figure 1 on comparator anode relatively and the negative terminal, when signal was higher than negative terminal triangular wave current potential, comparator was output as high level, on the contrary output low level then.But the wave amplitude up and down of common control signal differs and aligns with the wave amplitude of triangular wave surely, if the too high or too low modulation that will cause of control signal waveform is out-of-sequence, thereby produces mistake.In addition because analog circuit makes Digital Implementation pulse width modulation become more and more important to the low tolerance that disturbs and to the complexity of phase modulated.One of main purpose of the present invention is to solve traditional analog method anti-interference difference and the out-of-sequence problem of modulation, reduces circuit scale simultaneously, reduces application cost.

Summary of the invention

The technical problem that the present invention will solve is to realize the pulse width modulation and the phase shift modulated of switch power amplifier through digital circuit, guarantees the normal orderly work of switch power amplifier.

In order to achieve the above object, the present invention provides a digital phase-modulation and amplitude-modulation clock forming circuit that is used for switch power amplifier.This circuit comprises that 18 1, two 18 of identical frequency clock forming circuit select 3,9, two 5-32

bit decoders

2,10 of 1 selector; Two divide by four circuits 4,8, alternative selector 5, four selects a selector 7; Four overlap mutually clock forming circuit 11, clock combined treatment circuit 6.Wherein, said 18 identical frequency clock forming circuits 1 are made up of 9 tunnel difference symmetry clock, and this circuit is produced the clock signal of 18 road same phases poor (being that phase intervals is 20 degree) by 9 grades of ring oscillators; Select 1

selector

3,9 for two 18, choose the two-way in 18 road clocks respectively, as the prime minister's bit clock and the last phase clock of pulse width modulation and phase shift modulated; And through obtaining the drive clock of required frequency under the carrier wave behind two divide by four circuit 4,8,4 frequency divisions; Simultaneously; Choose maximum phase shift in 18 road clocks a road as 4 overlap mutually clock forming circuit 11 drive clock; Select a selector 7 through alternative selector 5 with through four respectively; Get into divide by four circuit 4 and divide by four circuit 8 more respectively, promptly define prime minister's bit clock and the required pulse duration of last phase clock under carrier frequency through choosing 4 suitable phase clock time windows; At last through offering power amplifier through the clock combined treatment circuit 6 synthetic

differential clocks

12,13 that have phase place and pulse width information at last; Two 5-32

bit decoders

2,10 select 1

selector

3,9 to be connected with two 18 respectively.

Among the present invention, said four overlap mutually clock forming circuit 11 receives electrification reset 14 controls, makes the phase-modulation and amplitude-modulation generative circuit when incoming call, produce correct sequential.

Among the present invention, said clock combined treatment circuit 6 is a combinational logic circuit, by with door and not gate logical constitution, and be the difference symmetrical structure.

Among the present invention, said clock control position is 13 bit controls.

Among the present invention, said 18 tunnel clock frequencies become 4 frequencys multiplication relation with the carrier frequency of last output, and this frequency multiplication relation is consistent with the number of phases of overlapping clock forming circuit output.

Among the present invention, said 2 divide by four circuits constitute by the d type flip flop that has reseting controling signal.

Characteristics of the present invention are: in phase modulated and pulse width modulation, adopt basic digital circuit to realize fully, improved traditional analog method anti-interference difference and the out-of-sequence problem of modulation.Adopt digital method to realize that phase modulated and pulse-width modulation have reduced circuit scale simultaneously, have reduced application cost.

Description of drawings

The pulse width modulation that Fig. 1 realizes for analogy method.

Fig. 2 is the theory diagram of the digital phase-modulation and amplitude-modulation clock forming circuit of the present invention.

Fig. 3 is the sequential chart of the digital phase-modulation and amplitude-modulation clock forming circuit of the present invention.

Embodiment

Bottom combines accompanying drawing and embodiment that the present invention is described in further detail:

Digital phase-modulation and amplitude-modulation clock forming circuit as shown in Figure 2 comprises that 18 identical frequency clock forming circuits 1, two 18 select 1

selector

3 and 9, two 5-32

bit decoders

2 and 10, two divide by four circuits 4 and 8, alternative selector 5, four to select a selector 7, four to overlap mutually clock forming circuit 11, clock combined treatment circuit 6 etc.

At first, the 18 phase shift clocks that clock forming circuit provides are selected an initial phase clock, then this clock is carried out 4 frequency divisions and obtain the identical power amplifier drive clock 1 of phase place through the control of P4, P3, P2, P1, P0.Through the control of P5, can freely select last power amplifier drive clock phase shift is greater than 90 degree or less than 90 degree.As shown in Figure 3, P5 can selection cycle T1 and T2 in just along clock, wherein T1 represents phase shift between 0 to 85 degree, stepping accuracy is 5 degree; T2 represents phase shift between 90 to 175 degree, and stepping accuracy is 5 degree; Thereby can realize 36 rank phase shift modulated altogether.

Secondly, through the control of S4, S3, S2, S1, S0, the 18 phase shift clocks that clock forming circuit provides are selected an end phase clock, this clock is carried out 4 frequency divisions obtains the identical power amplifier drive clock 2 of phase place equally then.Through the selection of S6 and S5, select a clock and drive clock 1 and make up and obtain the needed clock signal that had not only had phase shift but also had duty cycle adjustment.As shown in Figure 3, S6 and S5 have four kinds of combinations, can selection cycle T1, in the T2, T3, T4 just along clock, wherein T1 represents phase shift between 0 to 85 degree, pulse duration just along duty ratio smaller or equal to 12.5%, stepping accuracy is about 1.39%; T2 represents phase shift between 0 to 85 degree, pulse duration just along duty ratio greater than 12.5% but smaller or equal to 25%, stepping accuracy is about 1.39%; T3 represents phase shift between 90 to 175 degree, pulse duration just along duty ratio greater than 25% smaller or equal to 37.5%, stepping accuracy is about 1.39%; T4 represents phase shift between 90 to 175 degree, pulse duration just along duty ratio greater than 37.5% but smaller or equal to 50%, stepping accuracy is about 1.39%; Thereby can realize 36 rank pulse width modulations altogether.

This circuit have 13 bit control bits (be P={P4, P3, P2, P1, P0}, P5, S={S4, S3, S2, S1, S0}, S6, S5), so can form 8192 kinds of combinations of states in theory.But the requirement of clock signal is had 1296 kinds of output clock status according to system.For fear of the unwanted clock status of output, to the use of control bit total below several kinds of constraints:

1) suppose P={P4, P3, P2, P1, P0}, S={S4, S3, S2, S1, S0}, then the effective control bit of P and S be 0=P=17,0=< S ≤17, export if P and S, then all have clock greater than above-mentioned scope by respectively corresponding 18 kinds of input clock phase places.

2) P5 has only 0 and 1 two states, and 0 represents phase shift in 0 to 85 degree scope, and 1 represents phase shift between 90 to 175 degree.When P5 equals 0, and S6, S5} have only 0,0}, 0, and 1} with 1, three kinds of combinations of 0}; When P5 equals 1, and S6, S5} have only 0,1}, 1, and 0} with 1, three kinds of combinations of 1}.

It should be noted last that above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although the present invention is specified with reference to embodiment; Those of ordinary skill in the art is to be understood that; Technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and the scope of technical scheme of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.

Claims

1. a digital phase-modulation and amplitude-modulation clock forming circuit that is used for switch power amplifier is characterized in that, this circuit comprises 18 identical frequency clock forming circuits (1); Select 1 selector (3,9) for two 18, two 5-32 bit decoders (2,10), two divide by four circuits (4,8); Alternative selector (5); Four select a selector (7), and four overlap mutually clock forming circuit (11), clock combined treatment circuit (6); Wherein:

Said 18 identical frequency clock forming circuits (1) are made up of 9 tunnel difference symmetry clock, and this 18 identical frequency clock forming circuit is produced the clock signal of 18 road same phase differences by 9 grades of ring oscillators; Select 1 selector (3,9) for two 18, choose the two-way in 18 road clocks respectively, as the prime minister's bit clock and the last phase clock of pulse width modulation and phase shift modulated; And, obtain the drive clock of required frequency under the carrier wave behind 4 frequency divisions through two divide by four circuits (4,8); Simultaneously; Choose maximum phase shift in 18 road clocks a road as 4 overlap mutually clock forming circuit (11) drive clock; Select a selector (7) through alternative selector (5) and four respectively; Get into divide by four circuit (4,8) more respectively, promptly define prime minister's bit clock and the required pulse duration of last phase clock under carrier frequency through choosing 4 suitable phase clock time windows; Offer power amplifier through the synthetic differential clocks (12,13) that has phase place and pulse width information of clock combined treatment circuit (6) at last; Two 5-32 bit decoders (2,10) select 1 selector (3,9) to be connected with two 18 respectively.

2. the digital phase-modulation and amplitude-modulation clock forming circuit that is used for switch power amplifier according to claim 1; It is characterized in that; Said four overlap mutually clock forming circuit (11) receives electrification reset (14) control, makes the phase-modulation and amplitude-modulation generative circuit when incoming call, produce correct sequential.

3. the digital phase-modulation and amplitude-modulation clock forming circuit that is used for switch power amplifier according to claim 1 is characterized in that said clock combined treatment circuit (6) is a combinational logic circuit, by with door and not gate logical constitution, and be the difference symmetrical structure.