RU2401514C2 - Digital phase-difference manipulator - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: proposed phase-difference manipulator comprises reference oscillator, 8-ratio divider, D-trigger, permanent memory, two-digit accumulating adder, pulse generator, register. Note here that pulse generator is built around serial register, inverter and AND gate.

EFFECT: shaping of phase-difference signal with one- and two-fold relative phase manipulation with no abrupt change in duration of output signal half-period during change of oscillation phase.

2 cl, 9 dwg

Description

The invention relates to radio communications technology, in particular to phase-difference modulators with single and double relative phase shift keying for high-power transmitters, and can be used in data transmission equipment.

A device that is used as a phase difference manipulator [1. Shlyapobersky V.I. Fundamentals of discrete messaging technology. M., "Communication", 1973, p.228, Fig.4.37], containing a carrier frequency generator, two triggers and an adder modulo two. The disadvantage of this device is a sharp change in the duration of the half-periods of the output signal at the time of the change in the oscillation phase.

Of the known digital phase difference manipulators, the closest in technical essence is a pulsed phase difference manipulator [2. Zaezdny A.M. Phase difference modulation and its application for transmitting discrete information. M., "Communication", 1967, p.62, Fig.2.6], containing a reference frequency generator, an eight divider, two keys and a decoder. At the output of the divider, the oscillation of the carrier frequency, manipulated in phase, is a rectangular voltage, since the division of the frequency is carried out on the triggers.

The disadvantage of this device is also a sharp change (from zero to two times) the duration of the half-periods of the output signal at the time of the change of the oscillation phase. The use of this device in the transmitter as a modulator, connected, for example, in series with a key power amplifier with a transformer output and an oscillatory circuit in the load, leads to spurious amplitude modulation of the output signal, large voltage spikes on the output transistors and the possibility of the transmitter failing.

The aim of the invention is the formation of a phase-difference signal with single and double relative phase manipulation without a sharp change in the duration of the half-periods of the output signal at the time of changing the phase of the oscillation.

This goal is achieved by the fact that the digital phase-difference manipulator, comprising a reference frequency generator and an eight divider in series, is additionally equipped with a D-trigger, read-only memory, a two-bit accumulating adder, a pulse shaper and a register, the first and second inputs of the two-bit accumulating adder being the same information inputs of a digital phase difference manipulator, the third input of a two-bit accumulating adder and the first input the pulse shaper are combined and are the third (clock) input of the digital phase difference manipulator, the first two outputs of the eight divider are connected to the corresponding inputs of the read-only memory device, the third output of the divider by eight is connected to the third input of the read-only memory and the second input of the pulse shaper, the first and second outputs two-digit accumulating adder connected to the corresponding inputs of the register, the first and second outputs of the register are connected to the third and fourth in the register odes and with the fourth and fifth inputs of the read-only memory, respectively, the third and fourth outputs of the register are connected to the sixth and seventh inputs of the read-only memory, respectively, the output of the pulse shaper is connected to the fifth input of the register and the eighth input of read-only memory, the output of the read-only memory is connected to the first input of the D-flip-flop, the second input of which is connected to the output of the reference frequency generator, and the output of the D-flip-flop is the output of the digital oraznostnogo manipulator.

Figure 1 shows a block diagram of a digital phase difference manipulator; figure 2 is a block diagram of a pulse shaper; figure 3 is a truth table (in hex code) of read-only memory; figure 4 - plot voltage, explaining the operation of the pulse shaper; figure 5 - plot of the voltage at the output of the digital phase-difference manipulator in the absence of a control pulse, with values of the absolute phase φ _{x of the} output oscillation equal to 0 °, 90 °, 180 ° and 270 °; 6 is a diagram of the voltage at the output of the digital phase-difference manipulator when changing the phase of the output oscillation from the phase φ _x equal to 0 °, to the phase φ _{x + 1} equal to 0 °, 270 °, 180 ° or 90 °; 7 is a diagram of the voltage at the output of a digital phase difference manipulator when changing the phase of the output oscillation from the phase φ _x equal to 270 °, to the phase φ _{x + 1} equal to 0 °, 270 °, 180 ° or 90 °; on Fig - plot voltage at the output of a digital phase difference manipulator when changing the phase of the output oscillation from the phase φ _x equal to 180 °, phase φ _{x + 1} equal to 0 °, 270 °, 180 ° or 90 °; figure 9 - plot of the voltage at the output of the digital phase difference manipulator when changing the phase of the output oscillation from the phase φ _x equal to 90 °, phase φ _{x + 1} equal to 0 °, 270 °, 180 ° or 90 °.

The digital phase difference manipulator comprises a reference frequency generator 1 and a divider 2 by eight, a D-trigger 3, a read-only memory 4, a two-bit accumulating adder 5, a pulse shaper 6 and a register 7, the first and second inputs of the two-bit accumulating adder 5 being the same information the inputs of the digital phase difference manipulator, the third input of the two-bit accumulating adder 5 and the first input of the pulse shaper 6 are combined and are the third (ticks) the first input of the digital phase difference manipulator, the first two outputs of the divider 2 by eight are connected to the corresponding inputs of the read-only memory 4, the third output of the divider 2 by eight is connected to the third input of the read-only memory 4 and the second input of the pulse shaper 6, the first and second outputs of the two-bit accumulating the adder 5 is connected to the corresponding inputs of the register 7, the first and second outputs of the register 7 are connected to the third and fourth inputs of the register 7 and with the fourth and fifth inputs are constant memory device 4, respectively, the third and fourth outputs of the register 7 are connected to the sixth and seventh inputs of the permanent memory 4, respectively, the output of the pulse shaper 6 is connected to the fifth input of the register 7 and the eighth input of the permanent memory 4, the output of the permanent memory 4 is connected to the first the input of the D-trigger 3, the second input of which is connected to the output of the generator 1 of the reference frequency, and the output of the D-trigger 3 is the output of the digital phase difference manipulator.

The pulse shaper 6 (see Fig. 2) contains a serial register 8, an inverter 9 and a coincidence circuit 10, the output of which is the output of the pulse shaper 6, the first and second inputs (data input and clock input, respectively) of the serial register 8 are the inputs of the shaper 6 of the same name pulse, the first output of the serial register 8 is connected to the first input of the matching circuit 10, the second output of the serial register 8 is connected to the input of the inverter 9, the output of which is connected to the second input of the matching circuit 10.

Digital phase difference manipulator operates as follows.

Consider the operation of a digital phase difference manipulator using the example of operation in the double relative phase manipulation mode.

The signal 8Fo from the output of the reference frequency generator 1 is fed to the counting input of the divider 2 by eight and to the counting input of the D-trigger 3. The divided signals 4Fo, 2Fo and Fo from the output of the divider 2 to eight are constantly fed to the first, second and third inputs of the permanent memory, respectively device 4, the first input being the least significant bit.

Information about the phase increment of the output signal (code 11 corresponds to a phase shift of + 90 °, code 10 to a phase shift of + 180 °, code 01 to a phase shift of + 270 °, code 00 to a phase shift of + 0 °) received at the input of the two-bit accumulating adder 5 is added to the accumulating adder 5 with its output and, on the trailing edge of the clock signal Ft, is written to the output of the accumulating adder 5. Thus, the output of the accumulating adder 5 produces a two-bit binary code of the absolute phase of the output signal: 00 - proportional to 0 ° , 01 - proportional 270 °, 10 - 180 ° proportional or 11 - 90 proportional °.

With the arrival of the leading edge of the clock signal Ft at the output of the pulse shaper 6, the signal Upr is generated by the signal Fo, the duration of which is equal to the period of the signal Fo, and its position is “tied” to the leading edge Fo (see figure 2, figure 4). On the leading edge of the signal Upr, the two-digit code of the absolute phase of the current information packet from the output of the accumulating adder 5 is written to the first and second outputs of the register 7, and the absolute phase code of the previous information packet is written to the third and fourth outputs of the register 7, respectively. During the action of the control signal at the output of the permanent storage device 4, a signal is generated with a gradual (without sharp changes in pulse duration) phase change in accordance with the phase codes of the previous and current information packets. The signal from the output of the read-only memory 4 is supplied through the D-trigger 3, with a shift of the signal 8Fo by one period, to the output of the digital phase difference manipulator (see Fig. 3, Fig.6 ... 9). Moreover, the output signal Fc is formed in such a way that during the phase change the duty cycle remains equal to two, and the duration of half-periods differs from the nominal value by no more than a quarter.

After the end of the control signal, when the transition to the current phase is completed, an Fc signal with an absolute phase of 0 °, 90 °, 180 ° or 270 ° is generated at the device output in accordance with the code recorded on the first and second outputs of register 7 (00, 11, 10 or 01, respectively) of the current absolute phase of the output signal (see figure 3, figure 5).

The operation of the digital phase difference manipulator in the single relative phase shift keying mode differs from the operation in the double relative phase shift keying mode only in that a logical zero is constantly supplied to the first (youngest) input of the accumulating adder 5. Moreover, the phase of the output signal Fc always has two values: 0 °, 180 ° or 90 °, 270 ° depending on the initial state of the first (lowest) output of the accumulating adder 5.

Thus, the use of this device in the transmitter as a modulator, connected, for example, in series with a key power amplifier with a transformer output and an oscillatory circuit in the load, will allow (due to the formation of a signal without a sharp change in the duration of the half-periods of the output signal at the time of the change of the oscillation phase) to be significantly reduce spurious amplitude and phase modulation of the output signal, voltage spikes at the output transistors and eliminate the possibility of the transmitter failing.

Information sources

1. Shlyapobersky V. I. Fundamentals of discrete message transmission technology. M., “Communication”, 1973, p. 228, Fig. 4.37.

2. Arrival A.M. Phase difference modulation and its application for transmitting discrete information. M., "Communication", 1967, p.62, Fig.2.6.

Claims (2)

1. A digital phase difference manipulator comprising a reference frequency generator and an eight divider connected in series, characterized in that it is additionally equipped with a D-trigger, read-only memory, a two-bit accumulating adder, a pulse shaper and a register, the first and second inputs of the two-bit accumulating adder being of the same name information inputs of a digital phase difference manipulator, the third input of a two-bit accumulating adder and the first input of the shaper pulses are combined and are the third input of the digital phase difference manipulator, the first two outputs of the eight divider are connected to the corresponding inputs of the read-only memory, the third output of the divider by eight is connected to the third input of the read-only memory and the second input of the pulse shaper, the first and second outputs of the two-bit accumulating adder are connected with the corresponding inputs of the register, the first and second outputs of the register are connected with the third and fourth inputs of the register and with four the fifth and fifth inputs of read-only memory, respectively, the third and fourth outputs of the register are connected to the sixth and seventh inputs of the read-only memory, respectively, the output of the pulse shaper is connected to the fifth input of the register and the eighth input of read-only memory, the output of the read-only memory is connected to the first input D- trigger, the second input of which is connected to the output of the reference frequency generator, and the output of the D-trigger is the output of a digital phase difference manipulator but. 2. The digital phase difference manipulator according to claim 1, characterized in that the pulse shaper is made on a serial register, inverter and match circuit, the output of which is the output of the pulse shaper, the first and second inputs of the serial register are the inputs of the pulse shaper of the same name, the first output of the serial register is connected with the first input of the matching circuit, the second output of the serial register is connected to the input of the inverter, the output of which is connected to the second input of the matching circuit.

Images