CN201690418U - Novel D-type power amplifier based on clock edge adjustment - Google Patents

Abstract

A novel D-type power amplifier based on clock edge adjustment relates to electronic technique and comprises an integrator, a PWM circuit and an output stage. An input end of the integrator is connected with a system input end while an output end is connected with a control end of the PWM circuit, an input end of the PWM circuit is connected with a clock signal, and an output end of the PWM circuit is fed back to the input end of the integrator via the output stage. The novel D-type power amplifier based on clock edge adjustment has the advantages that the power amplifier is simple in structure, high in interference resistant capacity and applicable to large-scale digital integration, and dose not need an internal oscillator to generate saw tooth wave or triangular wave.

Description

Novel D power-like amplifier based on the adjustment of clock edge

Technical field

The utility model relates to electronic technology, particularly integrated circuit technique.

Background technology

The D power-like amplifier also claims the PWM amplifier, can be used for amplifying audio signal.The D power-like amplifier comprises integrator and comparator usually, and the sawtooth waveforms of the output of integrator and oscillator output or triangular wave are relatively exported the PWM ripple.Traditional D power-like amplifier is owing to contain comparator and the oscillator of output sawtooth waveforms or triangular wave, and circuit is complicated and be subjected to noise jamming serious.When the output signal slope variation of integrator, the output of PWM ripple may be exported two pulses at one-period, produces the modulation mistake.

The utility model content

Technical problem to be solved in the utility model is, a kind of new D class A amplifier A is provided, and has stronger anti-interference.

The technical scheme that the utility model solve the technical problem employing is, novel D power-like amplifier based on the adjustment of clock edge, comprise integrator, pwm circuit and output stage, the input welding system input of integrator, the control end of output termination pwm circuit, the input termination clock signal of pwm circuit, the output of pwm circuit feeds back to the input of integrator by output stage.

The beneficial effects of the utility model are, and are simple in structure, and it is integrated to be fit to large scale digital, do not need internal oscillator to produce sawtooth waveforms or triangular wave, and antijamming capability is strong.

Below in conjunction with the drawings and specific embodiments the utility model is further described.

Description of drawings

Fig. 1 is the circuit diagram of prior art.

Fig. 2 is a circuit diagram of the present utility model.

Fig. 3 is pwm circuit figure of the present utility model.

Embodiment

Prior art such as Fig. 1, circuit is made of integrator, comparator 2 and output stage 3.Integrator is made of amplifier 1 and electric capacity 8.Electric capacity 8 connects the output and the reverse input end of amplifier 1.The reverse input end of amplifier 1 is exactly the input of integrator, and output is exactly the output of integrator.Integrator is received the input INPUT of system by a resistance 16.The reverse input end of comparator 2 is directly received the output of amplifier 1, the output of positive input connection oscillator 17.The input of output stage 3 connects the output of comparator 2, and output is the output OUTPUT of system.The output of system is connected to filter 4, and filter output is connected to load 5.Load 5 is generally loud speaker.The output OUTPUT of resistance 9 connected systems and the reverse input end of amplifier 1.

The voltage of the reverse input end of the duty ratio of OUTPUT output signal and comparator 2 is proportional.As voltage V of system input INPUT input _In, output signal that duty ratio is stable of system's output.The voltage of the reverse input end of this hint comparator 2 is stable, and the input current of integrator is zero, promptly

$\frac{V_{\mathrm{in}}}{R_{\mathrm{in}}}+\frac{V_{\mathrm{out}}}{R_f}=0$

System's output can be expressed as

$V_{\mathrm{out}}=-\frac{R_f}{R_{\mathrm{in}}}{V}_{\mathrm{in}}$

V wherein _OutBe the equivalent output voltage of system, V _InBe the output voltage of system, R _fBe the resistance value of feedback resistance 9, R _InResistance value for input resistance 16.

Structure of the present utility model such as Fig. 2, circuit is made of amplifier 1, pwm circuit 6 and output stage 3.The input INPUT of the system that is input as of amplifier 1, output meets the control end CTR of pwm circuit 6.The input of output stage 3 connects the output of pwm circuit 6, and output is the output OUTPUT of system.The output of system is connected to filter 4, and filter output is connected to load 5.Load 5 is generally loud speaker.A feedback branch is arranged between output OUTPUT of system and the integrator.For example, the reverse input end of the output OUTPUT of resistance 9 connected systems and amplifier 1.Amplifier circuit inserts an input resistance 16 between the reverse input end of amplifier 1 and system's input.Amplifier circuit inserts an electric capacity 8 between the reverse input end of amplifier 1 and output, amplifier 1 and electric capacity 8 constitute integrators.The reverse input end that is input as amplifier 1 of integrator, output are the output of amplifier 1, the external square-wave signal of the input of pwm circuit 6 (CLK).

Fig. 3 is a kind of specific implementation of pwm circuit.Pwm circuit 6 is made of voltage control edge delay circuit 69 and reverser.PMOS pipe 61,62 and NMOS pipe 63,64 constitute voltage control edge delay circuit 69.PMOS pipe 61,62 and NMOS pipe 63,64 are series between power supply and the ground successively.The grid of PMOS pipe 61 and NMOS pipe 64 meets voltage controling end CTR, and the grid of PMOS pipe 62 and NMOS pipe 63 meets input IN.The tie point of PMOS pipe 62 and NMOS pipe 63 is the output of voltage control edge delay circuit 69.The output of voltage control edge delay circuit 69 connects the input of inverter, and inverter is output as the output of pwm circuit 6.Pwm circuit 6 can have one or more circuits cascadings shown in Figure 3.

Pwm circuit 6 input duty cycles are 0.5 square wave, and CTR raises when control voltage, and the resistance of PMOS pipe 61 increases, and the resistance of NMOS pipe 64 reduces, and the output rate of climb of voltage control edge delay circuit 69 is slack-off, and decrease speed increases.Increase through the duty cycle square wave behind the inverter.When the reduction of control voltage, the duty ratio of output square wave reduces.

As voltage V of system input INPUT input _In, output signal that duty ratio is stable of system's output.The voltage of the output of integrator is stable at this moment, and the input current of integrator is zero, promptly

$\frac{V_{\mathrm{in}}}{R_{\mathrm{in}}}+\frac{V_{\mathrm{out}}}{R_f}=0$

System's output can be expressed as

$V_{\mathrm{out}}=-\frac{R_f}{R_{\mathrm{in}}}{V}_{\mathrm{in}}$

V wherein _OutBe the equivalent output voltage of system, V _InBe the output voltage of system, R _fBe the resistance value of feedback resistance 9, R _InResistance value for input resistance 16.

Claims (2)

1. the novel D power-like amplifier of adjusting based on the clock edge, it is characterized in that, comprise integrator, pwm circuit (6) and output stage (3), the input welding system input of integrator, the control end of output termination pwm circuit (6), the input termination clock signal of pwm circuit (6), the output of pwm circuit (6) feeds back to the input of integrator by output stage.

2. the novel D power-like amplifier of adjusting based on the clock edge as claimed in claim 1, it is characterized in that, described pwm circuit is made of metal-oxide-semiconductor (61～66), and PMOS pipe (61), (62) and NMOS pipe (63), (64) are series between power supply and the ground successively; The grid tie point of PMOS pipe (61) and NMOS pipe (64) is the voltage controling end of pwm circuit, and the grid tie point of PMOS pipe (62) and NMOS pipe (63) is the input of pwm circuit; The tie point of PMOS pipe (62) and NMOS pipe (63) connects the PMOS pipe (65) of series connection and the control end of NMOS pipe (66), and the tie point of PMOS pipe (65) and NMOS pipe (66) is the output of pwm circuit.

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