CN102522881B - Switching power supply sub-harmonic suppression circuit - Google Patents

Abstract

The invention discloses a switching power supply sub-harmonic suppression circuit, relating to the technology of integrated circuits. The switching power supply sub-harmonic suppression circuit comprises a clock generation circuit, a comparer, an RS trigger, a power MOSFET (metal-oxide -semiconductor field effect transistor) and a sampling resistor; the switch power supply sub-harmonic suppression circuit is characterized by further comprising a half-cycle circuit and a logic control circuit; the half-cycle circuit and an output end of the comparer are respectively connected to two input ends of the logic control circuit; and an output end of the logic control circuit is connected to a resetting end of the RS trigger. Through the switching power supply sub-harmonic suppression circuit, the application range of the system when the working voltage strongly fluctuates is improved.

Description

Switching Power Supply sub-harmonic suppression circuit

Technical field

The present invention relates to integrated circuit technique and circuit system technology, the secondary harmonic suppression circuit particularly driving for the constant current of type switching power.

Technical background

DC-DC Switching Power Supply adopts power semiconductor as switch, by the duty ratio of control switch, adjusts output voltage.Its control circuit topology is divided into current-mode and voltage mode, and Controlled in Current Mode and Based is widely used because dynamic response is fast, compensating circuit is simplified, gain bandwidth is large, outputting inductance is little and be easy to the advantages such as current-sharing.But Controlled in Current Mode and Based there will be subharmonic oscillation when duty ratio is greater than 0.5, many documents have carried out detailed analysis to this.Current measure is to adopt the vibration of the method harmonic carcellation of compensation.

Summary of the invention

Technical problem to be solved by this invention is that the Switching Power Supply sub-harmonic suppression circuit of the larger operating voltage fluctuation of a kind of adaptation is provided.

The technical scheme that the present invention solve the technical problem employing is, Switching Power Supply sub-harmonic suppression circuit, comprise clock generation circuit, comparator, rest-set flip-flop, power MOSFET, sampling resistor, clock generation circuit connects the S end of rest-set flip-flop, the negative input of comparator meets reference voltage REF, the positive input of comparator connects the source electrode of power MOSFET, the grid of the Q termination power MOSFET of rest-set flip-flop, the source electrode of power MOSFET is by sampling resistor ground connection, also comprise half period circuit and logic control circuit, the output of half period circuit and comparator is connected respectively to two inputs of logic control circuit, the output of logic control circuit is connected to the reset terminal of rest-set flip-flop, wherein, half period circuit is sent a pulse signal at 1/2 period position of clock generation circuit,

Further, half period circuit comprises the second current source, the second electric capacity and second clock comparator, clock generation circuit comprises the first current source, the first electric capacity and the first clock comparator, the first current source and the second Current-source matching, current value is identical, the first current source is by the first capacity earth, the second current source is by the second capacity earth, the capacitance of the first electric capacity is the twice of the second electric capacity, the tie point of the first current source and the first electric capacity is connected with the negative input end of the first clock comparator, the tie point of the second current source and the second electric capacity is connected with the negative input end of second clock comparator.

Or, half period circuit comprises the second current source, the second electric capacity and second clock comparator, clock generation circuit comprises the first current source, the first electric capacity and the first clock comparator, the current value of the first current source is 1/2 of the second current source, the first current source is by the first capacity earth, the second current source is by the second capacity earth, the capacitance of the first electric capacity is identical with the second electric capacity, the tie point of the first current source and the first electric capacity is connected with the negative input end of the first clock comparator, the tie point of the second current source and the second electric capacity is connected with the negative input end of second clock comparator.

The present invention has abandoned the scheme that adopts harmonic compensation in prior art, adopts logic control, forbids that the duty ratio of application circuit surpasses 0.5.The present invention has promoted system in the very large range of application of operating voltage fluctuation.Logic control technology of the present invention, is not affected by peripheral applications circuit.The present invention is very suitable for integrated circuit (IC) chip, is applied to the field that LED etc. needs constant current to control.

Below in conjunction with the drawings and specific embodiments, the present invention is further illustrated.

Accompanying drawing explanation

Fig. 1 is the typical structure schematic diagram of prior art.

Fig. 2 is implementation structure schematic diagram of the present invention.

Fig. 3 is the clock generation circuit of a kind of embodiment of the present invention and the circuit diagram of half period circuit.

Fig. 4 is the clock generation circuit of the second embodiment of the present invention and the circuit diagram of half period circuit.

Embodiment

Figure 1 shows that the typical circuit structure of prior art.Circuit consists of clock generation circuit 1, comparator 2, rest-set flip-flop 3, power MOSFET 6, sampling resistor Rsense4 and peripheral cell.The output of clock generation circuit 1 is connected to the set end S of rest-set flip-flop 3.The reset terminal R of rest-set flip-flop 3 is received in the output of comparator 2.What the negative input end of comparator 2 connected is reference voltage, and positive input terminal is connected with sampling resistor Rsense4.The conducting cut-off (concrete realization may be added driving stage betwixt) that rest-set flip-flop 3 output pwm control signals remove power ratio control MOSFET6.

Clock generation circuit 1 produces the pulse signal of fixed frequency, with the clock cycle T fixing _oscset rest-set flip-flop 3, makes rest-set flip-flop 3 produce high level signal and removes driving power MOSFET6.The electric current of inductance 7 starts to increase, and the voltage that forms the sampling resistor Rsense4 of series relationship with inductance 7 has reflected current value size.When sample rate current (voltage Vs) rises to reference threshold, the output switching activity of comparator 2 produces reset signal, makes rest-set flip-flop 3 be output as zero, thus switch-off power MOSFET6.By the time the next set pulse of clock generation circuit 1 is come, power MOSFET 6 conducting again.The state that starts to go round and begin again.

Figure 2 shows that implementation structure of the present invention.Circuit clock produces circuit 1, comparator 2, rest-set flip-flop 3, power MOSFET 6, sampling resistor Rsense4, half period generation circuit 9, half period comparator 9, logic control circuit 12 and peripheral cell and forms.Logic control circuit is or door.Than traditional circuit structure, the present invention has increased half period circuit 9 and logic control circuit 12.Half period circuit 9 is sent a pulse signal at 1/2 period position of complete period clock generation circuit 1, and through the judgement of logic control circuit 12, rest-set flip-flop 3 goes to reset.The possible operating state of major loop has two kinds:

Duty ratio D<0.5, comparator 2 can be prior to half period circuit reset rest-set flip-flop 3, and the reset of half period circuit is afterwards to repeat to reset;

Duty ratio D>0.5, the half period circuit rest-set flip-flop 3 that can reset when D=0.5, the reset of comparator 2 is afterwards to repeat to reset;

Therefore, half period circuit has guaranteed that the duty ratio D of whole system can not surpass 0.5.

Figure 3 shows that the specific implementation of half period circuit of the present invention.Two couplings, the first current source 13 that current value is identical and the second current source 14 are connected respectively to two couplings, and capacitance becomes the first electric capacity 15, the second electric capacity 16 of twice relation.The ramp voltage of the rising producing on the first electric capacity 15, the second electric capacity 16 is delivered to respectively the negative input end of the first clock comparator 17 and second clock comparator 18.Because the capacitance of the first electric capacity 15 is twices of the second electric capacity 16, according to the charging formula of electric capacity:

c-capacitance, Δ U-magnitude of voltage, I-charging current

$\mathrm{\&Delta;}{\mathrm{<figure-callout\; id="16"\; label="T"\; filenames="HDA0000118359620000021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{16}=C\frac{\mathrm{\&Delta;U}}{I};$

Clearly

ΔT ₁₆=0.5ΔT ₁₅

The in the situation that of identical charging current I, the voltage slope of the second electric capacity 16 is twices of the first electric capacity 15.Like this, when a half period of master clock, this half period circuit can be sent a reset pulse.That is, the reset pulse of this half period and master clock are quadratures.

System of the present invention can go out to produce a reset pulse or signal in the half period.Half period circuit 9 in Fig. 2 comprises ratio electric capacity or proportion current source and comparator circuit, and Fig. 3 is a kind of specific implementation wherein.

Different circuit also can be realized and the same function, and as the half period circuit of another specific implementation, as Fig. 4, the current value of the second current source is the twice of the first current source, and the capacitance of the first electric capacity equates with the second electric capacity,

c-capacitance, Δ U-magnitude of voltage, I-charging current

$\mathrm{\&Delta;}{\mathrm{<figure-callout\; id="16"\; label="T"\; filenames="HDA0000118359620000021.png"\; state="\{\{state\}\}">T</figure-callout>}}_{16}=C\frac{\mathrm{\&Delta;U}}{2I};$

Δ T clearly ₁₆=0.5 Δ T ₁₅.

Specification has absolutely proved principle of the present invention and necessary details, and those of ordinary skill can be implemented accordingly.Interest field of the present invention is not limited to previous embodiment.

Claims (2)

1. Switching Power Supply sub-harmonic suppression circuit, comprise clock generation circuit (1), comparator (2), rest-set flip-flop (3), power MOSFET (6), sampling resistor (4), clock generation circuit (1) connects the S end of rest-set flip-flop (3), the negative input of comparator (2) meets reference voltage REF, the positive input of comparator (2) connects the source electrode of power MOSFET (6), the grid of the Q termination power MOSFET (6) of rest-set flip-flop (3), the source electrode of power MOSFET (6) is by sampling resistor (4) ground connection, it is characterized in that, also comprise half period circuit (9) and logic control circuit (12), the output of half period circuit (9) and comparator (2) is connected respectively to two inputs of logic control circuit (12), the output of logic control circuit (12) is connected to the reset terminal of rest-set flip-flop (3), wherein, half period circuit (9) is sent a pulse signal at 1/2 period position of clock generation circuit (1),

Half period circuit (9) comprises the second current source (14), the second electric capacity (16) and second clock comparator (18), clock generation circuit (1) comprises the first current source (13), the first electric capacity (15) and the first clock comparator (17), the first current source (13) and the second current source (14) coupling, current value is identical, the first current source (13) is by the first electric capacity (15) ground connection, the second current source (14) is by the second electric capacity (16) ground connection, the capacitance of the first electric capacity (15) is the twice of the second electric capacity (16), the tie point of the first current source (13) and the first electric capacity (15) is connected with the negative input end of the first clock comparator (17), the tie point of the second current source (14) and the second electric capacity (16) is connected with the negative input end of second clock comparator (18).

2. Switching Power Supply sub-harmonic suppression circuit, comprise clock generation circuit (1), comparator (2), rest-set flip-flop (3), power MOSFET (6), sampling resistor (4), clock generation circuit (1) connects the S end of rest-set flip-flop (3), the negative input of comparator (2) meets reference voltage REF, the positive input of comparator (2) connects the source electrode of power MOSFET (6), the grid of the Q termination power MOSFET (6) of rest-set flip-flop (3), the source electrode of power MOSFET (6) is by sampling resistor (4) ground connection, it is characterized in that, also comprise half period circuit (9) and logic control circuit (12), the output of half period circuit (9) and comparator (2) is connected respectively to two inputs of logic control circuit (12), the output of logic control circuit (12) is connected to the reset terminal of rest-set flip-flop (3), wherein, half period circuit (9) is sent a pulse signal at 1/2 period position of clock generation circuit (1),

Half period circuit (9) comprises the second current source (14), the second electric capacity (16) and second clock comparator (18), clock generation circuit (1) comprises the first current source (13), the first electric capacity (15) and the first clock comparator (17), the current value of the first current source (13) is 1/2 of the second current source (14), the first current source (13) is by the first electric capacity (15) ground connection, the second current source (14) is by the second electric capacity (16) ground connection, the capacitance of the first electric capacity (15) is identical with the second electric capacity (16), the tie point of the first current source (13) and the first electric capacity (15) is connected with the negative input end of the first clock comparator (17), the tie point of the second current source (14) and the second electric capacity (16) is connected with the negative input end of second clock comparator (18).

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