CN101924075B - Flash memory manufacturing method - Google Patents
Flash memory manufacturing method Download PDFInfo
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- CN101924075B CN101924075B CN200910052805XA CN200910052805A CN101924075B CN 101924075 B CN101924075 B CN 101924075B CN 200910052805X A CN200910052805X A CN 200910052805XA CN 200910052805 A CN200910052805 A CN 200910052805A CN 101924075 B CN101924075 B CN 101924075B
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- flash memory
- ion
- memory manufacturing
- bit line
- injection
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Abstract
The invention provides a flash memory manufacturing method which comprises the following steps: providing a structure comprising a semiconductor substrate, an insulating medium layer, a polycrystalline silicon layer, a silicon nitride layer and an oxide layer side wall; carrying out first type ion implantation on the structure, and forming a plurality of bit lines corresponding to each groove; carrying out annealing treatment on the structure; and arranging isolated bit lines at the interval of a preset number of bit lines, wherein the isolated bit line is formed by carrying out second type ion implantation on the bit line after the first type ion implantation. The flash memory manufacturing method provided by the invention can achieve the effect identical with the effect achieved by shallow trench isolation, and can not generate mechanical stress simultaneously.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, relate in particular to a kind of manufacturing approach of flash memory.
Background technology
Flash memory is one type of nonvolatile memory, even still can the retention tab internal information after power supply is closed, but in system's electric erasable and overprogram process, need not apply special high voltage, has the characteristics that cost is low, density is big in addition.Its particular performances makes it apply to every field widely; Comprise embedded system; Like PC and peripheral hardware, telecommunications switch, cell phone, network interconnection device, instrument and meter and automobile device; Also comprise emerging voice, image, storage series products simultaneously, like digital camera, digital recorder and personal digital assistant.
Along with reducing of integrated circuit size, the device of forming circuit must be placed more thick and fast, to adapt to the confined space available on the chip.Because present research is devoted to increase the density of active device on the unit are of Semiconductor substrate, becomes more important so the effective insulation between circuit is isolated.
Shallow trench isolation has multinomial technology and electrical isolation advantage from (STI) technology, comprises and can reduce the integrated level that the area that takies crystal column surface increases device simultaneously, keeps surface flatness and less channel width erosion etc.Yet when device size constantly dwindled, needing the mechanical stress between control device was the key point that guarantees device high-performance and high reliability.And in the present technology, shallow trench isolation is from being easy to cause mechanical stress to produce.
Shown in Figure 1 is the design drawing of NROMTM type flash chip, and shown in Figure 2 is the circuit domain of this chip.As shown in the figure, be arranged with a plurality of active elements (memory cell) on this NROMTM type flash chip, wherein each memory cell all is used to store data, a shared bit lines between the consecutive storage unit.Because a large amount of memory cell is through after the operation of a very long time; There is the electronics of storing in the individual memory cell can move in the polysilicon substrate; The data that cause storing in the memory cell are made mistakes; Being difficult to find error unit when breaking down, usually a plurality of memory cell on the chip being divided into groups according to predetermined quantity, is one group like 16～50 memory cell; Be to be one group with 33 memory cell shown in the figure, the position that in 33 unit of every group, is positioned at two ends then is provided with 2 fault detection unit (ED cells) 11,12.These 2 fault detection unit can be carried out obtaining data behind the specific algorithm operating to the unit that programming in the memory cell that they were responsible for write data and are recorded in 11,12 li of fault detection unit; When the data that data that after system discovery carries out the special algorithm operation once more, obtain and fault detection unit are 11,12 li are unequal; System carries out the anti-operation of special algorithm; Made mistakes and calculate the data of storing in which memory cell, replaced with the data correction in the memory cell of mistake or with the memory cell of other positions by system control error correction unit again.So said fault detection unit 11,12 is more important than general memory cell.
In order to reduce a side adjacent interference of fault detection unit; Prior art adopts the virtual ground of shallow trench isolation (STI) 10 partly to isolate per 33 memory cell; Please refer to Fig. 2, comprise AA layer (active layer) 13 among Fig. 2, WL layer (word line layer) 14 and BL layer (bit line layer) 15.Use STI isolation can make near the substrate at STI edge because a large amount of negative stress (being pressure) of the reason of silica generation causes the mobility step-down near the substrate electron of STI, and just do not have stress influence away from the substrate of STI.Yet flash memory is controlled electronics just and is come work, thus near the unit of STI because mobility is low, what the electric current during work can be than away from STI is low, program capability is also low.Under the identical operations condition, can't be near near the memory cell the STI as operate as normal away from the memory cell of STI, thus cause chip to be difficult to carry out programming operation, reduced the performance of chip.
Summary of the invention
The present invention proposes a kind of flash memory manufacturing method, can reach the same effect of using shallow trench isolation, also can not produce mechanical stress simultaneously.
In order to achieve the above object, the present invention proposes a kind of flash memory manufacturing method, comprises the following steps:
Provide one comprise Semiconductor substrate, insulating medium layer, polysilicon layer, silicon nitride layer and oxide layer side wall structure; Said insulating medium layer, polysilicon layer, silicon nitride layer are formed on the Semiconductor substrate successively and wherein offer several grooves, and said oxide layer side wall covers on the surface of side, bottom surface and silicon nitride layer of groove;
Said structure is carried out first kind ion inject, corresponding each groove forms a bit lines;
Said structure is carried out annealing in process;
Every interval predetermined quantity bit lines is provided with one and isolates bit line, and said isolation bit line forms through the bit line that carried out the injection of first kind ion is carried out the injection of the second type ion.
Optional, the material of said insulating medium layer is silica, silica-silicon nitride or silica-silicon-nitride and silicon oxide.
Optional, the material of said oxide layer side wall is a silica.
Optional, the step that bit line is isolated in said formation comprises:
On the structure after first time ion injection and the annealing, form one deck photoresistance;
Through exposure and development, remove corresponding to the photoresistance of isolating the bit line position and form opening;
Utilize photoresistance as mask, carry out the second type ion at opening part and inject formation isolation bit line.
Optional, the width of said opening is 100nm～500nm.
Optional, every interval 16～50 bit lines are provided with one and isolate bit line.
Optional, said first kind ion is a N type ion, the second type ion is a P type ion.
Optional, the said second type ion injects and comprises that carrying out boron fluoride ion or the injection of boron ion and indium ion successively injects.
Optional, the injection energy that said boron fluoride ion injects is 110Kev～130Kev.
Optional, the injection rate that said boron fluoride ion injects is 8E+13 atoms/cm
2～4E+14atoms/cm
2
Optional, the injection energy that said boron ion injects is 75Kev～90Kev.
Optional, the injection rate that said boron ion injects is 9E+12 atoms/cm
2～3E+13 atoms/cm
2
Optional, the injection energy that said indium ion injects is 40Kev～80Kev.
Optional, the injection rate that said indium ion injects is 8E+15 atoms/cm
2～1.5E+16 atoms/cm
2
The flash memory manufacturing method that the present invention proposes; The isolation bit line that adopts the second type ion to inject is isolated the predetermined quantity bar and is injected the common bit line that forms through first kind ion; Injected dissimilar ions owing to isolate bit line and common bit line; Therefore it can reach and use shallow trench isolation to solve the identical effect of adjacent interference, also can not produce mechanical stress simultaneously.Adopt the photoresistance of 100nm～500nm opening lower when bit line is isolated in formation as mask, inject the formed isolation bit line of boron fluoride ion and indium ion in two steps respectively simultaneously and have the good isolation effect for equipment requirements.
Description of drawings
Shown in Figure 1 is the design drawing of prior art NROMTM type flash chip.
Shown in Figure 2 is the circuit domain of chip shown in Figure 1.
Shown in Figure 3 is the formation method flow diagram of the flash memory of preferred embodiment of the present invention.
Shown in Figure 4 is the circuit domain of the flash memory of preferred embodiment of the present invention.
Fig. 5～shown in Figure 8 isolates the structural representation of bit line for the formation of the flash memory of preferred embodiment of the present invention.
Embodiment
In order more to understand technology contents of the present invention, special act specific embodiment also cooperates institute's accompanying drawing explanation as follows.
Core concept of the present invention is; Based on the existing storage organization of flash memory, inject through dissimilar ions, between group that constitutes by predetermined quantity (16～50) memory cell and group, form bit line with isolation effect; Thereby replace isolation structure of shallow trench used in the prior art; When reaching use shallow trench isolation solution adjacent interference same effect, also can avoid the generation of mechanical stress, improved the performance of flash memory thus.
The present invention proposes a kind of flash memory manufacturing method, can reach the same effect of using shallow trench isolation, also can not produce mechanical stress simultaneously.
Please refer to Fig. 3, shown in Figure 3 is the formation method flow diagram of the flash memory of preferred embodiment of the present invention.The present invention proposes a kind of flash memory formation method, comprises the following steps:
Step S10: provide one comprise Semiconductor substrate, insulating medium layer, polysilicon layer, silicon nitride layer and oxide layer side wall structure; Wherein, Said insulating medium layer, polysilicon layer, silicon nitride layer are formed on the Semiconductor substrate successively and wherein offer several grooves, and said oxide layer side wall covers on the surface of side, bottom surface and silicon nitride layer of groove;
Step S20: said structure is carried out first kind ion inject, corresponding each groove forms a bit lines;
Step S30: said structure is carried out annealing in process;
Step S40: every interval predetermined quantity bit lines is provided with one and isolates bit line, and said isolation bit line forms through the bit line that carried out the injection of first kind ion is carried out the injection of the second type ion.
Wherein, first kind ion is a N type ion, and the second type ion is a P type ion.
Please refer to Fig. 4 again, shown in Figure 4 is the circuit domain of the flash memory of preferred embodiment of the present invention.Comprising WL layer (word line layer) on the AA layer (active layer) 130 140 and BL layer (bit line layer) 150; The processing of the flash memory formation method of process preferred embodiment of the present invention; Have between a plurality of active elements and isolate the shallow trench isolation (STI) that bit line 100 substitutes prior art; The quantity of said a plurality of active elements is decided according to the needs of technological design, for example in certain concrete application, is 16-55.
Please refer to Fig. 5～Fig. 8 again, Fig. 5～shown in Figure 8 is the structural representation of the formation bit line of the flash memory of preferred embodiment of the present invention.The preferred embodiment according to the present invention; The step that on Semiconductor substrate, forms a plurality of bit lines comprises: with reference to figure 5; At first on Semiconductor substrate 200, form insulating medium layer 210; The material of said insulating medium layer 210 is silica, silica-silicon nitride or silica-silicon-nitride and silicon oxide (ONO layer), is silica-silicon-nitride and silicon oxide layer shown in the accompanying drawing; And then on insulating medium layer 210, form polysilicon layer 220; And on polysilicon layer 220, form silicon nitride layer 230; Please refer to Fig. 6～Fig. 8 again, Fig. 6～Fig. 8 is the part-structure sketch map.On silicon nitride layer, form one deck photoresistance; Utilizing the bit line light shield that photoresistance is carried out exposure imaging, the photoresistance that form the bit line position is removed, subsequently, is mask with the photoresistance pattern, and etching is not formed groove by the silicon nitride layer 230 that photoresistance covers until exposing Semiconductor substrate 200, please refer to Fig. 6; Remove photoresistance and on silicon nitride layer 230 and the sidewall of groove and bottom formation oxide layer side wall 240, the material of said oxide layer side wall 240 is a silica, please refer to Fig. 7.
With the said structure is mask, in Semiconductor substrate, carries out the ion injection first time, and corresponding each groove forms a bit lines, then said structure is carried out annealing in process.
Then; Need every interval predetermined quantity bit lines (can be 16～50, is 33 in the preferred embodiment of the present invention) to form one and isolate bit line, its processing step is following: at first form one deck photoresistance 110 on the device architecture surface; Utilize isolation bit line light shield to make public, develop then; To remove the photoresistance of isolating the bit line correspondence position, form opening, the width of opening is 100nm～500nm; See Fig. 8, then utilize photoresistance 110 as mask the carrying out of opening portion proceed the second type ion on the bit line that injects of first kind ion and inject to form and isolate bit line.The second type ion injects and comprises that carrying out boron fluoride ion or the injection of boron ion and indium ion successively injects; Wherein the injection energy of boron fluoride ion injection is 110Kev～130Kev, and the injection rate that the boron fluoride ion injects is 8E+13 atoms/cm2～4E+14 atoms/cm2.If adopt the boron ion to inject, then its injection energy is 75Kev～90Kev, and the injection rate that the boron ion injects is 9E+12 atoms/cm2～3E+13atoms/cm2.The injection energy that indium ion injects is 40Kev～80Kev, and the injection rate that indium ion injects is 8E+15 atoms/cm2～1.5E+16 atoms/cm2.Remove photoresistance 110 afterwards, and carry out the completion bit line and isolate the subsequent operation that forms flash memory afterwards.Isolate the degree of depth of bit line P type when injecting the P type doping depth that forms and reaching original STI and isolate; Form together divider wall completely; And the width of isolating bit line equates with the width of bit line, does not influence contiguous bit line, therefore can isolate in order to replace original STI fully.
Divide 2 steps inject different ions be because the P type of hoping to form isolate can be as STI divider wall, certain degree of depth (2000 dusts～3500 dusts) is arranged, and needs to offset original bit line N type doping.It is to isolate in order to form the simple degree of depth that the first road boron fluoride ion or boron ion adopt the injection of low dosage high-energy, and it is that substrate surface counteracting N type bit line mixes and formation P type is isolated in order to rest on that the second road indium ion adopts the low-yield injection of high dose.Only inject and be difficult to then to reach simultaneously that the degree of depth is isolated and with the effect of the assorted disastrously transoid of bit line, therefore in preferred embodiment of the present invention, adopted the processing method of dividing 2 steps injection different ions with one ion.
In sum; The flash memory manufacturing method that the present invention proposes; The isolation bit line that adopts the second type ion to inject is isolated first kind ion and is injected the predetermined quantity memory cell on the bit line that forms; Have dissimilar ions with bit line and inject owing to isolate bit line, so it can reach and use shallow trench isolation solution adjacent interference same effect, also can not produce mechanical stress simultaneously.The photoresistance of employing 100nm～500nm opening forms when isolating bit line lower for equipment requirements, injects the formed isolation bit line of boron fluoride ion and indium ion in two steps respectively simultaneously and has the good isolation effect.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (14)
1. a flash memory manufacturing method is characterized in that, comprises the following steps:
Provide one comprise Semiconductor substrate, insulating medium layer, polysilicon layer, silicon nitride layer and oxide layer side wall structure; Said insulating medium layer, polysilicon layer, silicon nitride layer are formed on the Semiconductor substrate successively and said insulating medium layer, polysilicon layer, silicon nitride layer in offer several grooves; Said groove exposes the surface of said Semiconductor substrate, and said oxide layer side wall covers on the surface of side, bottom surface and silicon nitride layer of groove;
With the said structure is mask, in Semiconductor substrate, carries out first kind ion and injects, and corresponding each groove forms a bit lines;
Said structure is carried out annealing in process;
Every interval predetermined quantity bit lines is provided with one and isolates bit line, and said isolation bit line forms through the bit line that carried out the injection of first kind ion is carried out the injection of the second type ion.
2. flash memory manufacturing method according to claim 1 is characterized in that, the material of said insulating medium layer is silica, silica-silicon nitride or silica-silicon-nitride and silicon oxide.
3. flash memory manufacturing method according to claim 1 is characterized in that, the material of said oxide layer side wall is a silica.
4. flash memory manufacturing method according to claim 1 is characterized in that, the step that bit line is isolated in said formation comprises:
On the structure after first time ion injection and the annealing, form one deck photoresistance;
Through exposure and development, remove corresponding to the photoresistance of isolating the bit line position and form opening;
Utilize photoresistance as mask, carry out the second type ion at opening part and inject formation isolation bit line.
5. flash memory manufacturing method according to claim 4 is characterized in that, the width of said opening is 100nm～500nm.
6. flash memory manufacturing method according to claim 1 is characterized in that, every interval 16～50 bit lines are provided with one and isolate bit line.
7. flash memory manufacturing method according to claim 1 is characterized in that, said first kind ion is a N type ion, and the second type ion is a P type ion.
8. flash memory manufacturing method according to claim 1 is characterized in that, the said second type ion injects and comprises that carrying out boron fluoride ion or the injection of boron ion and indium ion successively injects.
9. flash memory manufacturing method according to claim 8 is characterized in that, the injection energy that said boron fluoride ion injects is 110Kev～130Kev.
10. flash memory manufacturing method according to claim 8 is characterized in that, the injection rate that said boron fluoride ion injects is 8E+13atoms/cm
2～4E+14atoms/cm
2
11. flash memory manufacturing method according to claim 8 is characterized in that, the injection energy that said boron ion injects is 75Kev～90Kev.
12. flash memory manufacturing method according to claim 8 is characterized in that, the injection rate that said boron ion injects is 9E+12atoms/cm
2～3E+13atoms/cm
2
13. flash memory manufacturing method according to claim 8 is characterized in that, the injection energy that said indium ion injects is 40Kev～80Kev.
14. flash memory manufacturing method according to claim 8 is characterized in that, the injection rate that said indium ion injects is 8E+15atoms/cm
2～1.5E+16atoms/cm
2
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| CN200910052805XA CN101924075B (en) | 2009-06-09 | 2009-06-09 | Flash memory manufacturing method |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6670246B1 (en) * | 2002-12-17 | 2003-12-30 | Nanya Technology Corporation | Method for forming a vertical nitride read-only memory |
| CN100463146C (en) * | 2005-03-14 | 2009-02-18 | 海力士半导体有限公司 | Method for manufacturing semiconductor device with recess channels and asymmetrical junctions |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6670246B1 (en) * | 2002-12-17 | 2003-12-30 | Nanya Technology Corporation | Method for forming a vertical nitride read-only memory |
| CN100463146C (en) * | 2005-03-14 | 2009-02-18 | 海力士半导体有限公司 | Method for manufacturing semiconductor device with recess channels and asymmetrical junctions |
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