CN116825822A

CN116825822A - Semiconductor structure and preparation method thereof

Info

Publication number: CN116825822A
Application number: CN202310781326.1A
Authority: CN
Inventors: 李泽伦
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-06-28
Filing date: 2023-06-28
Publication date: 2023-09-29

Abstract

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: a substrate; two transistors in the substrate and arranged in sequence along a first direction; the grid electrode of one transistor is connected with the drain electrode of the other transistor, the channel of one transistor is U-shaped, and the channel of the other transistor extends along the second direction. The first direction intersects with the second direction, and the second direction is the thickness direction of the substrate.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure and a method of fabricating the same.

Background

A conventional memory cell of a dynamic random access memory (Dynamic Random Access Memory, DRAM) includes a Transistor (Transistor) and a Capacitor (Capacitor), i.e., a 1T1C structure, wherein the Capacitor is responsible for storing data information. As the integration density of DRAM is advancing toward higher, it is necessary to prepare a capacitor having a larger capacitance value per unit area, and thus, the capacitor limits the progress of memory advancing toward integration.

It has been found that the gate in the transistor is able to accommodate a small amount of charge, so a 2T0C structure appears that includes two transistors and has no capacitor, with the gate of one of the two transistors replacing the memory function of the capacitor in the memory cell. However, the current 2T0C structure has a larger size, which results in a lower integration level of the semiconductor memory.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same.

In a first aspect, embodiments of the present disclosure provide a semiconductor structure, comprising:

a substrate;

two transistors in the substrate and arranged in sequence along a first direction; the grid electrode of one transistor is connected with the drain electrode of the other transistor, the channel of one transistor is U-shaped, and the channel of the other transistor extends along the second direction;

the first direction intersects the second direction, and the second direction is a thickness direction of the substrate.

In some embodiments, the two transistors include a first transistor and a second transistor; wherein the first transistor includes: a U-shaped first channel and a first grid electrode positioned on the surface of the first channel; the second transistor includes: a second channel extending in the second direction and a second drain electrode at one end of the second channel; the first gate is connected with the second drain.

In some embodiments, the first transistor further comprises: the first source electrode and the first drain electrode are positioned at two ends of the U-shaped opening of the first channel; the second transistor further includes: a second source and a second gate; the second source electrode and the second drain electrode are respectively positioned at two ends of the second channel, and the second grid electrode covers the second channel; and the projection parts of the second drain electrode and the first drain electrode on the plane of the substrate are overlapped.

In some embodiments, the semiconductor structure further comprises: a dielectric layer;

the dielectric layer is positioned between the first grid electrode and the second grid electrode, and the material of the dielectric layer comprises a low dielectric constant material;

an isolation layer;

the isolation layer is located at least between the first transistor and the second transistor.

In some embodiments, the two transistors include a first transistor and a second transistor; wherein the first transistor includes: a U-shaped first channel and a first drain; the second transistor includes: a second channel extending in the second direction and a second gate on a surface of the second channel; the first drain electrode is connected with the second grid electrode.

In some embodiments, the first transistor further comprises: a first source and a first gate; the first source electrode and the first drain electrode are respectively positioned at two ends of the U-shaped opening of the first channel, and the first grid electrode is positioned on the surface of the first channel;

the second transistor further includes: a second source electrode and a second drain electrode; the second source electrode and the second drain electrode are respectively positioned at two ends of the second channel.

In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:

Providing a substrate;

forming two transistors sequentially arranged along a first direction in the substrate; the grid electrode of one transistor is connected with the drain electrode of the other transistor, the channel of one transistor is U-shaped, and the channel of the other transistor extends along the second direction;

In some embodiments, the two transistors comprise a first transistor and a second transistor, wherein a first channel of the first transistor is U-shaped, a second channel of the second transistor extends in the second direction, and a first gate of the first transistor is connected to a second drain of the second transistor;

forming, in the substrate, the two transistors sequentially arranged in the first direction, including:

etching the substrate to form a first groove and a second groove which are arranged at intervals along the first direction, and an active column positioned between the first groove and the second groove;

forming the first transistor in the first trench, the second trench, and the surface of the active pillar; wherein the first channel of the U shape covers the active column;

Forming the second transistor at least in the remaining second trenches.

In some embodiments, forming the first transistor in the first trench, the second trench, and a surface of the active pillar includes:

forming a first semiconductor layer at the bottom of the first trench, the bottom of the second trench and the surface of the active column; wherein the first semiconductor layer covering the active column forms the first channel of U shape; the first semiconductor layer positioned at the bottom of the first groove forms a first source electrode; the first semiconductor layer positioned at the bottom of the second groove forms a first drain electrode;

and forming the first grid electrode on the surface of the first channel.

In some embodiments, forming the second transistor at least in the remaining second trenches includes:

forming an isolation layer on the surface of the first semiconductor layer at the bottom of the second groove;

forming a second semiconductor layer on the surface of the isolation layer, the side wall of the second groove and the surface of the substrate; the second semiconductor layer located on the surface of the isolation layer forms the second drain electrode of the second transistor, the second semiconductor layer located on the surface of the substrate forms the second source electrode of the second transistor, and the second semiconductor layer located on the side wall of the second groove forms the second channel;

And forming a second grid electrode on the surface of the second channel.

In some embodiments, after forming the second semiconductor layer and before forming the second gate, the method further comprises:

forming a dielectric layer in the remaining second grooves; the material of the dielectric layer comprises a low dielectric constant material.

In some embodiments, the two transistors include a first transistor and a second transistor, wherein a first channel of the first transistor is U-shaped and a second channel of the second transistor extends in the second direction; the first drain electrode of the first transistor is connected with the second gate electrode of the second transistor;

etching the substrate to form a third groove and a fourth groove which are arranged at intervals along the first direction;

forming the first transistor in the third trench;

the second transistor is formed in the fourth trench.

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: a substrate; two transistors in the substrate and arranged in sequence along a first direction; the grid electrode of one transistor is connected with the drain electrode of the other transistor, the channel of one transistor is U-shaped, and the channel of the other transistor extends along the second direction; the first direction intersects with the second direction, and the second direction is the thickness direction of the substrate. Because in the semiconductor structure of the embodiment of the disclosure, the channel of one transistor of the two transistors sequentially arranged along the first direction is U-shaped, and the channel of the other transistor extends along the second direction (i.e., vertically extends), compared with the transistor with a planar channel, the size of the U-shaped channel and the vertical channel in the horizontal direction can be reduced under the same control capability, so that the area of the formed semiconductor structure is effectively reduced, the integration level can be improved, and the miniaturization is realized.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1 to 6 are schematic structural views of a semiconductor structure according to an embodiment of the disclosure;

fig. 7 is an equivalent circuit diagram of a semiconductor structure provided in an embodiment of the present disclosure;

fig. 8 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 9 to 21 are schematic structural diagrams during the manufacturing process of the semiconductor structure according to the embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the related art, two transistors in the 2T0C semiconductor structure are generally two planar transistors, that is, the channel of the transistor is a planar channel, and since the two planar transistors occupy a larger area of a horizontal plane, the semiconductor structure is difficult to achieve size miniaturization, so that the improvement of the integration level is limited. In addition, the distance between the two transistors is relatively short, which is prone to coupling, resulting in reduced performance of the semiconductor device.

Based on this, the embodiment of the disclosure provides a semiconductor structure and a method for manufacturing the same, in the semiconductor structure of the embodiment of the disclosure, two transistors are sequentially arranged along an X-axis direction, where a channel of one transistor is U-shaped, and a channel of the other transistor extends (i.e., vertically extends) along a Y-axis direction.

Hereinafter, a semiconductor structure and a method for manufacturing the same in embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Before describing embodiments of the present disclosure, two directions describing semiconductor structures that may be used in the following embodiments are defined, and may include X-axis and Y-axis directions, for example, in a cartesian coordinate system. Two directions intersecting each other (e.g., perpendicular to each other) are defined as a first direction and a second direction, and for example, a thickness direction of the substrate may be defined as a second direction. The first direction may be, for example, an X-axis direction, and the second direction may be, for example, a Y-axis direction.

An embodiment of the present disclosure provides a semiconductor structure, please refer to fig. 1 to 6, and fig. 1 to 6 show schematic structural diagrams of the semiconductor structure provided by the embodiment of the present disclosure. As shown in fig. 1 to 6, the semiconductor structure includes:

a substrate 200;

two transistors located in the substrate 200 and arranged in sequence along the X-axis direction; the grid electrode of one transistor is connected with the drain electrode of the other transistor, the channel of one transistor is U-shaped, and the channel of the other transistor extends along the Y-axis direction.

In the semiconductor structure in the embodiment of the disclosure, the gate of one transistor is connected with the drain of the other transistor to form a 2T0C structure. One of the two transistors serves as a read transistor and the other serves as a write transistor, wherein the gate of the read transistor is connected to the drain of the write transistor.

In the embodiment of the disclosure, the channel of one transistor is in a U shape, and the channel of the other transistor extends along the Y axis direction (i.e., vertically extends), and compared with the transistors with planar channels, the U-shaped channel and the vertical channel can both be reduced in size in the horizontal direction under the same control capability, so that the area of the formed semiconductor structure is effectively reduced, the integration level can be improved, and the miniaturization is realized.

In the embodiment of the disclosure, when the two transistors occupy the same dimension in the horizontal direction, the channel length of the two transistors can be longer than that of the transistors with planar channels, so that the control capability of the transistors is stronger.

In some embodiments, substrate 200 includes, for example, but is not limited to, an elemental semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium substrate, etc.), or a silicon-on-insulator substrate, a germanium-on-insulator substrate, etc.

In some embodiments, referring to fig. 1 and 2, the two transistors include a first transistor and a second transistor; wherein the first transistor includes: a U-shaped first channel 211 and a first gate 212 positioned on the surface of the first channel 211; the second transistor includes: a second channel 221 extending in the Y-axis direction and a second drain 222 located at one end of the second channel 221; the first gate 212 is connected to the second drain 222.

In the disclosed embodiment, the first gate 212 of the first transistor is connected to the second drain 222 of the second transistor, i.e., the first transistor acts as a read transistor and the second transistor acts as a write transistor.

In some embodiments, referring to fig. 1 and 2, the first transistor further includes: a first source 213 and a first drain 214 located at both ends of the U-shaped opening of the first channel 211; the second transistor further includes: a second source 223 and a second gate 224; wherein the second source 223 and the second drain 222 are respectively located at two ends of the second channel 221, and the second gate 224 covers the second channel 221; the projection portions of the second drain electrode 222 and the first drain electrode 214 on the plane of the substrate 200 overlap.

In some embodiments, referring to fig. 2, the U-shaped opening of the first channel 211 faces away from the substrate 200, the first drain 214 is located on the surface of the substrate 200, and the projection portions of the second drain 222 and the first drain 214 on the plane of the substrate 200 overlap, so that the space between the first transistor and the second transistor can be reduced, and thus the area of the semiconductor structure can be reduced.

In some embodiments, referring to fig. 1, the U-shaped opening of the first channel 211 faces the substrate 200, the first drain 214 is located in the substrate 200, the projections of the second drain 222 and the first drain 214 on the plane of the substrate 200 may coincide, specifically, the projection of the second drain 222 on the plane of the substrate 200 is completely located in the projection of the first drain 214 on the plane of the substrate 200, so that the space between the first transistor and the second transistor may be further reduced, and the area of the semiconductor structure may be further reduced.

In the embodiment of the disclosure, the first channel 211, the first source 213 and the first drain 214 may be integrally formed, and the second channel 221, the second drain 222 and the second source 223 may be integrally formed, so that the actual manufacturing process may be simplified. The materials of the first channel 211, the first source 213 and the first drain 214, and the second channel 221, the second drain 222 and the second source 223 may include, but are not limited to, indium gallium zinc oxide, indium tin oxide, gallium oxide, indium oxide, silicon or silicon germanium, etc.

In some embodiments, the materials of the first channel 211, the first source 213 and the first drain 214, and the second channel 221, the second drain 222 and the second source 223 are all indium gallium zinc oxide. First, the indium gallium zinc oxide has a high carrier mobility, so that the sensitivity of the first transistor 21 and the second transistor 22 can be improved, and the power consumption of the semiconductor device can be reduced. And secondly, the indium gallium zinc oxide also has higher off-state current, so that the gate induced drain leakage current of the semiconductor structure can be reduced, and the performance of the semiconductor structure is improved. In addition, the indium gallium zinc oxide has better fluidity, and can grow on any needed interface, so that the preparation difficulty of the semiconductor structure can be reduced.

In the embodiment of the present disclosure, the first source 213 and the first drain 214 may be connected to corresponding read bit lines and read word lines, respectively, through different conductive plugs. For example, in an actual process, connection holes exposing the first source electrode 213 and the first drain electrode 214 may be formed in the substrate 200, and then a conductive material may be filled in the connection holes to form conductive plugs.

In other embodiments, the conductive plugs connected to the first source 213 and the first drain 214 may be used as the first source and the first drain of the first transistor.

In some embodiments, with continued reference to fig. 1 and 2, the first gate 212 includes a first gate dielectric layer 215 and a first gate conductive layer 216 that sequentially cover the first channel 211, and the second gate 224 includes a second gate dielectric layer 225 and a second gate conductive layer 226 that sequentially cover the second channel 221. The materials of the first gate dielectric layer 215 and the second gate dielectric layer 225 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like. The material of the first gate conductive layer 216 and the second gate conductive layer 226 may be any material with good conductivity, for example, any one or a combination of a plurality of titanium, titanium nitride, tungsten, cobalt, platinum, palladium, ruthenium, copper, and polysilicon.

It is noted that the connection of the first gate 212 and the second drain 222 means: the first gate conductive layer 216 in the first gate 212 is connected to the second drain 222.

In some embodiments, referring to fig. 1, the semiconductor structure further includes: a dielectric layer 23; dielectric layer 23 is located between first gate 212 and second gate 224, and the material of dielectric layer 23 comprises a low dielectric constant material.

In embodiments of the present disclosure, the material of dielectric layer 23 includes a low-k material, such as a low-k dielectric material having a dielectric constant (k value) less than about 3.0, less than about 2.5, or less, including but not limited to silicon oxide, carbon-based materials, hydrogen Silsesquioxane (HSQ), methyl Silsesquioxane (MSQ), or other silicon-based polymer materials, and the like. The dielectric layer 23 may improve parasitic capacitance, reduce a coupling effect between the first transistor and the second transistor, and thus improve performance of the semiconductor structure.

Note that referring to fig. 2, since the first gate 212 and the second gate 224 are separated from each other by the substrate 200 and the second channel 221 in the semiconductor structure shown in fig. 2, the semiconductor structure in fig. 2 may not have the dielectric layer 23 between the first gate 212 and the second gate 224.

In some embodiments, referring to fig. 1, the semiconductor structure further includes: an isolation layer 24; the isolation layer 24 is located at least between the first transistor and the second transistor.

In the embodiment of the present disclosure, the isolation layer is located between the second drain 222 and the first drain 214, and above the first source 213. The isolation layer may realize insulation isolation between the second drain electrode 222 and the first drain electrode 214 on the one hand, and protect materials of the second drain electrode 222, the first drain electrode 214 and the first source electrode 213 on the other hand. The material of the isolation layer may include, but is not limited to, an oxide or nitrogen-containing material, such as silicon oxide, silicon nitride, or silicon carbide nitride, etc. When the materials of the second drain electrode 222, the first drain electrode 214 and the first source electrode 213 are indium gallium zinc oxide, the material of the isolation layer may include a nitrogen-containing material. Because the InGaZn oxide is exposed to the water and oxygen in the air, the performance degradation is easy to cause, and the nitrogen-containing material can provide better barrier effect so as to avoid the influence on the performance of the semiconductor structure due to the degradation of the InGaZn oxide.

It should be noted that, in the semiconductor structure shown in fig. 2, the second drain electrode 222 is located inside the substrate 200, and the first drain electrode 214 is located on the surface of the substrate 200, and the two are separated by the substrate 200, so that the semiconductor structure in fig. 2 may not provide the isolation layer 24 between the second drain electrode 222 and the first drain electrode 214, and only provide the isolation layer 24 on the surface of the first channel 211 to protect the material of the first channel 211.

It should be further noted that, with continued reference to fig. 1 and 2, in the semiconductor structure shown in fig. 1 and 2, the second gate 224 is located on a side of the second channel 221 away from the first gate 212, so that a distance between the first gate 212 and the second gate 224 is larger, which can reduce a coupling effect between the first transistor and the second transistor.

In some embodiments, referring to fig. 3 and 4, the second gate 224 may also be located on a side of the second channel 221 adjacent to the first gate 212.

In the disclosed embodiment, the first gate 212 and the second gate 224 are separated by a dielectric layer 23 as shown in fig. 3, and the first gate 212 and the second gate 224 are separated by the substrate 200 as shown in fig. 4. Here, both the dielectric layer 23 and the substrate 200 may reduce the coupling effect between the first transistor and the second transistor. Accordingly, the second gate electrode 224 is disposed on the side of the second channel 221 close to the first gate electrode 212 on the premise that the coupling effect between the first transistor and the second transistor can be reduced, and further reduction of the occupied area of the semiconductor structure can be achieved.

In some embodiments, referring to fig. 5 and 6, two transistors include a first transistor and a second transistor; wherein the first transistor includes: a U-shaped first channel 211 and a first drain 214; the second transistor includes: a second channel 221 extending in the Y-axis direction and a second gate 224 located on a surface of the second channel 221; the first drain 214 is connected to the second gate 224.

In the disclosed embodiment, the first drain 214 of the first transistor is connected to the second gate 224 of the second transistor, i.e., the first transistor acts as a write transistor and the second transistor acts as a read transistor.

In some embodiments, referring to fig. 5 and 6, the first transistor further includes: a first source 213 and a first gate 212; the first source 213 and the first drain 214 are respectively located at two ends of the U-shaped opening of the first channel 211, and the first gate 212 is located on the surface of the first channel 211; the second transistor further includes: a second source electrode 223 and a second drain electrode 222; wherein the second source 223 and the second drain 222 are respectively located at both ends of the second channel 221.

In the embodiment of the present disclosure, the materials of the structures of the portions of the first transistor and the second transistor may be understood with reference to the first transistor and the second transistor described above, and will not be described herein again.

In some embodiments, referring to fig. 5, the U-shaped opening of the first channel 211 faces away from the substrate 200; the first gate 212 and the second gate 224 are separated by the substrate 200 and the first channel 211, which may reduce a coupling effect between the first transistor and the second transistor.

In some embodiments, referring to fig. 6, the U-shaped opening of the first channel 211 faces the substrate 200; a dielectric layer 23 is provided between the first gate 212 and the second gate 224.

The dielectric layer 23 in the embodiments of the present disclosure may be used to isolate the first gate 212 and the second gate 224, thereby improving parasitic capacitance and reducing coupling effects between the first transistor and the second transistor.

In some embodiments, the material of dielectric layer 23 may include a low dielectric constant material, such as a low k dielectric material having a dielectric constant (k value) less than about 3.0, less than about 2.5, or less, including but not limited to silicon oxide, carbon-based materials, hydrogen Silsesquioxane (HSQ), methyl Silsesquioxane (MSQ), or other silicon-based polymer materials, and the like. When the material of the dielectric layer 23 is a low dielectric constant material, the parasitic capacitance can be further improved, and the coupling effect between the first transistor and the second transistor can be reduced, thereby improving the performance of the semiconductor structure.

In the embodiment of the disclosure, a 2T0C structure formed by combining such an arch shape (corresponding to the first transistor including the U-shaped first channel 211 described above) with a vertical shape (corresponding to the second transistor including the second channel 221 described above) is formed, and such an arch shape can avoid the problem that planar transistors are not arranged in a planar arrangement, and can increase the channel area at the same time; the vertical transistor has the same effect, and the whole structure can solve the problem of size shrinkage and increase the integration level.

Fig. 7 is an equivalent circuit diagram of a semiconductor structure provided in an embodiment of the present disclosure, as shown in fig. 7, the semiconductor structure includes a Write transistor 11 and a Read transistor 12, a control terminal of the Write transistor 11 is connected to a Write Word Line (WWL), a source (or drain) of the Write transistor 11 is connected to a Write Bit Line (WBL), a drain (or source) of the Write transistor 11 is connected to a control terminal of the Read transistor 12 through a Storage Node contact (SN), and a source and a drain of the Read transistor 12 are connected to a Read Bit Line (Read Bit-Line, RBL) and a Read Word Line (Read Word-Line, RWL), respectively.

Next, an operation principle of the semiconductor structure (2 t0c DRAM memory cell) provided by the embodiment of the present disclosure is described with reference to fig. 7.

In the process of writing "1", a positive voltage is applied to the write word line terminal, and the positive voltage needs to be greater than the threshold voltage of the write transistor 11, so that the write transistor 11 is turned on, and charges are injected into the gate capacitance of the read transistor 12 at the write bit line terminal positive voltage. The gate voltage and the drain voltage of the write transistor 11 are removed after the charge injection, and the "1" state is preserved.

In the process of reading 1, a reading voltage is applied to the end of the reading bit line, and as a certain charge exists in the gate capacitance of the reading transistor 12, the reading transistor 12 is in a lower resistance state, a larger current is obtained, and the process of reading 1 is completed after the peripheral circuit is amplified and identified.

In the process of writing "0", a positive voltage is applied to the write word line end, and the positive voltage needs to be greater than the threshold voltage of the write transistor 11, so that the write transistor 11 is turned on, and a negative voltage is applied to the write bit line end to extract charges from the gate capacitance of the read transistor 12. The gate voltage and the drain voltage of the write transistor 11 are removed after the charge extraction, and the "0" state is held.

In the process of reading 0, a reading voltage is applied to the end of the reading bit line, and as no charge exists in the gate capacitance of the reading transistor 12, the reading transistor 12 is in a higher resistance state, so that smaller current is obtained, and the process of reading 0 is completed after the peripheral circuit is amplified and identified.

Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, fig. 8 is a flowchart of the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, and fig. 9 to 21 are schematic structural diagrams of the semiconductor structure in the manufacturing process provided by the embodiment of the present disclosure. The method for manufacturing the semiconductor structure according to the embodiments of the present disclosure will be described in detail with reference to fig. 8 to 21.

As shown in fig. 9 to 21, the method for manufacturing the semiconductor structure includes steps 101 and 102:

first, referring to fig. 9, step 101 is performed to provide a substrate 200.

Next, referring to fig. 10 to 21, step 102 is performed, in which two transistors sequentially arranged in the X-axis direction are formed in the substrate 200; the grid electrode of one transistor is connected with the drain electrode of the other transistor, the channel of one transistor is U-shaped, and the channel of the other transistor extends along the Y-axis direction.

In the two transistors formed by the embodiment of the disclosure, the channel of one transistor is in a U shape, and the channel of the other transistor extends along the Y-axis direction (i.e., vertically extends), compared with the transistors with planar channels, the U-shaped channel and the vertical channel can be reduced in size in the horizontal direction under the same control capability, so that the area of the formed semiconductor structure is effectively reduced, the integration level is improved, and the miniaturization is realized.

In the embodiment of the disclosure, when the two transistors formed occupy the same dimension in the horizontal direction, the channel length of the two transistors can be longer than that of the transistor with the planar channel, so that the control capability of the transistors is stronger.

In some embodiments, referring to fig. 16, the two transistors include a first transistor and a second transistor, wherein a first channel 211 of the first transistor is U-shaped, a second channel 221 of the second transistor extends along the Y-axis direction, and a first gate 212 of the first transistor is connected to a second drain 222 of the second transistor.

In some embodiments, referring to fig. 10 to 16, step 102 may be implemented by:

first, referring to fig. 10, the etching substrate 200 forms first trenches 25 and second trenches 26 arranged at intervals in the X-axis direction, and active pillars 27 between the first trenches 25 and the second trenches 26.

In some embodiments, forming the first trenches 25 and the second trenches 26 may be formed using an anisotropic etching process, such as a plasma etching process.

Next, referring to fig. 11, a first transistor is formed in the first trench 25, the second trench 26, and the surface of the active pillar 27; wherein the first channel 211 of the U-shape covers the active pillars 27.

Specifically, please continue with reference to fig. 11, forming the first transistor includes:

a first semiconductor layer 28 as shown in fig. 11 is formed at the bottom of the first trench 25, the bottom of the second trench 26, and the surface of the active column 27; wherein the first semiconductor layer 28 covering the active pillars 27 constitutes a first channel 211 of a U-shape; the first semiconductor layer 28 located at the bottom of the first trench 25 constitutes a first source electrode 213; the first semiconductor layer 28 at the bottom of the second trench 26 constitutes the first drain electrode 214.

In some embodiments, the first semiconductor layer 28 may be formed using one or more of physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes, wherein the material of the first semiconductor layer 28 may include, but is not limited to, indium gallium zinc oxide, indium tin oxide, gallium oxide, indium oxide, silicon germanium, or the like.

In some embodiments, the material of the first semiconductor layer 28 is indium gallium zinc oxide. First, the indium gallium zinc oxide has a high carrier mobility, so that the sensitivity of the first transistor 21 can be improved, and the power consumption of the semiconductor device can be reduced. And secondly, the indium gallium zinc oxide also has higher off-state current, so that the gate induced drain leakage current of the semiconductor structure can be reduced, and the performance of the semiconductor structure is improved. In addition, the indium gallium zinc oxide has better fluidity, and can grow on any needed interface, so that the preparation difficulty of the semiconductor structure can be reduced.

A first gate 212 as shown in fig. 11 is formed on the surface of the first channel 211.

In implementation, referring to fig. 11, a first gate dielectric layer 215 and a first gate conductive layer 216 are formed to cover the surface of the first channel 211 in sequence, and the first gate dielectric layer 215 and the first gate conductive layer 216 form the first gate 212.

In the embodiment of the present disclosure, the first gate dielectric layer 215 and the first gate conductive layer 216 may be formed by one or more of physical vapor deposition, chemical vapor deposition, or atomic layer deposition; the material of the first gate dielectric layer 215 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like. The material of the first gate conductive layer 216 may be any material with good conductivity, for example, any one or more of titanium, titanium nitride, tungsten, cobalt, platinum, palladium, ruthenium, copper, and polysilicon.

The first channel 211, the first source 213, the first drain 214, and the first gate 212 in the embodiment of the present disclosure constitute a first transistor.

Next, referring to fig. 12 to 16, a second transistor is formed at least in the remaining second trench 26.

Specifically, please continue with reference to fig. 12, forming the second transistor includes:

an isolation layer 24 as shown in fig. 12 is formed on the surface of the first semiconductor layer 28 at the bottom of the second trench 26.

In some embodiments, isolation layer 24 may be formed using one or more of physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes, wherein the material of isolation layer 24 may include, but is not limited to, an oxide or nitride, or the like. Here, the isolation layer 24 may realize insulation isolation between the first drain electrode 214 and a second drain electrode formed later on, on the one hand, and may protect the material of the covered first semiconductor layer 28, on the other hand. The material of isolation layer 24 may include, but is not limited to, an oxide or nitrogen-containing material, such as silicon oxide, silicon nitride, or silicon carbide nitride, etc. When the material of the first semiconductor layer 28 is indium gallium zinc oxide, the material of the isolation layer 24 may include a nitrogen-containing material. Since the indium gallium zinc oxide is exposed to the water oxygen of the air, performance degradation is easily caused, and the nitrogen-containing material can provide better barrier effect so as to avoid the influence on the performance of the semiconductor structure due to the degradation of the indium gallium zinc oxide.

In some embodiments, referring to fig. 12, a second isolation layer 241 is formed in the remaining first trench 25 as shown in fig. 12.

In the embodiment of the disclosure, the process of forming the second isolation layer 241 may be understood by referring to the formation of the isolation layer 24 in the above embodiment, and will not be described herein. The second isolation layer 241 may protect the material of the first semiconductor layer 28 that it covers.

Forming a second semiconductor layer 29 as shown in fig. 13 on the surface of the isolation layer 24, the sidewalls of the second trench 26, and the surface of the substrate 200; the second semiconductor layer 29 on the surface of the isolation layer 24 forms a second drain 222 of the second transistor 22, the second semiconductor layer 29 on the surface of the substrate 200 forms a second source 223 of the second transistor 22, and the second semiconductor layer 29 on the sidewall of the second trench 26 forms a second channel 221.

In the embodiment of the present disclosure, the process of forming the second semiconductor layer 29 may be understood with reference to the above-mentioned process of forming the first semiconductor layer 28, and will not be described herein. The material of the second semiconductor layer 29 may include, but is not limited to, indium gallium zinc oxide, indium tin oxide, gallium oxide, indium oxide, silicon germanium, or the like.

In some embodiments, the material of both the first semiconductor layer 28 and the second semiconductor layer 29 is indium gallium zinc oxide.

In some embodiments, referring to fig. 14, after forming the second semiconductor layer 29, the method for preparing the semiconductor structure further includes: forming a dielectric layer 23 in the remaining second trenches 26; the material of the dielectric layer 23 includes a low dielectric constant material.

A second gate electrode 224 as shown in fig. 16 is formed on the surface of the second channel 221.

Specifically, first, a fifth trench 251 adjacent to the second trench 26 as shown in fig. 15 is formed; next, a second gate dielectric layer 225 and a second gate conductive layer 226 are formed in the fifth trench 251 to cover the surface of the second channel 221 in this order as shown in fig. 16; a third semiconductor layer 291 is then formed over the second gate dielectric layer 225 and the second gate conductive layer 226.

In the disclosed embodiment, the dielectric layer 23 is first formed in the remaining second trench 26, and then the second gate 224 is formed. It is to be understood that, in some other embodiments, the second gate 224 may be formed first, and then the dielectric layer 23 may be formed in the remaining second trench 26, where the processes of forming the second gate 224 and forming the dielectric layer 23 may be understood with reference to the corresponding processes in the foregoing embodiments, which are not repeated herein.

In the embodiment of the present disclosure, the second gate dielectric layer 225 and the second gate conductive layer 226 constitute the second gate electrode 224. The process of forming the second gate dielectric layer 225 and the second gate conductive layer 226 may be understood with reference to the process of forming the first gate dielectric layer 215 and the first gate conductive layer 216, and the process of forming the third semiconductor layer 291 may be understood with reference to the process of forming the first semiconductor layer 28, which will not be described herein.

The second channel 221, the second drain 222, the second source 223, and the second gate 224 in the embodiment of the present disclosure constitute a second transistor.

It should be noted that, the semiconductor structure formed in the embodiment of the present disclosure is similar to the semiconductor structure shown in fig. 1 in the above embodiment, and for the technical features that are not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and the description is omitted here.

It should be further noted that the process of forming the semiconductor structure shown in fig. 2 to 4 can be understood by referring to the process in the above embodiment, and will not be repeated here.

In some embodiments, please refer to fig. 21, the two transistors include a first transistor 21 and a second transistor 22, wherein a first channel 211 of the first transistor 21 is U-shaped, and a second channel 221 of the second transistor 22 extends along the Y-axis direction; the first drain 214 of the first transistor 21 is connected to the second gate 224 of the second transistor 22.

In some embodiments, referring to fig. 17 to 21, step 102 may be further implemented by:

referring to fig. 17, the etching substrate 200 forms third trenches 30 and fourth trenches 31 arranged at intervals in the X-axis direction.

In some embodiments, the third trenches 30 and the fourth trenches 31 may be formed using dry etching, such as plasma etching.

Next, referring to fig. 18, a first transistor is formed in the third trench 30.

Specifically, forming the first transistor includes:

forming a first semiconductor layer 28 as shown in fig. 18 on the inner wall of the third trench 30 and the surface of the substrate 200; wherein the first semiconductor layer 28 covering the inner wall of the third trench 30 forms a first channel 211, and the first semiconductor layer covering the surface of the substrate 200 forms a first source 213 and a first drain 214, respectively;

A first gate 212 as shown in fig. 18 is formed on the surface of the first channel 211, wherein the first gate 212 includes a first gate dielectric layer 215 and a first gate conductive layer 216.

In some embodiments, after forming the first gate 212, a third isolation layer 242 is formed as shown in fig. 19 filling the remaining third trench 30 and covering the first gate 212 and the first semiconductor layer 28.

In the embodiment of the disclosure, the processes of forming the first semiconductor layer 28, forming the first gate electrode 212 and forming the third isolation layer 242 may be respectively understood with reference to the processes of forming the first semiconductor layer 28, forming the first gate electrode 212 and forming the isolation layer 24 in the above embodiment, and will not be described herein.

In the embodiment of the present disclosure, the first channel 211, the first source 213, the first drain 214, and the first gate 212 constitute a first transistor.

Next, referring to fig. 20 and 21, a second transistor is formed in the fourth trench 31.

Specifically, forming the second transistor includes:

forming a second gate 224 as shown in fig. 20 on a sidewall of the fourth trench 31; wherein the second gate 224 includes a second gate dielectric layer 225 and a second gate conductive layer 226.

Forming a second semiconductor layer 29 as shown in fig. 20 at the bottom of the fourth trench 31 and the surface of the second gate electrode 224, wherein the second semiconductor layer 29 covering the bottom of the fourth trench 31 constitutes a second drain electrode 222, and the second semiconductor layer 29 covering the surface of the second gate electrode 224 constitutes a second channel 221;

A polysilicon layer (not shown) is formed in the remaining fourth trench 31, the polysilicon layer is subjected to a high-temperature heat treatment to form a single crystal silicon layer 201 as shown in fig. 21, and a fourth isolation layer 243 and a semiconductor layer as shown in fig. 21 are sequentially formed over the single crystal silicon layer 201, wherein the semiconductor layer constitutes a second source electrode 223 as shown in fig. 21.

In embodiments of the present disclosure, the polysilicon layer may be formed by one or more of physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes. The processes of forming the second gate electrode 224, forming the second semiconductor layer 29, and forming the semiconductor layer and the fourth isolation layer 243 may be understood with reference to the processes of forming the second gate electrode 224, forming the second semiconductor layer 29, and forming the isolation layer 24 in the above embodiments, respectively, and will not be described herein.

In the embodiment of the present disclosure, the second channel 221, the second drain 222, the second source 223, and the second gate 224 constitute a second transistor.

It should be noted that, the semiconductor structure formed in the embodiment of the present disclosure is similar to the semiconductor structure shown in fig. 5 in the above embodiment, and for the technical features that are not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and the description is omitted here.

It should be further noted that the process of forming the semiconductor structure shown in fig. 6 may be understood with reference to the process in the above embodiment, and will not be described herein.

In several embodiments provided by the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

Features disclosed in the several method or structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.

The above is merely some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present disclosure, and should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, comprising:

a substrate;

2. The semiconductor structure of claim 1, wherein the two transistors comprise a first transistor and a second transistor;

wherein the first transistor includes: a U-shaped first channel and a first grid electrode positioned on the surface of the first channel; the second transistor includes: a second channel extending in the second direction and a second drain electrode at one end of the second channel; the first gate is connected with the second drain.

3. The semiconductor structure of claim 2, wherein the first transistor further comprises: the first source electrode and the first drain electrode are positioned at two ends of the U-shaped opening of the first channel;

the second transistor further includes: a second source and a second gate; the second source electrode and the second drain electrode are respectively positioned at two ends of the second channel, and the second grid electrode covers the second channel;

The projection part of the second drain electrode and the projection part of the first drain electrode on the plane of the substrate are overlapped;

the semiconductor structure further includes: a dielectric layer;

an isolation layer;

4. The semiconductor structure of claim 1, wherein the two transistors comprise a first transistor and a second transistor;

wherein the first transistor includes: a U-shaped first channel and a first drain; the second transistor includes: a second channel extending in the second direction and a second gate on a surface of the second channel; the first drain electrode is connected with the second grid electrode.

5. The semiconductor structure of claim 4, wherein the first transistor further comprises: a first source and a first gate; the first source electrode and the first drain electrode are respectively positioned at two ends of the U-shaped opening of the first channel, and the first grid electrode is positioned on the surface of the first channel;

6. A method of fabricating a semiconductor structure, the method comprising:

providing a substrate;

7. The method of claim 6, wherein the two transistors comprise a first transistor and a second transistor, wherein a first channel of the first transistor is U-shaped, a second channel of the second transistor extends in the second direction, and a first gate of the first transistor is connected to a second drain of the second transistor;

forming the second transistor at least in the remaining second trenches.

8. The method of claim 7, wherein forming the first transistor in the first trench, the second trench, and a surface of the active pillar comprises:

and forming the first grid electrode on the surface of the first channel.

9. The method of claim 8, wherein forming the second transistor at least in the remaining second trenches comprises:

forming a dielectric layer in the remaining second grooves; the material of the dielectric layer comprises a low dielectric constant material;

and forming a second grid electrode on the surface of the second channel.

10. The method of claim 6, wherein the two transistors comprise a first transistor and a second transistor, wherein a first channel of the first transistor is U-shaped and a second channel of the second transistor extends in the second direction; the first drain electrode of the first transistor is connected with the second gate electrode of the second transistor;

Forming the first transistor in the third trench;

the second transistor is formed in the fourth trench.