CN101897095A - 用于保护高速接口的阻抗补偿esd电路及使用其的方法 - Google Patents

用于保护高速接口的阻抗补偿esd电路及使用其的方法 Download PDF

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CN101897095A
CN101897095A CN2008801204600A CN200880120460A CN101897095A CN 101897095 A CN101897095 A CN 101897095A CN 2008801204600 A CN2008801204600 A CN 2008801204600A CN 200880120460 A CN200880120460 A CN 200880120460A CN 101897095 A CN101897095 A CN 101897095A
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esd
pcb
inductance
parasitism
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J·C·邓尼胡
R·基蒙托
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Semiconductor Components Industries LLC
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California Micro Devices Corp
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Abstract

本文描述的设备和方法的实施例提供一种集成的ESD/EOS保护方案，其简化用于信号完整一致性的系统PCB设计。作为提供该方案的一部分，其也期望实现改进的ESD/EOS保护以及改进的PCB布线。

Description

用于保护高速接口的阻抗补偿ESD电路及使用其的方法
本发明要求享有2007年12月11日提交的美国临时申请NO.61/007,298，名称为“Impedance Compensated ESD Protection For High-Speed Interfaces”的优先权，该申请特别地通过引用并入本文。
技术领域
本发明涉及一种用于保护高速接口的阻抗补偿ESD电路及使用其的方法。
背景技术
许多公司目前都有配置有多个高速I/O界面的电子系统处于开发中。这些系统和接口必须满足多个工业标准信号完整规范，例如，以HDMI标准为例，有HDMI一致性规范。此外，还有工业广泛的ESD/EOS(电过载)耐久等级。许多这些系统的目标信号完整需求确保系统可通过BERT测试、眼图波罩或被动式TDR传输线分析的互操作性。
图1示出了执行ESD/EOS保护的传统系统的一个简化的例子。注意，下面示出的系统可使用典型的分路型ESD钳位或串联型ESD保护，其中信号从一侧进入并从另一侧几何相同地出去。这些高速应用的目的是包括ESD保护而不沿着从连接器(P1)至接收机或发射机ASIC(DUP)的传输线插入明显的阻抗不连续。
传统系统具有保护下的器件(DUP)和测试下的器件(DUT)，其中具有ESD产品使DUT与DUP并联的“分路机构”。在具有二极管的传统ESD结构中，一端连接到信号线且另一端接地。所以，在这样的结构中，该ESD二极管总是与DUP并联。在这些现有器件中，例如来自CMD的CM1213，DUT的串联寄生电阻和电感工作为排斥从DUP引走ESD电流，且并联寄生电容在感兴趣的频段中产生阻抗不连续。
在传统的DUT中，芯片键合线和其它寄生电感在高频和快速脉冲边缘率(fast pulse edge rates)(即，在ESD事件中)时表现出高阻抗。从DUP中引走的电流量被键合线和这些寄生元件所阻碍。结果，DUP仍在很大程度上直接暴露于ESD的威胁下，如下所示。
在波段中，ESD钳位电路的寄生电容性负载，此处示为C(PAR)可降低从连接器至ASIC(DUP)的位于ESD DUT附近的传输线的阻抗。为抵消这个，标准做法是调整(典型地为增加)在DUT附近的传输线的特征阻抗以抵消(典型地为降低)这个ESD DUT布置的阻抗不连续。
发明内容
本发明的一个目的是提供一种集成的ESD/EOS保护的解决方案，其简化用于信号的完整一致性的系统PCB设计。
作为提供该解决方案的一部分，也期望实现改进的ESD/EOS保护和改进的PCB布线。
附图说明
本发明的这些和其它方面和特征，在下面结合附图参考描述的本发明的具体实施例的基础上，将为本领域普通技术人员所知，其中：
图1示出传统的并联ESD连接；
图2示出一种根据本发明的实施例的串联ESD连接；
图3a-b分别示出一种传统的ESD下方连接和一种根据本发明的穿通ESD连接；
图4示出一种本发明使用二极管的具体实施。
图5示出一种根据本发明的差分对实施。
图6示出了频谱图，其示出根据本发明的流通(flow-through)方式的优势。
图7示出一种根据本发明使用图4的电路的具体实施。
具体实施方式
在根据本发明的系统中，如图2所示，DUT与DUP串联。结果，ESD事件在到达DUP之前必须经过DUT。进一步，寄生串联电感和电阻与DUT一起工作，以减小进入DUP的电流。
由此“流通”拓扑，可在感兴趣的频段下在ESD DUT封装中完全地执行上述的预补偿，这样减小系统PCB中的“调节”(tuning)的需要。这有利于PCB设计的简化和上市时间的减少。尽管DUP和EMI滤波器件的串联是公知的，但该EMI滤波器件用于在高频区域过滤掉不需要的信号。相反，采用本发明的DUT，高频信号无衰变地通过。
根据本发明的DUT，如图2中所示的信号通道执行，可更普通地描述为并入如下所示的串联“T-网络”中的分路型ESD钳位。为了术语的清楚，双向I/O线朝向连接器被标识为“OUT”(出)，并且朝向ASIC(DUP)被标识为“IN”(入)。这种“单端”钳位的物理实现如图3b所示，其中，如所示，不允许信号从ESD器件下通过(如图3a所示)而是信号穿过ESD器件，如所示，信号PCB迹线不是单线。如所示，结果，在ESD器件的任一侧上的键合线自身为“L(PAR)”，如上面的图所示。
此外，通过集成这些级到单个封装中，相比于由离散的元件实现的相似的解决方案，可获得许多改进。第一个优点是由于处理和其它变化，一个通道和另一个通道之间的差异可紧密地匹配。这最小化了不匹配表现到解决方案中导致的负面影响，其中信号的完整性是重要的。例如，具有最小化的不匹配的两个通道可形成差分对，如图5所示。更低的不匹配将减小由DUT表现的信号偏斜和反射。另一个优点是相比于离散的解决方案，可减少板空间和由此的成本。
在如图2所示的单通道实现中，半导体封装的寄生电感可用于该串联元件，与设计到半导体晶片电路中的其他元件结合。在一个实施例中，根据本发明的“ESD钳位结构”是ESD二极管，如图4所示，在一个构造中有8条不同的线允许用于ESD保护。
采用如上所示的该专用集成电路ESD器件，结合用作如前所述的寄生电感器的键合线，本发明工作为一个钳位结构，但是其具有如前所述的构造的PCB迹线、键合线和这里所示的ESD二极管。串联元件也可为电感器、变压器、共模滤波器或甚至为用于AC耦合带通滤波器的电容器+电感器组合。这里注意，对于这里描述的实施例，封装的串联电感寄生占主导，虽然这样占主导的电感寄生一般是不期望的(因为这些成为不需要的封装毁损)，但是这些占主导的电感寄生这里可有利地使用。这样，如果一个大电感器集成到芯片上，那么，占主导的电感寄生将变得可忽略，并实际将减少封装尺寸和成本。下述实现可提供改进的阻抗匹配，并在同一封装中达到增强共模EMI抑制和滤波。
本发明的多个方面包括串联元件、流通布线和分布式的ESD级的使用。
对于串联元件，电感在高频和快速脉冲边缘率(ESD事件)时表现高阻抗，限制到DUP的电流和电压，以及电阻在高电流时降低或削弱高电压，减小在DUP处观察到的电压。在正常操作中的低信号电流，电阻在通带中造成一些信号削弱，减小可获得的信号，但是在接口器件恢复敏感度或传输等级要求的可接受等级内，这样整个系统仍然满足信号完整的要求。
对于流通布线，封装键合线不阻碍ESD保护，而是有助于ESD保护。具体来说，封装键合线可用于(如图3B所示)调节传输线的阻抗(即消除ESD级电容的影响)，这通过使DUT对分布式的ESD级(多级)更透明，而改进了信号完整性。具体来说，基于上述的流通方式，对于PCB迹线，本发明使用一种相比于传统不同的方式。具体来说，不像传统做法那样具有物理地经过ESD器件的下方(且与ESD器件电并联)的PCB迹线，在本发明中PCB迹线不经过ESD器件的下方，而是因此在PCB迹线上的信号需经过ESD器件。这个方法这样布置键合线电感与迹线串联，且串联电感用于取消不期望的电容并由此拓宽信号通带的频谱。这可从图6所示的频谱图看出。在此例中，带宽从2.7Ghz(传统的分路型结构)拓宽到4.2Ghz(新的流通结构)。进一步，通道到通道的信号的变化被最小化。如图7所示，其为示出用于在图4的视图中所示的8条不同线的键合线连接的物理级别上的具体实施例，虽然具有通道到通道的阻抗变化，但这些是对称的，因此，虽然中间的对比外部的对将具有稍微不同的阻抗，但该差异可被预先确定、最小化且容易特征化。
更进一步，当各种连接被用于驱动差分信号，键合线的长度(即电感)相互匹配是重要的，以便于最小化任何对内偏斜。此外，最小化不同对之间的偏斜是重要的。因此，如果出现若干信号对，可以期望在一个封装中具有若干小片，如图7所示。进一步，注意，从通道到通道，键合线的串联电感以及因此的在寄生电感之间的差异与键合线的长度的差异成比例。
采用此构造，各通道的差分阻抗是相同的。
虽然参考本发明的实施例具体地描述了本发明，但本领域技术人员将容易地知晓本发明的形式和细节中的各种改变、修正和替代，并不背离发明的精神和范围。因此，可理解，在许多情况下将使用本发明的一些特征，而不相应地使用其它特征。进一步，本领域技术人员将明白，可对上面所述的图中的元件的数量和布置做改变。所附的权利要求的范围意在包括这样的改变和修正。

Claims (10)

1.一种用于传输信号和放电与ESD事件相关联的ESD事件脉冲至地以保护处于保护下的器件的系统，所述系统包括：
印刷电路板，其具有传输信号的PCB迹线，所述PCB迹线由相互电隔离的第一线部分和第二线部分形成；以及
静电放电保护器件，其安装在所述印刷电路板上以保护该处于保护下的器件不受ESD事件损害，并用于从所述第一线部分传输信号至所述第二线部分，所述静电放电保护器件包括器件寄生，该器件寄生具有与PCB迹线电感/电容比匹配的电感/电容比，所述静电放电保护器件进一步包括：
集成半导体，所述集成半导体包括：
输入台，其适于电耦合至所述印刷电路板的第一线部分，接收所述信号和与所述ESD事件相关联的ESD事件脉冲；
输出台，其适于电耦合至所述印刷电路板的第二线部分；以及
连接在所述输入台和所述输出台之间的静电放电电路，所述静电放电电路为从所述输入台至所述输出台的信号提供电路径，并通过提供至地的路径来消散所述ESD事件脉冲。
2.根据权利要求1的设备，其中使用分别电连接所述输入台至所述第一线部分和所述输出台至所述第二线部分的第一键合线和第二键合线，来调整所述器件寄生的电感/电容比。
3.根据权利要求2的设备，其中所述第一键合线和第二键合线被构造为具有寄生电感，所述寄生电感消除存在于所述PCB迹线的不期望的电容。
4.根据权利要求2的设备，其中提供多个PCB迹线，其提供多个通道，且其中多个键合线彼此匹配以帮助维持所述器件寄生，所述器件寄生具有与所述PCB迹线的电感/电容比匹配的电感/电容。
5.根据权利要求1的设备，其中使用所述静电放电电路调整所述器件寄生的电感/电容比。
6.一种为保护高速接口提供阻抗补偿ESD电路的方法，所述方法包括步骤：
确定PCB迹线的Lo/Co特征阻抗比，所述ESD电路将安装在所述PCB迹线上；和
提供具有确定的寄生的所述阻抗补偿ESD电路以使所述阻抗补偿ESD电路器件的L/C特征阻抗比被补偿以匹配所述PCB迹线的Lo/Co特征阻抗比。
7.根据权利要求1的方法，其中所述提供步骤使用分别电连接输入台至第一线部分和输出台至第二线部分的第一键合线和第二键合线，来提供所述补偿ESD电路器件。
8.根据权利要求7的方法，其中所述第一键合线和第二键合线被构造为具有寄生电感，所述寄生电感消除存在于所述PCB迹线的不期望的电容。
9.根据权利要求7的方法，其中所述提供步骤提供具有多个通道的多个PCB迹线，且其中多个键合线彼此匹配以帮助维持所述器件寄生，所述器件寄生具有与所述PCB迹线的Lo/Co特征阻抗比匹配的L/C特征阻抗比。
10.根据权利要求9的方法，其中使用所述静电放电电路调整所述器件寄生的L/C特征阻抗比。
CN2008801204600A 2007-12-11 2008-12-10 用于保护高速接口的阻抗补偿esd电路及使用其的方法 Pending CN101897095A (zh)

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