CN101884025B - 用于使过程返回序列加速的方法和系统 - Google Patents

用于使过程返回序列加速的方法和系统 Download PDF

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Publication number
CN101884025B
CN101884025B CN200880118806.3A CN200880118806A CN101884025B CN 101884025 B CN101884025 B CN 101884025B CN 200880118806 A CN200880118806 A CN 200880118806A CN 101884025 B CN101884025 B CN 101884025B
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China
Prior art keywords
instruction
return
logic
address
instructions
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Expired - Fee Related
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CN200880118806.3A
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English (en)
Chinese (zh)
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CN101884025A (zh
Inventor
迈克尔·威廉·莫罗
詹姆斯·诺里斯·迪芬德尔费尔
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
CN200880118806.3A 2007-11-02 2008-10-31 用于使过程返回序列加速的方法和系统 Expired - Fee Related CN101884025B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/934,264 US8341383B2 (en) 2007-11-02 2007-11-02 Method and a system for accelerating procedure return sequences
US11/934,264 2007-11-02
PCT/US2008/081947 WO2009059100A1 (en) 2007-11-02 2008-10-31 A method and a system for accelerating procedure return sequences

Publications (2)

Publication Number Publication Date
CN101884025A CN101884025A (zh) 2010-11-10
CN101884025B true CN101884025B (zh) 2014-04-09

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CN200880118806.3A Expired - Fee Related CN101884025B (zh) 2007-11-02 2008-10-31 用于使过程返回序列加速的方法和系统

Country Status (6)

Country Link
US (1) US8341383B2 (https=)
EP (1) EP2220556B1 (https=)
JP (3) JP5301554B2 (https=)
KR (1) KR101254067B1 (https=)
CN (1) CN101884025B (https=)
WO (1) WO2009059100A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7587580B2 (en) * 2005-02-03 2009-09-08 Qualcomm Corporated Power efficient instruction prefetch mechanism
US8341383B2 (en) * 2007-11-02 2012-12-25 Qualcomm Incorporated Method and a system for accelerating procedure return sequences
US9411590B2 (en) * 2013-03-15 2016-08-09 Qualcomm Incorporated Method to improve speed of executing return branch instructions in a processor
US9703948B2 (en) 2014-03-28 2017-07-11 Intel Corporation Return-target restrictive return from procedure instructions, processors, methods, and systems
GB2542831B (en) * 2015-09-30 2018-05-30 Imagination Tech Ltd Fetch unit for predicting target for subroutine return instructions
GB2551548B (en) 2016-06-22 2019-05-08 Advanced Risc Mach Ltd Register restoring branch instruction
US11055098B2 (en) * 2018-07-24 2021-07-06 Advanced Micro Devices, Inc. Branch target buffer with early return prediction
WO2021141760A1 (en) * 2020-01-06 2021-07-15 Quadric. Io, Inc Systems and methods for optimizing nested loop instructions in pipeline processing stages
US11586440B2 (en) * 2021-06-01 2023-02-21 International Business Machines Corporation Link stack based instruction prefetch augmentation

Citations (3)

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US5812813A (en) * 1996-07-29 1998-09-22 Integrated Device Technology, Inc. Apparatus and method for of register changes during execution of a micro instruction tracking sequence
US6374350B1 (en) * 1998-02-20 2002-04-16 Intel Corporation System and method of maintaining and utilizing multiple return stack buffers
US6898698B1 (en) * 1999-09-29 2005-05-24 Fujitsu Limited Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof

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DE69032835T2 (de) * 1989-09-13 1999-07-01 Digital Equipment Corp., Maynard, Mass. Prozedurzustandsdeskriptorsystem für digitale Datenprozessoren
JPH06131250A (ja) * 1992-10-20 1994-05-13 Toshiba Corp データ処理装置
JPH07239782A (ja) * 1994-02-28 1995-09-12 Toshiba Corp 演算処理装置
JPH07281892A (ja) * 1994-04-06 1995-10-27 Hitachi Ltd 情報処理装置
JP2735523B2 (ja) * 1995-11-29 1998-04-02 日本電気アイシーマイコンシステム株式会社 プロシージャ・ステップ処理方法
US6094716A (en) 1998-07-14 2000-07-25 Advanced Micro Devices, Inc. Register renaming in which moves are accomplished by swapping rename tags
US6363473B1 (en) * 1999-04-01 2002-03-26 Compaq Information Technologies Group, L.P. Simulated memory stack in a stackless environment
GB2358261B (en) * 2000-01-17 2004-06-09 Advanced Risc Mach Ltd Data processing with native and interpreted program instruction words
US6848044B2 (en) * 2001-03-08 2005-01-25 International Business Machines Corporation Circuits and methods for recovering link stack data upon branch instruction mis-speculation
US6898699B2 (en) 2001-12-21 2005-05-24 Intel Corporation Return address stack including speculative return address buffer with back pointers
US7017030B2 (en) * 2002-02-20 2006-03-21 Arm Limited Prediction of instructions in a data processing apparatus
US7996659B2 (en) * 2005-06-06 2011-08-09 Atmel Corporation Microprocessor instruction that allows system routine calls and returns from all contexts
US7478228B2 (en) * 2006-08-31 2009-01-13 Qualcomm Incorporated Apparatus for generating return address predictions for implicit and explicit subroutine calls
US8341383B2 (en) * 2007-11-02 2012-12-25 Qualcomm Incorporated Method and a system for accelerating procedure return sequences

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5812813A (en) * 1996-07-29 1998-09-22 Integrated Device Technology, Inc. Apparatus and method for of register changes during execution of a micro instruction tracking sequence
US6374350B1 (en) * 1998-02-20 2002-04-16 Intel Corporation System and method of maintaining and utilizing multiple return stack buffers
US6898698B1 (en) * 1999-09-29 2005-05-24 Fujitsu Limited Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof

Also Published As

Publication number Publication date
EP2220556A1 (en) 2010-08-25
JP5301554B2 (ja) 2013-09-25
US20090119486A1 (en) 2009-05-07
WO2009059100A1 (en) 2009-05-07
KR20100087357A (ko) 2010-08-04
KR101254067B1 (ko) 2013-04-12
JP5815596B2 (ja) 2015-11-17
JP2015133126A (ja) 2015-07-23
EP2220556B1 (en) 2019-03-06
US8341383B2 (en) 2012-12-25
JP2011503718A (ja) 2011-01-27
JP2013211023A (ja) 2013-10-10
CN101884025A (zh) 2010-11-10

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Granted publication date: 20140409

Termination date: 20211031