CN101866920A - ESD protecting structure - Google Patents
ESD protecting structure Download PDFInfo
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- CN101866920A CN101866920A CN201010172671A CN201010172671A CN101866920A CN 101866920 A CN101866920 A CN 101866920A CN 201010172671 A CN201010172671 A CN 201010172671A CN 201010172671 A CN201010172671 A CN 201010172671A CN 101866920 A CN101866920 A CN 101866920A
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Abstract
The invention discloses an ESD protecting structure; an input end of an NMOS ESD device is arranged in an N-type well region, and the N-type well region is used for forming ballast resistance of the NMOS ESD device; meanwhile, a drain electrode of a PMOS ESD device is connected with a drain electrode of the NMOS ESD device, so that the PMOS ESD device also can use the ballast resistance of the NMOS ESD device, and a special ballast resistance of the PMOS ESD device is not needed to be additionally manufactured; therefore, the PMOS ESD device and the NMOS ESD device can share the same ballast resistance, the anti-static electricity capability of the NMOS ESD device and the PMOS ESD device can be guaranteed, the area of a chip is greatly saved, and the cost is reduced.
Description
Technical field
The present invention relates to technical field of integrated circuits, relate in particular to a kind of esd protection structure of the ESD of reducing device size.
Background technology
Enter the deep-submicron epoch of integrated circuit live width along with the integrated circuit fabrication process level, CMOS technology characteristics size is constantly dwindled, transistor constantly reduces for the ability to bear of high voltage and big electric current, the deep-submicron CMOS integrated circuit is easier to be subjected to electrostatic impact and to lose efficacy, thereby causes reliability of products to descend.
Static is ubiquitous in manufacturing, encapsulation, test and the use of chip, the electrostatic charge of accumulation discharges in the time of microsecond in nanosecond with the electric current of several amperes or tens amperes, instantaneous power is up to hundreds of kilowatt, and discharge energy can reach millijoule, and is very big to the destruction intensity of chip.So it is the electrostatic protection Module Design is directly connected to the functional stabilization of chip in the chip design, very important.Along with the development of technology, device feature size diminishes gradually, and grid oxygen is also proportional to be dwindled.The dielectric strength of silicon dioxide is approximately 8 * 10
6V/cm, so thickness is that the grid oxygen puncture voltage of 10nm is about about 8V, many although this puncture voltage will double than the supply voltage of 3.3V, the static that various factors causes, generally its crest voltage far surpasses 8V; And along with all the metallize use of new technologies such as (Salicid) of polysilicon metallization (Polyside), diffusion region metallization (Silicide), polysilicon and diffusion region, the dead resistance of device reduces, and the esd protection ability weakens greatly.
ESD is meant static discharge (Electrostatic Discharge, be called for short ESD), because of the reason of ESD generation and the mode difference that integrated circuit is discharged thereof, characterizing the ESD phenomenon has 4 kinds of models usually: manikin HBM (Human Body Model), machine mould MM (Machine Model) and Charged Device Model CDM (charged Device Model) and electric field induction model FIM (Field Induced Model).The HBM discharge process can produce several amperes the electric current that sparks at hundreds of in nanosecond; The process of MM discharge is shorter, and the electric current that sparks that has several amperes within several nanoseconds to tens nanoseconds produces.The CDM discharge process is shorter, and is the most serious to the harm of chip, several nanoseconds the time ask in electric current reach tens amperes.
The failure cause that ESD causes mainly contains 2 kinds: thermal failure and electricity lost efficacy.Local current is concentrated and a large amount of heat of generation, make fusing of device localized metallic interconnection line or chip hot spot occur, thereby cause second breakdown, be called thermal failure, the electric field strength that is added in the voltage formation on the gate oxide is greater than its dielectric strength, cause dielectric breakdown or surface breakdown, be called electricity and lost efficacy.The inefficacy that ESD causes has 3 kinds of failure modes, is respectively: hard failure, soft failure and potential failure, so-called hard failure are meant the material damage or damage that so-called soft failure is meant the Iterim Change of logic function, and so-called potential failure is meant that time dependence lost efficacy.
In order to prevent that the CMOS integrated circuit (IC) products from causing inefficacy because of ESD, the CMOS integrated circuit (IC) products must be used the esd protection device with high-performance, high tolerance usually.The esd protection device can be resistance, electric capacity, diode, bipolar transistor, metal-oxide-semiconductor, controllable silicon (SCR) etc., wherein metal-oxide-semiconductor owing to technology compatible good, be convenient to integrate and obtained to use widely with digital circuit.
MOS ESD is divided into NMOS ESD again and (is called for short: NESD) (be called for short: PESD) with PMOS ESD, in the CMOS integrated circuit, usually not only need NESD but also need PESD, and the grounded-grid of NESD, the grid of PESD connects high potential, because the CMOS integrated circuit generally all is to adopt P type substrate at present, the method for therefore making NESD and PESD is: definition N type well region and P type well region on P type substrate, on N type well region, make PESD, on P type well region, make NESD.
In order to improve the antistatic property of NESD and PESD; usually the way of taking is: when the grid polycrystalline silicon of PMOS and NMOS and diffusion region metallization; increase a mask definition SAB zone; and increase the width in SAB zone; promptly increase the distance between the drain-to-gate; form big steady resistance, thereby improve the electrostatic protection ability.But the width conference in SAB zone causes device area too big, and the increase of device area has increased the cost of IC design.
In order to reduce the ESD size of devices, there is a kind of method of employing to be at present: to utilize N type well region to produce the steady resistance of NESD, thereby do not need to increase again the SAB zone.This is because the doping of N type well region is low, so its resistivity is very big, thereby only needs the N type well region of small distance just can produce big resistance.Please refer to Fig. 1, Fig. 1 is the schematic diagram of existing ESD structure, and as shown in Figure 1, this ESD structure comprises a P type substrate 100, is positioned at P type well region 200 and N type well region 300, one NESD devices and a PESD device (not indicating among the figure) on the described substrate 100.The grid 401 of described NESD device is positioned on the described P type well region 200, the source region 402 of described NESD device and drain region 404 are positioned at described grid 401 both sides, described source region 402 is positioned at described P type well region 200, described source region 402 links to each other with earth terminal by source electrode 403, and described grid 401 links to each other with earth terminal; Described drain region 404 is positioned at described P type well region 200 and N type well region 300 simultaneously; The input 405 of described NESD device is located in the described N well region 300, and input signal is by input electrode 406 inputs.Like this, the input signal of NESD earlier through N type well region, is imported from the drain region 404 of NESD after input electrode 406 inputs again, therefore the resistance that just generation one is formed by N type well region between the input 405 of NESD and drain region 404, this resistance are promptly as the steady resistance of NESD.Therefore, do not need by the steady resistance that the SAB zone forms NESD is set, thereby saved the size of NESD.
Yet, for PESD, can not be arranged on by input in the P type well region to form the steady resistance of PESD PESD, this is because P type well region is identical with the doping type of P type substrate, there is not ghost effect between them, therefore input signal will be input to P type substrate through P type well region, and can not be input to the drain electrode of PESD through P type well region, also just can not form the steady resistance of PESD.Therefore, PESD still adopts the mode that increases the SAB zone to form steady resistance at present.Thereby also just need bigger device area, increased the cost of IC design.Please refer to Fig. 2, Fig. 2 is the equivalent circuit diagram of existing esd protection structure, and wherein, the steady resistance 20 of NESD forms by N type well region, and the steady resistance 10 of PESD forms by increasing the SAB zone.
Therefore, the device area that how to reduce PESD has effectively become the technical problem that industry needs to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide a kind of esd protection structure, too big to solve existing P ESD device area occupied, the problem that cost is too high.
For addressing the above problem, the present invention proposes a kind of esd protection structure, and described a kind of esd protection structure comprises:
The Semiconductor substrate of first conduction type;
The semiconductor well region of first conduction type;
The semiconductor well region of second conduction type;
First kind MOS ESD device, the grid of described first kind MOS ESD device is positioned on the semiconductor well region of described first conduction type, the source region of described first kind MOS ESD device and drain region are positioned at described grid both sides, described source region is positioned at the semiconductor well region of described first conduction type, described drain region is positioned at the semiconductor well region of described first conduction type and the semiconductor well region of described second conduction type simultaneously, and the input of described first kind MOS ESD device is positioned at the semiconductor well region of described second conduction type; And
The second type MOS ESD device, the described second type MOS ESD device is positioned at the semiconductor well region of described second conduction type, and the drain electrode of the described second type MOS ESD device links to each other with the drain electrode of described first kind MOSESD device.
Optionally, the Semiconductor substrate of described first conduction type is a P type substrate.
Optionally, the semiconductor well region of described first conduction type is a P type well region, and the semiconductor well region of described second conduction type is a N type well region.
Optionally, described first kind MOS ESD device is a NMOS ESD device.
Optionally, the input of described NMOS ESD device is a heavily doped N
+The zone.
Optionally, described heavily doped N
+Be provided with isolated area around the zone.
Optionally, described isolated area be shallow trench isolation from.
Optionally, the described second type MOS ESD device is a PMOS ESD device.
Esd protection structure provided by the present invention is arranged in the N type well region by the input with NMOS ESD device; utilize N type well region to form the steady resistance of NMOS ESD device; drain electrode with PMOS ESD device simultaneously links to each other with the drain electrode of NMOS ESD device; make PMOS ESD device also can utilize the steady resistance of NMOS ESD device; and do not need the extra steady resistance of making special PMOS ESD device; thereby realized the shared of PMOS ESD device and NMOS ESD device steady resistance, guaranteed NMOS
In the time of ESD device and PMOS ESD device antistatic effect, greatly save area of chip, reduced cost.
Description of drawings
Fig. 1 is the schematic diagram of existing esd protection structure;
Fig. 2 is the equivalent circuit diagram of existing esd protection structure;
Fig. 3 is the schematic diagram of esd protection structure provided by the invention;
Fig. 4 is the equivalent circuit diagram of esd protection structure provided by the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the esd protection structure that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is; a kind of esd protection structure is provided; described esd protection structure is arranged in the N type well region by the input with NMOS ESD device; utilize N type well region to form the steady resistance of NMOS ESD device; drain electrode with PMOS ESD device simultaneously links to each other with the drain electrode of NMOS ESD device; make PMOS ESD device also can utilize the steady resistance of NMOS ESD device; and do not need the extra steady resistance of making special PMOS ESD device; thereby realized the shared of PMOS ESD device and NMOS ESD device steady resistance; when guaranteeing NMOS ESD device and PMOS ESD device antistatic effect; greatly save area of chip, reduced cost.
Please refer to Fig. 3 and Fig. 4, wherein, Fig. 3 is the schematic diagram of esd protection structure provided by the invention, and Fig. 4 is the equivalent circuit diagram of esd protection structure provided by the invention, and to shown in Figure 4, described esd protection structure comprises as Fig. 3:
The Semiconductor substrate 100 of first conduction type;
The semiconductor well region 200 of first conduction type;
The semiconductor well region 300 of second conduction type;
First kind MOS ESD device, the grid 401 of described first kind MOS ESD device is positioned on the semiconductor well region 200 of described first conduction type, the source region 402 of described first kind MOS ESD device and drain region 404 are positioned at described grid 401 both sides, described source region 402 is positioned at the semiconductor well region 200 of described first conduction type, described drain region 404 is positioned at the semiconductor well region 200 of described first conduction type and the semiconductor well region 300 of described second conduction type simultaneously, and the input 405 of described first kind MOS ESD device is positioned at the semiconductor well region 300 of described second conduction type; And
The second type MOS ESD device (not identifying among the figure), the described second type MOS ESD device is positioned at the semiconductor well region 300 of described second conduction type, and the drain electrode of the described second type MOS ESD device links to each other with the drain electrode 408 of described first kind MOS ESD device.
Wherein, the Semiconductor substrate 100 of described first conduction type is a P type substrate, the semiconductor well region 200 of described first conduction type is a P type well region, the semiconductor well region 300 of described second conduction type is a N type well region, described first kind MOS ESD device is a NMOS ESD device, and the described second type MOS ESD device is a PMOS ESD device.
And the source electrode 403 and the grid 401 of described NMOS ESD device link to each other with earth terminal, and the signal input of described NMOSESD device is by input electrode 406 inputs.
The input 405 of described NMOS ESD device is a heavily doped N
+The zone is provided with shallow channel isolation area 407 around the described input 405.
In a specific embodiment of the present invention, the Semiconductor substrate of described first conduction type is a P type substrate, yet should be realized that, the Semiconductor substrate of described first conduction type can also be N type substrate, only need utilize the steady resistance of P type well region formation PMOS ESD device this moment, and with this steady resistance and shared the getting final product of NMOS ESD device.
In sum; the invention provides a kind of esd protection structure spare; described esd protection structure is arranged in the N type well region by the input with NMOS ESD device; utilize N type well region to form the steady resistance of NMOS ESD device; drain electrode with PMOS ESD device simultaneously links to each other with the drain electrode of NMOS ESD device; make PMOS ESD device also can utilize the steady resistance of NMOS ESD device; and do not need the extra steady resistance of making special PMOS ESD device; thereby realized the shared of PMOS ESD device and NMOS ESD device steady resistance; when guaranteeing NMOS ESD device and PMOS ESD device antistatic effect; greatly save area of chip, reduced cost.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (8)
1. an esd protection structure is characterized in that, comprising:
The Semiconductor substrate of first conduction type;
The semiconductor well region of first conduction type;
The semiconductor well region of second conduction type;
First kind MOS ESD device, the grid of described first kind MOS ESD device is positioned on the semiconductor well region of described first conduction type, the source region of described first kind MOS ESD device and drain region are positioned at described grid both sides, described source region is positioned at the semiconductor well region of described first conduction type, described drain region is positioned at the semiconductor well region of described first conduction type and the semiconductor well region of described second conduction type simultaneously, and the input of described first kind MOS ESD device is positioned at the semiconductor well region of described second conduction type; And
The second type MOS ESD device, the described second type MOS ESD device is positioned at the semiconductor well region of described second conduction type, and the drain electrode of the described second type MOS ESD device links to each other with the drain electrode of described first kind MOSESD device.
2. esd protection structure as claimed in claim 1 is characterized in that, the Semiconductor substrate of described first conduction type is a P type substrate.
3. esd protection structure as claimed in claim 2 is characterized in that, the semiconductor well region of described first conduction type is a P type well region, and the semiconductor well region of described second conduction type is a N type well region.
4. esd protection structure as claimed in claim 2 is characterized in that, described first kind MOS ESD device is a NMOS ESD device.
5. esd protection structure as claimed in claim 4 is characterized in that, the input of described NMOS ESD device is a heavily doped N+ zone.
6. esd protection structure as claimed in claim 5 is characterized in that, described heavily doped N
+Be provided with isolated area around the zone.
7. esd protection structure as claimed in claim 6 is characterized in that, described isolated area be shallow trench isolation from.
8. esd protection structure as claimed in claim 2 is characterized in that, the described second type MOS ESD device is a PMOS ESD device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010172671.8A CN101866920B (en) | 2010-05-12 | 2010-05-12 | A kind of esd protection structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010172671.8A CN101866920B (en) | 2010-05-12 | 2010-05-12 | A kind of esd protection structure |
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| CN101866920A true CN101866920A (en) | 2010-10-20 |
| CN101866920B CN101866920B (en) | 2015-12-09 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102655149A (en) * | 2012-05-07 | 2012-09-05 | 中国航天科技集团公司第九研究院第七七一研究所 | PD SOI (partially-depleted silicon on insulator) technology-based body grid coupling ESD (electro-static discharge) protection structure |
| CN106024896A (en) * | 2016-06-30 | 2016-10-12 | 上海华力微电子有限公司 | ESD NMOS device structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020074608A1 (en) * | 2000-10-31 | 2002-06-20 | Eiji Aoki | Protection circuit and semiconductor device |
| CN1414639A (en) * | 2001-10-22 | 2003-04-30 | 联华电子股份有限公司 | Silicon rectifier set in silicon covered insulator and its application circuit |
-
2010
- 2010-05-12 CN CN201010172671.8A patent/CN101866920B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020074608A1 (en) * | 2000-10-31 | 2002-06-20 | Eiji Aoki | Protection circuit and semiconductor device |
| CN1414639A (en) * | 2001-10-22 | 2003-04-30 | 联华电子股份有限公司 | Silicon rectifier set in silicon covered insulator and its application circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102655149A (en) * | 2012-05-07 | 2012-09-05 | 中国航天科技集团公司第九研究院第七七一研究所 | PD SOI (partially-depleted silicon on insulator) technology-based body grid coupling ESD (electro-static discharge) protection structure |
| CN102655149B (en) * | 2012-05-07 | 2015-01-07 | 中国航天科技集团公司第九研究院第七七一研究所 | PD SOI (partially-depleted silicon on insulator) technology-based body grid coupling ESD (electro-static discharge) protection structure |
| CN106024896A (en) * | 2016-06-30 | 2016-10-12 | 上海华力微电子有限公司 | ESD NMOS device structure |
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| CN101866920B (en) | 2015-12-09 |
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