CN106024896A - ESD NMOS device structure - Google Patents
ESD NMOS device structure Download PDFInfo
- Publication number
- CN106024896A CN106024896A CN201610510501.3A CN201610510501A CN106024896A CN 106024896 A CN106024896 A CN 106024896A CN 201610510501 A CN201610510501 A CN 201610510501A CN 106024896 A CN106024896 A CN 106024896A
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- CN
- China
- Prior art keywords
- nmos device
- esd
- region
- well
- device structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an ESD NMOS (electro static discharge n-channel metal oxide semiconductor) device structure. The device structure includes a substrate, a P well and an N well which are formed in the substrate, an NMOS device source region and an NMOS device drain region which are formed in the P well, an N type drain region formed at the upper part of the N well, and a gate structure which is formed on the P well and is located between the NMOS device source region and the NMOS device drain region, wherein the NMOS device drain region is separated from the N type drain region through a first shallow trench; and a protective ring region which is separated from the NMOS device source region through a second shallow trench is formed in the P well.
Description
Technical field
The present invention relates to quasiconductor design and manufacture field, it is more particularly related to a kind of electrostatic is released
Put (Electro Static Discharge, ESD) nmos device structure.
Background technology
Constantly enter submicron, deep-submicron along with semiconductor device art, electrostatic discharge protection device is reliable
Property becomes more and more important.In order to overcome lightly doped drain (Lightly Doped Drain, LDD) structure band
The problem that the electrostatic discharge protection ability come declines, Electro-static Driven Comb ion implanting (ESD implant) technology is joined
Close silicide baffle plate (Salicide blocking, SAB) technique, it is possible to obtain well effect.Generally,
ESD device need silicide baffle plate SAB mask to improve the ESD protective capability of NMOS, and reduce cover
Film can significantly reduce cost, is even more important especially for nanometer-grade IC design and manufacture.
Additionally, be the said current dumping ability improving ESD device, ESD NMOS design uses many finger-like to set
Meter structure, but ensure that its uniform unlatching is an importance of ESD circuit design.At GGNMOS
When many finger-like of (grounded-gate NMOS, the NMOS of grounded-grid) ESD device design, very
Being difficult to ensure that card finger triggers simultaneously, for the method avoiding this situation, traditional method is to use silicide baffle plate SAB
Technology improves drain region BHF control, to ensure that each finger undertakes earial drainage task uniformly, makes electric current uniform
Flow in wafer bulk, it is also desirable to domain is designed.
In the prior art, it is proposed that some schemes (such as, United States Patent (USP) US7170726B2) use electricity
Sense coupling network improves many finger-like of ESD NMOS and opens uniformity.But the method inductance area is bigger.
Another one scheme (such as, United States Patent (USP) US6747501B2) uses control circuit technology to improve ESD
The unlatching uniformity of nmos device structure, but there is also the shortcoming that circuit is complicated and area is big.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that one is not
Needing the ESD nmos device structure of the new construction of SAB mask, it uses N trap and novel layout techniques
Improve the BHF control in drain region, thus equally improve the ESD protective capability of NMOS, it is achieved that
The ESD protection of nmos device, saves silicide baffle plate SAB mask simultaneously, greatly reduces cost.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of ESD nmos device structure,
Including: substrate, the p-well being formed in substrate and N trap, the nmos device source area being formed in p-well
Territory and nmos device drain region, it is formed at the N-type drain electrode on N trap top, is formed on p-well region
The grid structure between nmos device source region and nmos device drain region of side；Wherein,
Nmos device drain region and N-type drain electrode are separated by the first shallow trench.
Preferably, p-well is formed through the second shallow trench isolation separate with nmos device source region
Protection ring region.
Preferably, it is formed with polycrystalline silicon at ESD nmos device body structure surface.
Preferably, protection ring region is p-type doping.
Preferably, the doping content in protection ring region is more than the doping content of p-well.
Preferably, substrate is p-type doping.
Preferably, the doping content in protection ring region is more than the doping content of substrate.
The present invention proposes a kind of new construction that need not SAB mask, uses N trap and novel layout techniques
Improve the BHF control in drain region, thus equally improve the ESD protective capability of NMOS, it is achieved that NMOS
The ESD protection of device, saves SAB mask simultaneously, greatly reduces cost.And, N trap resistance ratio
After silicide baffle plate, active area N-type heavy doping (N+) resistance is big, and many finger-like are opened effect and become apparent from, ESD
Can be more preferably.Thus, the present invention not only reduces by one mask while realizing ESD defencive function (SAB covers
Film), and enhance said current dumping ability and open uniformity.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete
Understand and its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows the vertical view of ESD nmos device structure according to the preferred embodiment of the invention
Figure.
Fig. 2 schematically shows the cross section of ESD nmos device structure according to the preferred embodiment of the invention
Figure.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent structure
Accompanying drawing may be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicate identical or
The label that person is similar to.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings to this
Bright content is described in detail.
Fig. 1 schematically shows the vertical view of ESD nmos device structure according to the preferred embodiment of the invention
Figure.Fig. 2 schematically shows the ESD nmos device according to the preferred embodiment of the invention shown in Fig. 1
The sectional view that structure along line A-A intercepts.
As depicted in figs. 1 and 2, ESD nmos device structure includes according to the preferred embodiment of the invention:
Substrate 100, the p-well 10 and N trap 20 being formed in substrate 100, the NMOS that is formed in p-well 10
Device source region 11 and nmos device drain region 12, it is formed at the N-type drain on N trap 20 top
District 30, be formed at p-well 10 overlying regions between nmos device source region 11 and nmos device
Grid structure 40 between drain region 12；Wherein, nmos device drain region 12 and N-type drain electrode
By the first shallow trench isolation 51,30 separate that (that is, nmos device drain region and N-type drain electrode 30 is
Drain electrode, is formed by with a same concentrations injection technology, is simply kept apart by the first shallow trench isolation 51).
And, p-well 10 is also formed through the second shallow trench isolation 52 and nmos device source region
The protection ring region 60 that 11 separate.
It is formed with polycrystalline silicon at ESD nmos device body structure surface.
Wherein, protection ring region 60 is p-type doping.
Wherein, the doping content in protection ring region 60 is more than the doping content of p-well 10.
Wherein, the doping content of N-type drain electrode 30 is more than the doping content of N trap 20.
Preferably, substrate 100 is p-type doping.And it is further preferred that the mixing of protection ring region 60
Miscellaneous concentration is more than the doping content of substrate 100.
For above-mentioned device architecture, it is shallow no less than two that drain extensions utilizes active area mask and technique to be formed
Groove isolation construction, and utilize N trap mask to carry out N trap ion implanting in this region, to improve NMOS
The ESD protective value of device.After in described structure, drain extensions forms shallow trench isolation and N trap, enter
Row normally drains heavy doping (N+) ion implanting, does not the most carry out silicide baffle plate, and carry out normal from
Alignment polycrystalline silicon (SALICIDE) technique.
Drain extensions forms shallow trench isolation and N well structure, and this structure has bigger pressure compared with traditional structure
Storehouse resistance (ballast resistance), thus improve the Electro-static Driven Comb current capacity of ESD nmos device structure.
Further, can to drain extensions formed STI and N well structure be optimized, including symmetrical structure,
Loop configuration, thus improve the unlatching uniformity of ESD nmos device structure.
The present invention proposes a kind of new construction that need not SAB mask, uses N trap and novel layout techniques
Improve the BHF control in drain region, thus equally improve the ESD protective capability of NMOS, it is achieved that NMOS
The ESD protection of device, saves SAB mask simultaneously, greatly reduces cost.And, N trap resistance ratio
After silicide baffle plate, active area N-type heavy doping (N+) resistance is big, and many finger-like are opened effect and become apparent from, ESD
Can be more preferably.
Thus, the present invention not only reduces by one mask (SAB mask) while realizing ESD defencive function,
And enhance said current dumping ability and open uniformity.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ",
" second ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc., and not
It is intended to indicate that the logical relation between each assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment is also
It is not used to limit the present invention.For any those of ordinary skill in the art, without departing from skill of the present invention
In the case of art aspects, technical solution of the present invention is made many by the technology contents that all may utilize the disclosure above
Possible variation and modification, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from this
The content of bright technical scheme, according to the present invention technical spirit to any simple modification made for any of the above embodiments,
Equivalent variations and modification, all still fall within the range of technical solution of the present invention protection.
Claims (8)
1. an ESD nmos device structure, it is characterised in that including: substrate, the P being formed in substrate
Trap and N trap, the nmos device source region being formed in p-well and nmos device drain region, shape
Become N-type drain electrode on N trap top, be formed at above p-well region between nmos device source region
And the grid structure between nmos device drain region；Wherein, nmos device drain region and N-type leakage
Polar region is separated by the first shallow trench.
ESD nmos device structure the most according to claim 1, it is characterised in that formed in p-well
Have and isolate, by the second shallow trench, the protection ring region separated with nmos device source region.
ESD nmos device structure the most according to claim 1 and 2, it is characterised in that at ESD
Nmos device body structure surface is formed with polycrystalline silicon.
ESD nmos device structure the most according to claim 1 and 2, it is characterised in that protection
Ring region territory is p-type doping.
ESD nmos device structure the most according to claim 1 and 2, it is characterised in that protection
The doping content in ring region territory is more than the doping content of p-well.
ESD nmos device structure the most according to claim 1 and 2, it is characterised in that N-type
The doping content of drain region is equal to the doping content of drain region.
ESD nmos device structure the most according to claim 1 and 2, it is characterised in that substrate
It it is p-type doping.
ESD nmos device structure the most according to claim 7, it is characterised in that protection ring region
The doping content in territory is more than the doping content of substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610510501.3A CN106024896A (en) | 2016-06-30 | 2016-06-30 | ESD NMOS device structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610510501.3A CN106024896A (en) | 2016-06-30 | 2016-06-30 | ESD NMOS device structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106024896A true CN106024896A (en) | 2016-10-12 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610510501.3A Pending CN106024896A (en) | 2016-06-30 | 2016-06-30 | ESD NMOS device structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN106024896A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019001518A1 (en) * | 2017-06-30 | 2019-01-03 | 无锡华润上华科技有限公司 | Semiconductor electrostatic protection structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030197226A1 (en) * | 2002-04-22 | 2003-10-23 | United Microelectronics Corp. | Structure and fabrication method of electrostatic discharge protection circuit |
| CN1630079A (en) * | 2003-12-15 | 2005-06-22 | 三星电子株式会社 | Electrostatic discharge protection device and manufacturing method thereof |
| US20060065932A1 (en) * | 2004-09-30 | 2006-03-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit to improve ESD performance made by fully silicided process |
| CN101866920A (en) * | 2010-05-12 | 2010-10-20 | 上海宏力半导体制造有限公司 | ESD protecting structure |
-
2016
- 2016-06-30 CN CN201610510501.3A patent/CN106024896A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030197226A1 (en) * | 2002-04-22 | 2003-10-23 | United Microelectronics Corp. | Structure and fabrication method of electrostatic discharge protection circuit |
| CN1630079A (en) * | 2003-12-15 | 2005-06-22 | 三星电子株式会社 | Electrostatic discharge protection device and manufacturing method thereof |
| KR100645039B1 (en) * | 2003-12-15 | 2006-11-10 | 삼성전자주식회사 | Electrostatic discharge protection device and mehtod of fabricating the same |
| US20060065932A1 (en) * | 2004-09-30 | 2006-03-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit to improve ESD performance made by fully silicided process |
| CN101866920A (en) * | 2010-05-12 | 2010-10-20 | 上海宏力半导体制造有限公司 | ESD protecting structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019001518A1 (en) * | 2017-06-30 | 2019-01-03 | 无锡华润上华科技有限公司 | Semiconductor electrostatic protection structure |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20161012 |
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| RJ01 | Rejection of invention patent application after publication |