CN101846875B

CN101846875B - Gray-scale photomask for defining patterns of source electrode, drain electrode and semiconductor layer of TFT

Info

Publication number: CN101846875B
Application number: CN2009101193481A
Authority: CN
Inventors: 蔡东晓; 苏大荣
Original assignee: CPT Video Wujiang Co Ltd; Chunghwa Picture Tubes Ltd
Current assignee: CPT Video Wujiang Co Ltd; Chunghwa Picture Tubes Ltd
Priority date: 2009-03-25
Filing date: 2009-03-25
Publication date: 2011-11-16
Anticipated expiration: 2029-03-25
Also published as: CN101846875A

Abstract

The invention relates to a gray-scale photomask for defining patterns of a source electrode, a drain electrode and a semiconductor layer of a TFT, which comprises a substrate and a making pattern, a translucent pattern and a transparent area which are arranged on the substrate, wherein the masking pattern is used for defining the patterns of the source electrode and drain electrode of a thin film transistor and the patterns of a semiconductor layer arranged below the source electrode or the drain electrode; the translucent pattern is used for defining the semiconductor layer which is not covered by the source electrode and the drain electrode, and the translucent pattern encircles the outer side of the making pattern in general; and the outer edge of the translucent pattern keeps a certain distance with the edge of the source electrode or the drain electrode.

Description

Gray-level mask in order to the pattern of source electrode, drain electrode and the semiconductor layer of definition of T FT

Technical field

The invention relates to a kind of gray-level mask of pattern of source electrode, drain electrode and the semiconductor layer that is used to define thin film transistor (TFT)

Background technology

Thin film transistor (TFT) (TFT) has been widely used in the large area electron circuit product, in LCD (LCD), contact-type image sensing device (CIS) and other common consumer electronic devices, mainly is the role who is playing the part of control element.Known thin film transistor (TFT) comprises a gate electrode, one source pole, one drain electrode and as the semi-conductor layer of transistor channels, when making thin film transistor (TFT) with existing manufacturing technology, usually the micro-photographing process of needs more than four times defines the pattern of each element of thin film transistor (TFT), in order to reduce the processing procedure cost, when definition thin-film transistor element pattern, then use gray-level mask (half-tone mask) to be used as the second road light shield for preparing thin film transistor (TFT) at present, therefore when making thin film transistor (TFT), comprise the making that gray-level mask only needs four times micro-photographing process can be finished thin film transistor (TFT).

Please refer to Fig. 1 to Fig. 4, Fig. 1 and Fig. 4 are the processing procedure synoptic diagram that illustrates known use four road light shield manufacture thin film transistor (TFT)s.As shown in Figure 1, provide a substrate 10 that is used to prepare thin film transistor (TFT).Substrate 10 surfaces are provided with one and utilize the first road light shield to carry out one first little shadow and the formed gate electrode 12 of etch process; form a gate electrode insulation course 14, semi-conductor layer 16, a conductive layer 18 and a photoresist layer 20 afterwards more in regular turn; in addition; for reducing the resistance value of 16 of conductive layer 18 and semiconductor layers, can form an ohmic contact layer (n who contains N type admixture in addition at

conductive layer

18 and 16 of semiconductor layers usually ⁺Ohmiccontact layer) 17.

Then please refer to Fig. 2 and Fig. 3, Fig. 2 is the synoptic diagram that illustrates as a gray-level mask 22 of the second road light shield.Gray-level mask 22 comprises a transparency carrier 24 and is located at one on the transparency carrier 24 and covers pattern 26, an and semi-transparent zone (half-tone region) 30, wherein covering pattern 26 is the patterns that are used to define thin film transistor (TFT) drain electrode and source electrode, and semi-transparent district 30 is used to define the pattern that is positioned at source electrode and drain electrode lower semiconductor layer, and as shown in Figure 2, semi-transparent district 30 is the patterns for a matrix, the opening of matrix is the position for drain electrode, the bottom of matrix is the passage that is used to define thin film transistor (TFT), and the edge of matrix both sides, semi-transparent district is along the edge setting of covering pattern 26.As shown in Figure 3, utilize gray-level mask 22 as the second road light shield and carry out second little shadow and the etch process, because the penetrability difference in each district of gray-level mask 22 in exposure process, therefore will be different via the thickness of the formed patterning photoresistance 32 of micro-photographing process with exposure, be the etch process of row then via one, and be the etching shade with patterning photoresistance 32, remove conductive layer 18, an ohmic contact layer 17 and the semiconductor layer 16 of part, with the drain electrode that defines thin film transistor (TFT), source electrode and as the semiconductor island of film crystal tube passage.Remove partially patterned photoresistance 32 thereafter; make channel region exposed; then remove the semiconductor layer 16 of partially conductive layer 18, part ohmic contact layer 17 and the part of channel region top in regular turn; and then remove patterning photoresistance 32 fully; the line number of going forward side by side road deposition manufacture process; and carry out the 3rd, the 4th little shadow and etch process, on substrate 10, form protective seam at last, to finish the making of thin film transistor (TFT).

As shown in Figure 4, Fig. 4 is the vertical view that utilizes the formed thin film transistor (TFT) 34 of above-mentioned processing procedure.As shown in Figure 4, the edge of the source electrode 36 of thin film transistor (TFT) 34 and drain electrode 38 with extremely press close to as semiconductor layer 40 edges of passage; If semiconductor layer 40 is not etched complete in etching process, when producing as the kick (so-called " native hand phenomenon " promptly takes place) as the mound, the former electronics that should drift to source electrode 36 via passage, edge along semiconductor layer 40 moves on the contrary, produce a leakage current path 42 (direction shown in arrow among the figure) at source electrode 36 and 38 semiconductor layer 40 edges of drain electrode, this leakage current path will have a strong impact on the element normal running of thin film transistor (TFT) 34.

Summary of the invention

For solving the electric leakage problem of above-mentioned thin film transistor (TFT), the inventor is after deep thinking, and a kind of gray-level mask that improves thin film transistor (TFT) electric leakage problem of special proposition is to overcome the deficiency of known technology.

For reaching above-mentioned purpose, the invention provides a kind of gray-level mask of pattern of source electrode, drain electrode and the semiconductor layer in order to the definition thin film transistor (TFT), it comprises a substrate and is located at one on this substrate and covers pattern, a semi-transparent pattern and a photic zone.This covers pattern and comprises one and cover pattern and in order to first of the pattern of the pattern of the drain electrode of definition thin film transistor (TFT) and the semiconductor layer that is positioned at drain electrode below and cover pattern in order to second of the pattern of the pattern of the source electrode of definition thin film transistor (TFT) and the semiconductor layer that is positioned at the source electrode below, wherein this first covers pattern and has one first limit and one second limit, and this first limit is vertical substantially with this second limit, and this second covers pattern and has one first limit and one second limit, this first limit is vertical substantially with this second limit, and this first this first limit of covering pattern with this second cover this first limit of pattern parallel substantially and the two between have a gap; In addition, this semi-transparent pattern of being located on the substrate is not by the pattern of drain electrode with the semiconductor layer of source electrode covering in order to definition, wherein this semi-transparent pattern has a main pattern and is located at this and first covers in pattern and this second this gap of covering between the pattern, and one first extends pattern and stretches out and coat this first this second limit and this second this second limit of covering pattern of covering pattern from this main pattern.

Therefore, use the thin film transistor (TFT) of gray-level mask preparation of the present invention, the outer rim of its semiconductor layer is that the edge with drain electrode or source electrode keeps a segment distance respectively, make electronics certainly the edge that drains through the leakage path growth of semiconductor layer edge to the source electrode edge, resistance value also increases with path propagation comparatively speaking, therefore can reduce the possibility of electronics along the semiconductor edge current leakage indirectly.

Description of drawings

Fig. 1 and Fig. 4 are the processing procedure synoptic diagram that illustrates known use four road light shield manufacture thin film transistor (TFT)s.

Fig. 5 is the gray-level mask of pattern in order to source electrode, drain electrode and the semiconductor layer of definition thin film transistor (TFT) that is illustrated according to a preferred embodiment of the present invention.

Embodiment

Please refer to Fig. 5, Fig. 5 illustrates according to a preferred embodiment of the present invention, in order to the gray-level mask 44 of the pattern of the source electrode, drain electrode and the semiconductor layer that define thin film transistor (TFT).As shown in Figure 5, gray-level mask 44 comprises a substrate 45 and forms one on the substrate 45 and covers pattern 48, one a semi-transparent pattern 54 and a printing opacity pattern 56.

Covering pattern 48 comprises one first and covers pattern 50 and one second and cover pattern 52, wherein first to cover pattern 50 be in order to the pattern of the drain electrode of definition thin film transistor (TFT) and the pattern of the semiconductor layer that is positioned at drain electrode below, and first covers pattern 50 has one first limit 501, one second limit 502 and one the 3rd limit 503, substantially, second limit 502 and the 3rd limit 503 are respectively perpendicular to first limit 501, and second limit 502 and the 3rd limit 503 are substantially and are parallel to each other.In addition, first covers pattern 50 is connected with a connection gasket pattern 53 that is used to define the drain electrode connection gasket in addition, so that when the source electrode that forms thin film transistor (TFT), drain electrode and semiconductor, form the drain electrode connection gasket that is electrically connected with thin film transistor (TFT) other elements (for example pixel electrode) in addition in the lump.

Covering second of pattern 48, to cover pattern 52 be in order to the pattern of the source electrode of definition thin film transistor (TFT) and the pattern of the semiconductor layer that is positioned at source electrode below.Second covers pattern 52 has one first limit 521 and one second limit 522, second to cover first limit 521 of pattern 52 vertical with second limit 522 substantially, and, as shown in Figure 5, first first limit 501 and second of covering pattern 50 cover pattern 52 first limit 521 the two be parallel to each other, each other and possess a gap.

Cover pattern 50 and second first and cover 52 in pattern and be provided with semi-transparent pattern 54, its transmittance is between covering between pattern 48 and the photic zone 56.Semi-transparent pattern 54 is patterns of the semiconductor layer that covered by drain electrode and source electrode in order to definition, and wherein semi-transparent pattern 54 comprises a main pattern 541, one first and extends pattern 542, one second and extend that pattern 543, one first drain electrode coat pattern 544, one second drain electrode coats pattern 545 and one source pole coating pattern 546.Main pattern 541 is to cover pattern 50 and second first to cover this gap between the pattern 52, mainly be used to be located at source electrode and drain between channel pattern; The first extension pattern 542 and the second extension pattern 543 are that the two ends of autonomous desirable pattern 541 stretch out, and it is vertical with main pattern 541 respectively, and the first extension pattern 542 is to be coated on 522 outsides, second limit that pattern 52 is covered on first second limit 502 and second of covering pattern 50, and the second extension pattern 543 is to be enclosed in first 503 outsides, the 3rd limit of covering pattern 50; Simultaneously, first drain electrode of semi-transparent pattern 54 coats pattern 544 and second drain electrode and coats pattern 545 and be arranged on first and cover pattern 50 second side of covering pattern 52 dorsad, and extends pattern 542 and second and extend pattern 543 and be connected with first respectively; In addition, semi-transparent regional 54 source electrode coats pattern 546 and is provided in a side of second and covers pattern 52 back to covering an example of pattern 50 in first, and connects first and extend pattern 542.As seen from Figure 5, first of gray-level mask covers pattern 50 by the main pattern 541 of semi-transparent pattern 54, first extends pattern 542, second extends pattern 543, the first drain electrode coating case 544 and second drain electrode coat pattern 545 and center on, second covers the then main pattern 541 of quilt of pattern 52, the first extension pattern 542 and source electrode coat pattern 546 and surround, therefore with regard to macroscopic, the semi-transparent pattern 54 of gray-level mask 44 is enclosed in first substantially and covers the pattern 50 and second periphery of covering pattern 52, in order to define thin film transistor (TFT) not by the pattern of source electrode or the semiconductor layer that drain electrode covered.

It should be noted that, simultaneously comparison diagram 2 and Fig. 5, gray-level mask 44 of the present invention cover pattern 48 with respect to semi-transparent pattern 54, originally extend out at the staged edge of figure right side of face and trim, and by the setting of first extension area 542, extend first second limit 502 and second of covering pattern 50 and covered the distance of second limit, 522 to first extension areas, 542 outer rims of pattern 52; Simultaneously, it is the edge settings of covering pattern 52 along second that the source electrode of gray-level mask 44 coats district 546, has increased semiconductor layer at the other area of source electrode; The outer rim of therefore utilize semi-transparent pattern 54 semiconductor layer that defines out can be possessed a suitable distance with the edge of drain electrode or source electrode, even because etching when native hand phenomenon not exclusively takes place, still can be avoided draining or the edge of source electrode and semiconductor layer is crossed near and leaky initiation.

Therefore, if use gray-level mask 44 of the present invention when making the second road light shield of thin film transistor (TFT), and when being the material of etching shade with the positive photoresistance that can be dissolved in developer after the exposure, on those material layers at thin film transistor (TFT) behind the exposure imaging, form the photoresistance pattern that the thickness degree differs, then again through a series of etch process, after removing unnecessary material layer, define source electrode, drain electrode and the semiconductor layer of thin film transistor (TFT); Therefore utilize the thin film transistor (TFT) of gray-level mask 44 mades shown in the above-mentioned preferred embodiment, the outer rim of the semiconductor layer that is defined by semi-transparent pattern 54 will maintain a certain distance with the edge of source electrode or drain electrode; Comparatively speaking, electronics extends along the path that the semiconductor layer outer rim moves to source electrode from drain electrode, and its resistance value also prolongs with the path and increases, and reduces the possibility of its electric leakage indirectly.

In sum, the gray-level mask that is used to make thin film transistor (TFT) disclosed in this invention is that definable goes out bigger semiconductor layer, the edge of feasible drain electrode or source electrode and the outer rim of semiconductor layer keep the distance of an appropriateness, the part that semiconductor layer protrudes from source electrode or drain electrode has increased resistance value, can reduce electronics and move to the possibility of source electrode, with the electric leakage problem of effective minimizing thin film transistor (TFT) via the semiconductor edge.

The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. the gray-level mask of the pattern of source electrode, drain electrode and a semiconductor layer that is used for definition of T FT is characterized in that, comprises:

One substrate;

One covers pattern, is located on this substrate, and this covers pattern and comprises:

One first covers pattern, and in order to the pattern of the drain electrode of definition thin film transistor (TFT) and the pattern of the semiconductor layer that is positioned at drain electrode below, wherein this first covers pattern and have one first limit and one second limit, and this first limit is vertical substantially with this second limit; And

One second covers pattern, in order to the pattern of the source electrode of definition thin film transistor (TFT) and the pattern of the semiconductor layer that is positioned at source electrode below, this second covers pattern and has one first limit and one second limit, this first limit is vertical substantially with this second limit, and this first this first limit of covering pattern with this second cover this first limit of pattern parallel substantially and the two between have a gap;

One semi-transparent pattern, be located on this substrate, in order to define by the pattern of drain electrode with the semiconductor layer of source electrode covering, wherein this semi-transparent pattern has a main pattern and is located at this and first covers in pattern and this second this gap of covering between the pattern, and one first extends pattern and stretches out and coat this first this second limit and this second this second limit of covering pattern of covering pattern from this main pattern; And

One photic zone is located on this substrate.

2. gray-level mask as claimed in claim 1 is characterized in that, this semi-transparent pattern comprises one first drain electrode and coats pattern, is connected in this and first extends pattern and coat this and first cover pattern this second side of covering pattern dorsad.

3. gray-level mask as claimed in claim 1 is characterized in that, this semi-transparent pattern comprises one source pole and coats the district, is connected in this and first extends pattern and coat this and second cover pattern back to first side of covering pattern.

4. gray-level mask as claimed in claim 1, it is characterized in that, this first covers pattern and has one the 3rd limit, first to cover first limit of pattern vertical substantially with this on this first the 3rd limit of covering pattern, and this semi-transparent pattern also comprises one second and extends pattern and stretch out and coat this first the 3rd limit of covering pattern from this main pattern.

5. gray-level mask as claimed in claim 4 is characterized in that, this semi-transparent pattern comprises one second drain electrode and coats pattern, is connected in this and second extends pattern and coat this and first cover pattern this second side of covering pattern dorsad.