CN101834718A - Chaotic signal generating circuit - Google Patents
Chaotic signal generating circuit Download PDFInfo
- Publication number
- CN101834718A CN101834718A CN 201010181924 CN201010181924A CN101834718A CN 101834718 A CN101834718 A CN 101834718A CN 201010181924 CN201010181924 CN 201010181924 CN 201010181924 A CN201010181924 A CN 201010181924A CN 101834718 A CN101834718 A CN 101834718A
- Authority
- CN
- China
- Prior art keywords
- circuit
- class
- change
- signal
- microcontroller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Complex Calculations (AREA)
Abstract
The invention relates to a chaotic signal generating circuit, comprising a microcontroller, a signal isolating circuit, three D/A switching circuits; each D/A switching circuit comprises 16-bit shift registers and 16-bit DAC registers and shift registers in each D/A switching circuit are connected in series to form a 48-bit shift register. Serial digital signals output by an SPI interface of the microcontroller are transmitted to a serial data input terminal of a first D/A switching circuit through the signal isolating circuit; clock signals and latch control signals output by the SPI interface are respectively transmitted to a clock input terminal and a latch control signal input terminal of the D/A switching circuit through the signal isolating circuit. In the invention, based on the chaotic circuit of the microcontroller, the Euler algorithm is adopted to carry out discretization processing on the continuous state equation of the improved generalized Lorenz system; as a result, the operation algorithm which can be appropriately realized by the microcontroller is established and folding directions of chaotic attractors and system operation modes are optional.
Description
Technical field
The present invention relates to a kind of chaotic signal generating circuit, specifically is a kind of modified model Generalized Lorenz chaotic signal generating circuit based on microcontroller.
Background technology
Chaos has disclosed the true rule and the essential characteristic of non linear system motion, has reflected the dynamic behavior of system.Because the randomlikeness of chaotic signal, continuous wide band power spectrum characteristic, chaos system are to the sensitive dependence of initial condition, and be easy to produce, be difficult to handle by time domain commonly used and frequency domain and predict and characteristics such as separate, make chaotic signal be specially adapted to fields such as secure communication and information encryption.Therefore, realizing having the chaotic signal generating circuit of different chaotic characteristics, is the focus that the researcher paid close attention to for a long time.The research of chaotic signal generating circuit also is information engineering field application needs such as communication encryption, radar communication, electronic countermeasures, cognitive radio, can be applicable to chaos phenomenon experimental demonstration, chaos system experimental verification etc. in scientific research and the teaching process.
The Cai Shi chaos circuit is most typical a kind of in numerous designs, the model of cai's circuit constitutes electronic circuit by electric capacity, inductance, resistance and Cai Shi diode to be realized, be used to produce two scrollworks or multi-scroll chaotic signals, because the discreteness of discrete electronic component is bigger, brings certain difficulty to circuit design and debugging.The chaotic signal generating circuit method for designing of domestic existing report mainly contains two classes at present: 1. utilize elements such as operational amplifier, resistance, electric capacity, constitute addition, subtraction, differential and integrating circuit, the output of realization chaotic signal, this analog circuit of forming by discrete component, parameter discrete is big, debugging is complicated, the circuit versatility is poor, is unfavorable for applying; 2. adopt digital processing technology, dimensionless state equation continuous time to chaos system carries out the discretization processing, with FPGA programmable logic device implementation algorithm, produce chaotic signal by D/A, need consume a large amount of hardware logic resources when realizing chaos algorithm, so the capacity of the precision of algorithm and logical block becomes the bottleneck of circuit design with FPGA.
Summary of the invention
Technical problem to be solved by this invention provides the chaotic signal generating circuit that a kind of reliability and stability are better, interference free performance is higher.
For solving the problems of the technologies described above, the invention provides a kind of chaotic signal generating circuit, comprising: microcontroller, signal isolation circuit, a D/A change-over circuit, the 2nd D/A change-over circuit and the 3rd D/A change-over circuit; Each D/A change-over circuit comprises one 16 shift register and one 16 DAC register, and the series connection successively of the shift register in each D/A change-over circuit, to constitute 48 bit shift register.
The serial digital signal MISO of the SPI interface output of microcontroller sends into the serial data input DATA IN of a D/A change-over circuit through signal isolation circuit
x, the clock signal SCK of described SPI interface output and latch control signal SS send into each D/A change-over circuit respectively through signal isolation circuit input end of clock CLOCK and latch control signal input LATCH are to realize distant serial synchronous telecommunications.
Described microcontroller is with three state variable x in the mathematic(al) representation of modified model Generalized Lorenz system
n, y
n, z
nDo linear transformation in proportion, make described three state variable x
n, y
n, z
nDynamic amplitude narrow down to 1/10, and carry out discretization and handle, obtain then on the basis of discretization iterative algorithm expression formula of class Lorenz system, class Chen system or class L ü system, calculate described three state variable x according to the discretization iterative algorithm expression formula of described class Lorenz system, class Chen system or class L ü system
n, y
n, z
nThe data of floating number type, then the data of this floating number type are converted to the data of integer type, with as described serial digital signal MISO output.
Whenever the clock rising edge of input end of clock CLOCK when taking place, described serial digital signal MISO is through the serial data input DATA IN of signal isolation circuit from a described D/A change-over circuit
xSerial enters described 48 bit shift register, and the 48th clock rising edge edge at input end of clock CLOCK come then, make described latch control signal input LATCH produce a rising edge edge, so that 16 bit data in 16 bit shift register in each D/A change-over circuit are loaded in the corresponding D AC register immediately, respectively organize 16 bit data then and be latched and drive digital-to-analogue conversion, thereby realize V
x, V
y, V
zThe synchronous output of chaotic signal.
Further, at the voltage signal output end V of each D/A change-over circuit
OUTBe provided with variable-gain amplification circuit, and the dynamic range of the output voltage of this variable-gain amplification circuit be 0V～+ 10V.
Further, the switch control end of described microcontroller is provided with three control switch K
0, K
1And K
2, microcontroller is by judging the logic state of each control switch, the selection of the selection of the discretization iterative algorithm pattern of realization class Lorenz system, class Chen system, class L ü system and the folding direction of chaos attractor.
The present invention has positive effect:
(1) chaotic signal generating circuit of the present invention is based on the multidimensional chaotic signal generating circuit of microcontroller, by the three-dimensional modified model Generalized Lorenz of programming realization system, adopt the Euler algorithm that the continuous state equation of modified model Generalized Lorenz system has been carried out the discretization processing, set up the operation algorithm that suitable microcontroller is realized, obtained digital circuit experiment output by software programming, and obtained and the on all four circuit output of computer artificial result, verified the feasibility that realizes chaos system based on the microcontroller digital circuit, the digital chaotic system that generates has good versatility, software portability, mentality of designing extend to design and realization general or the The high dimensional chaotic systems circuit.
(2) chaotic signal generating circuit of the present invention has following characteristics: 1. microcontroller and A/D modulus circuit adopt the SPI interface, and operating rate is fast, is applicable to the various microcontroller chips with SPI interface, the circuit highly versatile; 2. circuit modular design, simple in structure, the multidimensional simulation voltage signal is exported synchronously; 3. system is easy to expansion, the signal dimension is variable, extends to the multidimensional chaos system, can adapt to different chaos systems, as multiple wing L ü system, four-dimensional grid scrollwork hyperchaotic system, many scrollworks Colpitts chaos system etc., can produce dissimilar multidimensional chaos attractor phase rail figure; 4. with the software portable of C language design, can adapt to different chaos systems; 5. adopt digital isolator spare ADUM120, suppress system interference with high-speed cmos technology and chip-scale transformer technology; 6. the buffer circuit drive current is little, supports the microprocessor of low voltage operating, realizes level conversion by buffer circuit, with the A/D circuit interface.
(3) the present invention has provided class Lorenz system, class Chen system and class L ü system and folded the chaos attractor simulation result about under the canonical system parameter on the basis of analyzing modified model Generalized Lorenz system and folding chaos attractor characteristic thereof.On this basis, designed a general digital circuit based on microcontroller, adopt the Euler algorithm that the continuous state equation of modified model Generalized Lorenz system has been carried out the discretization processing, set up the operation algorithm that suitable microcontroller is realized, chaos attractor folding direction, system works pattern can be selected.Experiment output result and numerical simulation result are in full accord, confirmed to realize the feasibility of Generalized Lorenz system chaos circuit based on the digital circuit of microcontroller, its hardware circuit not only has versatility, and software design thinking portable, extending to the The high dimensional chaotic systems digital circuit realizes, thereby for microcontroller realize chaos synchronously and secure communication a technical support preferably is provided, for the research based on the chaos application lays the foundation.
Description of drawings
For the easier quilt of content of the present invention is clearly understood, below the specific embodiment and in conjunction with the accompanying drawings of basis, the present invention is further detailed explanation, wherein
Fig. 1 is the attractor analogous diagram of the modified model Generalized Lorenz system among the embodiment;
Fig. 2 is the circuit theory diagrams of the chaotic signal generating circuit among the embodiment;
Fig. 3 is the circuit theory diagrams of three road D/A change-over circuits in the described chaotic signal generating circuit;
Fig. 4 is the data I/O sequential of the chaotic signal generating circuit among the embodiment;
Fig. 5 is the program flow chart of the chaotic signal generating circuit among the embodiment.
Embodiment
The chaotic signal generating circuit of present embodiment comprises: microcontroller, signal isolation circuit, a D/A change-over circuit, the 2nd D/A change-over circuit and the 3rd D/A change-over circuit.
Each D/A change-over circuit comprises one 16 shift register and one 16 DAC register, and the series connection successively of the shift register in each D/A change-over circuit, to constitute 48 bit shift register; The serial digital signal MISO of the SPI interface output of microcontroller sends into the serial data input DATA IN of a D/A change-over circuit through signal isolation circuit
x, the clock signal SCK of described SPI interface output and latch control signal SS send into each D/A change-over circuit respectively through signal isolation circuit input end of clock CLOCK and latch control signal input LATCH are to realize distant serial synchronous telecommunications.Described SPI interface is serial peripheral interface.
Modified model Generalized Lorenz system, its mathematic(al) representation is as follows:
Wherein, x=[x y z]
T, λ
3∈ R, and A is one 2 * 2 real matrix
Its characteristic root (λ
1, λ
2) ∈ R, and λ 2＞λ 1＞λ 3＞0 is arranged.If it has at least one to separate and do not go to zero or infinite or limit cycle, modified model Generalized Lorenz system is also referred to as non-trivial so.
Different is that the represented modified model Generalized Lorenz system of described expression formula (1) has increased a linear term coefficient a newly with the Generalized Lorenz system
23=± 1.Coefficient a
23It is folding that the chaos attractor of described modified model Generalized Lorenz system is produced, and its folding direction depends on a
23The distinct symbols value, here a
23Be called folding factor, can prove the dynamics of folding factor being made not change after symbol switches system.
Do not have differomorphism between described modified model Generalized Lorenz system and the Generalized Lorenz system, they are topological non-equivalences.According to a in the above-mentioned expression formula (2)
12a
21,
With
System has provided classification to the autonomous Generalized Lorenz of three-dimensional.According to its sorting technique, described modified model Generalized Lorenz system is divided into class Lorenz, class Chen and class L ü chaos system, wherein, class Lorenz system satisfies: a
12a
21＞0; Class Chen system satisfies: a
12a
21＜0; Class L ü system satisfies: a
12a
21=0.Similarly, at Van
Ek and
Under the meaning, class Chen system is the dual system of class Lorenz system, and class L ü system has then represented the conversion between class Lorenz system and the class Chen system.
If a
11=a
12=a, a
21=p, a
22=q, λ
3=b.Work as p=c, during q=1, a is arranged
12a
21＞0, can derive class Lorenz system by expression formula (1); (c a) during q=c, has a as p=
12a
21＜0, can derive class Chen system by expression formula (1); Work as p=0, during q=c, a is arranged
12a
21=0, then derive class L ü system by expression formula (1).During the canonical system parameter value, modified model Generalized Lorenz system on the xz plane the right folding attractor and left folding attractor analogous diagram as shown in Figure 1.
Instruction of the every execution of microcontroller needs to consume the regular hour (instruction cycle), and control a plurality of input/output interfaces by time-sharing method, employing parallel interface mode not only is subjected to the restriction of microcontroller I/O mouth resource, and multiple signals output synchronously is difficult to handle.For the chaos system of a multidimensional, in order to realize the synchronous output of multi-channel analog voltage, independently the D/A passage, also must consider the Synchronization Control of analog output signal except considering multichannel, and with the problems such as interface of microcontroller.
Fig. 2 is three-dimensional chaos signal Synchronization output circuit structure figure, is made of microcontroller, signal isolation circuit, D/A change-over circuit etc.Microcontroller is selected the ATmega 128 with SPI serial communication interface for use, and operating rate is carried out high speed data transfer up to 50ns by SPI interface and D/A change-over circuit.Each D/A change-over circuit comprises that model is the digital to analog converter of AD420, the serial input terminal DATA of each D/A change-over circuit, clock CLOCK, latch control LATCH and join with MISO, SCK, the SS of SPI serial port respectively, realize the SPI distant serial synchronous telecommunications, maximum rate can reach 3.3Mb/s.The external a few components of AD420 just can obtain high-precision continuous analog amount output.
By the corresponding positions among the ATmega128 control register SPCR is set, can set parameters such as main frame/slave mode, data bit order of transmission, baud rate, the idle level of SCK, SCK sampling edge.When ATmega128 is set at the SPI host mode,, promptly start clock SCK, 8 bit data are moved into the D/A change-over circuit successively as long as CPU writes data to SPI data buffer SPDR.After the end of transmission, clock SCK stops, and produces interrupt identification.By interrupt routine, CPU can be with a plurality of data shifts in the D/A change-over circuit, and with deposit data in the shift register of AD420.Because the transmission buffer of SPI system has only one, CPU when sending data, must wait until that 8 bit data shifting processes are all over after, could carry out write operation to data buffer SPDR.
Comprise 16 bit shift register and 16 DAC registers in the AD420, with the shift register concatenation of x, y, z three road D/A change-over circuits, to constitute 48 bit shift register circuit, as shown in Figure 3.DATA IN
x, IN
YAnd IN
ZBe respectively the serial digital signal input of first, second and the 3rd D/A change-over circuit, OUT
x, OUT
YBe respectively the serial digital signal output of first, second D/A change-over circuit, LATCH is 16 parallel-by-bit data latching control ends, whenever CLOCK clock rising edge when taking place, data are from DATA IN
xThe end serial enters 48 bit shift register, and the data sending order is high-order first.If X
n, Y
n, Z
nBe respectively the data (16bit) of x, y, z three paths, when X is come then on the 48th CLOCK clock rising edge edge
n, Y
n, Z
nData are moved in three road AD420 shift registers successively.At this moment, latch control signal input LATCH produces a rising edge edge, and 16 bit data in each shift register are loaded in each DAC register respectively immediately, and data are latched and drive digital-to-analogue conversion, thereby realizes V
x, V
y, V
zThe synchronous output of voltage signal, data I/O sequential is seen shown in Figure 4.
Between microcontroller and each D/A change-over circuit, adopt ADUM1410 four-way digital isolator to constitute the digital signal channel isolation, improved the common mode inhibition capacity of system, guaranteed the stable output of analog signal.
Because AD420 is a single supply device, analog quantity voltage output V
OUTDynamic range have only 0V～+ 5V, in experiment in order to obtain the output of wide voltage, can be at V
OUTOutput design one-level variable-gain amplification circuit is worked as R as shown in Figure 3
f=R
1During=5k Ω, the output voltage dynamic range be extended to 0V～+ 10V.In order to satisfy the quick response of full scale 3ms, filter capacitor C
1And C
2Should select the ceramic condenser of low-dielectric, wherein C
1=0.01 μ F, C
2=0.01 μ F.
K among Fig. 2
0, K
1, K
2Be control switch,, select corresponding system parameters, realize that class Lorenz system, class Chen system, class L ü system pattern are selected and the folding direction of chaos attractor is selected by the logic state of program judgement switch, as shown in table 1.
Table 1 mode of operation is selected
| ??K 0?K 1?K 2 | Mode of operation | Function |
| ??0??0??0 | |
Class Lorenz system right folding attractor |
| ??1??0??0 | |
Class Lorenz system left folding attractor |
| ??0??0??1 | |
Class Chen system right folding attractor |
| ??1??0??1 | |
Class Chen system left folding attractor |
| ??0??1??0 | Pattern 4 | Class L ü system right folding attractor |
| ??1??1??0 | Pattern 5 | Class L ü system left folding attractor |
Continuous analog signal is realized by digital system, must carry out discretization to corresponding continuous system and handle.The discretization of the differential equation has three kinds of methods usually, i.e. Euler algorithm, improved Euler algorithm and Runge-Kutta method, and the method for these three kinds of discretizations respectively has pluses and minuses, and wherein Runge-Kutta method precision is higher.This paper has adopted the Euler algorithm that system is carried out discretization and has handled, and at first to three the state variables dos linear transformation in proportion in described modified model Generalized Lorenz system (1) formula, makes dynamic amplitude narrow down to 1/10, carries out discretization then and handles, and obtains
Wherein, x
N+1=[x
N+1y
N+1z
N+1]
T, x
n=[x
ny
nz
n]
T, h is the sampling interval.
According to algorithm (3), can obtain the discretization iterative algorithm of class Lorenz system, class Chen system or class L ü system, be respectively
Wherein: n is an iterations, a
23=± 1 is folding factor, and a, b, c are modified model Generalized Lorenz system canonical parameter.
The data of calculating according to discretization equation are the floating number type, before giving the D/A change-over circuit with data, data must be converted to integer type.Simultaneously,, analog-to-digital digital quantity must be carried out suitable linear transformation, promptly in software design, need data are changed according to the factors such as experiment effect that figure place, aanalogvoltage out-put dynamic range and the oscilloscope of D/A conversion observed phasor.If X
n, Y
n, Z
nBe respectively three state variable x
n, y
n, z
nAdjusted 16 integer type digital quantities, then
Wherein, d is chaos attractor phase rail figure center coefficient, and is relevant with the D/A converter figure place, gets d=32768; K is a proportionality coefficient, gets k=10000.Coefficient k can be passed through AVR STUDIO artificial debugging, obtains X
n, Y
n, Z
nData are not more than under 65536 the condition satisfying maximum data value, are determined by experiment.
According to algorithm (4) (5) (6) (7), can design c program based on microcontroller, by ICC AVR compiler c program is compiled then, generate the HEX run time version, carry out emulation, debugging with AVR STUDIO, its program flow diagram as shown in Figure 5, h gets 0.002.Before interative computation, at first giving three state variables is not zero initial value (x entirely
0, y
0, z
0)=(1,1,1), judge K
0, K
1, K
2On off state is determined folding direction and is selected class Lorenz system, class Chen system or class L ü system works pattern, selected iterative algorithm, and give canonical parameter a, b, c carries out iterative computation.Iterative computation adopts the double precision formats operation, carries out the numerical value conversion at last and changes into the integer type form.
Adopt Agilent DSO7032A digital oscilloscope, " Y passage " met V
zOutput, " X passage " meets V
xOutput can be observed the phase rail figure that modified model Generalized Lorenz system exports when the canonical system parameter, as shown in Figure 6 on the x z-plane.Make comparisons with modified model Generalized Lorenz system value simulation result shown in Figure 1, both results are in full accord as can be known.Simultaneously from experimental result also as can be known, modified model Generalized Lorenz system can generate folding attractor of complicated two scrollworks and the folding attractor of single scrollwork, and its folding direction can be switched by the symbol of folding factor.Evaluation in the program adopts floating number, because result of calculation only need be preserved the n time and n+1 correlations value, so the microcontroller ram space is not subjected to the restriction of iterations n, promptly system hardware resources is not influenced by n.
Obviously, the foregoing description only is for example of the present invention clearly is described, and is not to be qualification to embodiments of the present invention.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here need not also can't give exhaustive to all execution modes.And these belong to conspicuous variation or the change that spirit of the present invention extended out and still are among protection scope of the present invention.
Claims (3)
1. a chaotic signal generating circuit is characterized in that comprising: microcontroller, signal isolation circuit, a D/A change-over circuit, the 2nd D/A change-over circuit and the 3rd D/A change-over circuit;
Each D/A change-over circuit comprises one 16 shift register and one 16 DAC register, and the series connection successively of the shift register in each D/A change-over circuit, to constitute 48 bit shift register;
The serial digital signal (MISO) of the SPI interface output of microcontroller is sent into serial data input (the DATA IN of a D/A change-over circuit through signal isolation circuit
x), the clock signal (SCK) of described SPI interface output and latch control signal (SS) are sent into each D/A change-over circuit respectively through signal isolation circuit input end of clock (CLOCK) and latch control signal input (LATCH) are to realize distant serial synchronous telecommunications;
Described microcontroller is with three state variable x in the mathematic(al) representation of modified model Generalized Lorenz system
n, y
n, z
nDo linear transformation in proportion, make described three state variable x
n, y
n, z
nDynamic amplitude narrow down to 1/10, and carry out discretization and handle, obtain then on the basis of discretization iterative algorithm expression formula of class Lorenz system, class Chen system or class L ü system, calculate described three state variable x according to the discretization iterative algorithm expression formula of described class Lorenz system, class Chen system or class L ü system
n, y
n, z
nThe data of floating number type, then the data of this floating number type are converted to the data of integer type, to export as described serial digital signal (MISO);
Whenever the clock rising edge of input end of clock (CLOCK) when taking place, described serial digital signal (MISO) is through serial data input (the DATA IN of signal isolation circuit from a described D/A change-over circuit
x) serial enters described 48 bit shift register, and the 48th clock rising edge edge at input end of clock (CLOCK) come then, make described latch control signal input (LATCH) produce a rising edge edge, so that 16 bit data in 16 bit shift register in each D/A change-over circuit are loaded in the corresponding D AC register immediately, respectively organize 16 bit data then and be latched and drive digital-to-analogue conversion, thereby realize V
x, V
y, V
zThe synchronous output of chaotic signal.
2. chaotic signal generating circuit according to claim 1 is characterized in that: at the voltage signal output end (V of each D/A change-over circuit
OUT) be provided with variable-gain amplification circuit, and the dynamic range of the output voltage of this variable-gain amplification circuit be 0V～+ 10V.
3. chaotic signal generating circuit according to claim 2 is characterized in that: the switch control end of described microcontroller is provided with three control switch (K
0, K
1And K
2), microcontroller is by judging the logic state of each control switch, the selection of the selection of the discretization iterative algorithm pattern of realization class Lorenz system, class Chen system, class L ü system and the folding direction of chaos attractor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101819248A CN101834718B (en) | 2010-05-26 | 2010-05-26 | Chaotic signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101819248A CN101834718B (en) | 2010-05-26 | 2010-05-26 | Chaotic signal generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101834718A true CN101834718A (en) | 2010-09-15 |
| CN101834718B CN101834718B (en) | 2012-05-16 |
Family
ID=42718659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101819248A Active CN101834718B (en) | 2010-05-26 | 2010-05-26 | Chaotic signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101834718B (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108875218A (en) * | 2018-06-21 | 2018-11-23 | 西安交通大学 | A kind of transformer vortex field finite element solving method based on sinc function |
| CN109858191A (en) * | 2019-03-13 | 2019-06-07 | 江西理工大学 | A kind of building of generalized chaotic synchronization system and circuit design method |
| CN110928813A (en) * | 2019-11-18 | 2020-03-27 | 珠海运控电机有限公司 | System and method for outputting low-frequency synchronous signal based on double SPI |
| US20210006390A1 (en) * | 2018-03-16 | 2021-01-07 | Yanhua JIAO | Method for Generating Digital Quantum Chaotic Wavepacket Signals |
| CN113541920A (en) * | 2021-06-21 | 2021-10-22 | 中国人民解放军陆军炮兵防空兵学院 | Design method for simulating chaotic communication secret circuit |
| CN114780912A (en) * | 2022-04-06 | 2022-07-22 | Oppo广东移动通信有限公司 | Data processing apparatus and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002065721A1 (en) * | 2001-02-15 | 2002-08-22 | Massachusetts Institute Of Technology | Modulator and demodulator for lorenz-based chaotic signals |
| CN1420431A (en) * | 2002-12-12 | 2003-05-28 | 浙江大学 | Real random number generator |
| CN2594867Y (en) * | 2002-12-12 | 2003-12-24 | 浙江大学 | True random number generator |
-
2010
- 2010-05-26 CN CN2010101819248A patent/CN101834718B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002065721A1 (en) * | 2001-02-15 | 2002-08-22 | Massachusetts Institute Of Technology | Modulator and demodulator for lorenz-based chaotic signals |
| CN1420431A (en) * | 2002-12-12 | 2003-05-28 | 浙江大学 | Real random number generator |
| CN2594867Y (en) * | 2002-12-12 | 2003-12-24 | 浙江大学 | True random number generator |
Non-Patent Citations (2)
| Title |
|---|
| 《International journal of bifurcation and chaos in applied sciences and engineering》 20090831 BAOCHENG BAO, ZHONG LIU, JUEBANG YU MODIFIED GENERALIZED LORENZ SYSTEM AND FOLDED CHAOTIC ATTRACTORS 2573-2587 第19卷, 第5期 2 * |
| 《物理学报》 20090131 周武杰 禹思敏 基于现场可编程门阵列技术的混沌数字通信系统--设计与实现 113-119 第58卷, 第一期 2 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210006390A1 (en) * | 2018-03-16 | 2021-01-07 | Yanhua JIAO | Method for Generating Digital Quantum Chaotic Wavepacket Signals |
| US11509452B2 (en) * | 2018-03-16 | 2022-11-22 | Yanhua JIAO | Method for generating digital quantum chaotic wavepacket signals |
| CN108875218A (en) * | 2018-06-21 | 2018-11-23 | 西安交通大学 | A kind of transformer vortex field finite element solving method based on sinc function |
| CN108875218B (en) * | 2018-06-21 | 2020-07-28 | 西安交通大学 | Finite element solving method for transformer eddy current field based on sinc function |
| CN109858191A (en) * | 2019-03-13 | 2019-06-07 | 江西理工大学 | A kind of building of generalized chaotic synchronization system and circuit design method |
| CN109858191B (en) * | 2019-03-13 | 2023-09-26 | 江西理工大学 | Generalized chaotic synchronization system construction and circuit design method |
| CN110928813A (en) * | 2019-11-18 | 2020-03-27 | 珠海运控电机有限公司 | System and method for outputting low-frequency synchronous signal based on double SPI |
| CN113541920A (en) * | 2021-06-21 | 2021-10-22 | 中国人民解放军陆军炮兵防空兵学院 | Design method for simulating chaotic communication secret circuit |
| CN113541920B (en) * | 2021-06-21 | 2023-05-23 | 中国人民解放军陆军炮兵防空兵学院 | Design method of analog chaotic communication secret circuit |
| CN114780912A (en) * | 2022-04-06 | 2022-07-22 | Oppo广东移动通信有限公司 | Data processing apparatus and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101834718B (en) | 2012-05-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101834718B (en) | Chaotic signal generating circuit | |
| CN101789860B (en) | Chaotic signal generator | |
| Ould-Bachir et al. | A network tearing technique for FPGA-based real-time simulation of power converters | |
| CN105302956B (en) | Analogue system based on FPGA and method | |
| Benner et al. | Krylov-subspace based model reduction of nonlinear circuit models using bilinear and quadratic-linear approximations | |
| CN107169244B (en) | Electromechanical-electromagnetic transient hybrid simulation interface system and method | |
| CN109543339B (en) | Fixed admittance modeling and real-time simulation method of three-level converter | |
| CN102565751B (en) | Device for developing programmable single-phase electric energy metering chip | |
| CN114726196A (en) | Prediction decoupling control method and system for phase-shift discrete set model of TAB converter | |
| CN203149382U (en) | Virtual apparatus bus product calibration platform | |
| CN102866272A (en) | Integrated signal generator of virtual instrument integrated system for electronic measuring | |
| Amornwongpeeti et al. | A single chip FPGA-based solution for controlling of multi-unit PMSM motor with time-division multiplexing scheme | |
| CN110516276B (en) | High-frequency switch power converter real-time simulation method based on FPGA | |
| CN102004720B (en) | Variable-length fast fourier transform circuit and implementation method | |
| CN106208791A (en) | A kind of nine switching tube three brachium pontis current transformer model buildings method and devices thereof | |
| CN103490783A (en) | Method for converting analog signals into digital information | |
| CN114528794B (en) | Fractional order chaotic circuit design method based on hybrid memristor | |
| CN114185014B (en) | Parallel convolution method and device applied to radar signal processing | |
| CN110458277A (en) | The convolution hardware configuration of configurable precision suitable for deep learning hardware accelerator | |
| CN115421869A (en) | Hardware-in-loop simulation method and device based on data interaction event driving | |
| CN205281474U (en) | Quick adder of six operands on two -stage assembly line that can dispose | |
| CN103812473A (en) | Arbitrary waveform generator | |
| Esparza et al. | Real-time emulator of an induction motor: FPGA-based implementation | |
| Milton et al. | FPGA-based real-time LIM simulation of switching power converters | |
| Zhu et al. | A fully FPGA-based real-time simulator for the cascaded STATCOM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: NANTONG CHAOLI ROLLING MACHINE PRODUCING CO., LTD. Free format text: FORMER OWNER: CHANGZHOU POLYTECHNIC COLLEGE Effective date: 20150320 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 213000 CHANGZHOU, JIANGSU PROVINCE TO: 226631 NANTONG, JIANGSU PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20150320 Address after: 226631 Li Town Industrial Park, Jiangsu County, Haian Province Patentee after: Nantong Chaoli Rolling Machine Producing Co., Ltd. Address before: 213000 Jiangsu Province, Changzhou Tianning District of Tongjiang Road No. 299 Patentee before: Changzhou Polytechnic College |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20201229 Address after: 224000 Yancheng modern high end textile science and Technology Park, Jiangsu Province Patentee after: Yancheng Textile dyeing and finishing Industrial Park Industrial Development Co.,Ltd. Address before: 226631 Industrial Park, Libu Town, Hai'an County, Jiangsu Province Patentee before: Nantong Chaoli Rolling Machine Producing Co.,Ltd. |
|
| TR01 | Transfer of patent right |