CN101826469B - Coreless encapsulation substrate and manufacturing method thereof - Google Patents
Coreless encapsulation substrate and manufacturing method thereof Download PDFInfo
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- CN101826469B CN101826469B CN2009101185521A CN200910118552A CN101826469B CN 101826469 B CN101826469 B CN 101826469B CN 2009101185521 A CN2009101185521 A CN 2009101185521A CN 200910118552 A CN200910118552 A CN 200910118552A CN 101826469 B CN101826469 B CN 101826469B
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Abstract
The invention relates to a coreless encapsulation substrate and a manufacturing method thereof. The method for manufacturing the coreless encapsulation substrate comprises the following steps of: (a) providing a carrier plate and a first conducting layer, wherein the carrier plate is provided with a first surface and a second surface, and the first conducting layer is positioned on the first surface of the carrier plate; (b) forming a first built-in line on the first conducting layer; (c) forming a first dielectric layer to cover the first built-in line; (d) removing the carrier plate; (e) removing part of the first conducting layer to form at least one first welding pad; and (f) forming a first solder mask layer to cover the first built-in line and the first dielectric layer and expose the at least one first welding pad. Thus the coreless encapsulation substrate can improve the wiring density of the line, reduce the manufacturing cost and reduce the thickness of products.
Description
Technical field
The present invention relates to a kind of base plate for packaging and manufacturing approach thereof, particularly relate to a kind of coreless capsulation substrates and manufacturing approach thereof.
Background technology
With reference to figure 1 and Fig. 2, show the manufacturing approach of known package substrate.At first, core substrate 11 is provided, this core substrate 11 comprises sandwich layer 111, first line layer 112, second line layer 113 and at least one perforating holes 114.This sandwich layer 111 comprises first surface 1111 and second surface 1112.This first line layer 112 is positioned at the first surface 1111 of this sandwich layer 111.This second line layer 113 is positioned at the second surface 1112 of this sandwich layer 111.This perforating holes 114 runs through this sandwich layer 111, and electrically conduct this first line layer 112 and this second line layer 113.
Then; Form first dielectric layer 12 and second dielectric layer 13 respectively on this first line layer 112 and this second line layer 113; Wherein this first dielectric layer 12 has at least one first opening 121 to appear this first line layer 112, and this second dielectric layer 13 has at least one second opening 131 to appear this second line layer 113.Then, form first conducting metal 14 on this first dielectric layer 12 and first line layer 112 that appears, and form second conducting metal 15 on this second dielectric layer 13 and second line layer 113 that appears.At last; Carry out patterning and electroplating technology; With formation tertiary circuit layer 16 and at least one first conductive hole 17 on this first conducting metal 14, and on this second conducting metal 15, form the 4th line layer 18 and at least one second conductive hole 19, to make known package substrate 1.
The shortcoming of the manufacturing approach of this known package substrate 1 is following.This manufacturing approach is by these core substrate 11 beginnings, and it has certain thickness, so known package substrate 1 wiring density of gained is low.In addition, this core substrate 11 is accomplished endothecium structure through technologies such as boring, plating, consent, circuit moulding, makes this processing step complicated, and cost of manufacture is expensive.
Therefore, be necessary to provide a kind of coreless capsulation substrates and manufacturing approach thereof, to address the above problem.
Summary of the invention
The present invention provides a kind of coreless capsulation substrates.This substrate comprises sunken cord in first dielectric layer, first road, at least one first weld pad and first welding resisting layer.This first dielectric layer has first surface and second surface.This road of sunkening cord in first is positioned at this first dielectric layer, and is revealed in this first surface.This first weld pad is positioned on the first surface of this first dielectric layer, and electrically connects this road of sunkening cord in first.This first welding resisting layer covers the road of sunkening cord in first surface and this first of this first dielectric layer, and appears this at least one first weld pad.
The present invention provides a kind of coreless capsulation substrates in addition.This substrate comprises that the road of sunkening cord in first dielectric layer, first, at least one first weld pad, first welding resisting layer, at least one first via, at least one lamination circuit, at least one weld pad down reach welding resisting layer down.This first dielectric layer has first surface and second surface.This road of sunkening cord in first is positioned at this first dielectric layer, and is revealed in this first surface.First surface and this first that this first weld pad is positioned at this first dielectric layer sunken cord on the road, and electrically connects this road of sunkening cord in first.First surface and this first that this first welding resisting layer is positioned at this first dielectric layer sunken cord on the road, and appears this at least one first weld pad.This first via electrically connects this road of sunkening cord in first.This lamination circuit is positioned at the second surface below of this first dielectric layer, and it comprises sunken cord in lamination dielectric layer, the lamination road and at least one lamination via.This lamination dielectric layer has first surface and second surface.The road of sunkening cord in this lamination is positioned at this lamination dielectric layer, and is revealed in this first surface.This lamination via is positioned at this lamination dielectric layer, and electrically connects the road of sunkening cord in this lamination to this road of sunkening cord in first.This time weld pad is positioned at the surface of this lamination circuit, and electrically connects the lamination via of this lamination circuit.This time welding resisting layer is positioned at the surface of this lamination circuit, and appears this time weld pad.
Thus, coreless capsulation substrates of the present invention can improve line layout density, reduces cost of manufacture, and reduces product thickness.
The present invention provides a kind of manufacturing approach of coreless capsulation substrates again.This manufacturing approach may further comprise the steps: the support plate and first conductive layer (a) are provided, and this support plate has first surface and second surface, and this first conductive layer is positioned at the first surface of this support plate; (b) sunken cord the road on this first conductive layer in the formation first; (e) form first dielectric layer, to cover this road of sunkening cord in first; (d) remove this support plate; (e) remove this first conductive layer of part, to form at least one first weld pad; And (f) form first welding resisting layer, covering this sunken cord in first road and this first dielectric layer, and appear this at least one first weld pad.Wherein step (c) also comprises afterwards: (c1) form second conductive layer on this first dielectric layer; (c2) form at least one first perforate at this first dielectric layer, this first perforate runs through this second conductive layer, and appears this road of sunkening cord in first of part; Reach and (c3) form second electric conducting material in this first perforate, to form at least one first via.
Description of drawings
Fig. 1 and Fig. 2 show the sketch map of the manufacturing approach of known package substrate;
Fig. 3 to Fig. 8 shows the sketch map of manufacturing approach of first embodiment of coreless capsulation substrates of the present invention;
Fig. 9 to Figure 15 shows the sketch map of manufacturing approach of second embodiment of coreless capsulation substrates of the present invention;
Figure 16 to Figure 29 shows the sketch map of manufacturing approach of the 3rd embodiment of coreless capsulation substrates of the present invention; And
Figure 30 shows the generalized section of the 4th embodiment of coreless capsulation substrates of the present invention.
Description of reference numerals
1: the known package substrate
2: first embodiment of coreless capsulation substrates of the present invention
3: second embodiment of coreless capsulation substrates of the present invention
4: the 3rd embodiment of coreless capsulation substrates of the present invention
5: the 4th embodiment of coreless capsulation substrates of the present invention
11: 12: the first dielectric layers of core substrate
14: the first conducting metals of 13: the second dielectric layers
Conducting metal 16 in 15: the second: the tertiary circuit layer
18: the four line layers of 17: the first conductive holes
22: the first weld pads road of sunkening cord in 23: the first
25: the first welding resisting layers of 24: the first dielectric layers
27: the first vias of 26: the second weld pads
28: the second welding resisting layers road of sunkening cord in 29: the second
31: the second dielectric layers of 30: the first lamination circuits
33: the second vias of 32: the three weld pads
34: the three welding resisting layers road of sunkening cord in 35: the three
37: the four weld pads of 36: the three dielectric layers
39: the four welding resisting layers of 38: the three vias
40: the second lamination circuits 111: sandwich layer
113: the second line layers of 112: the first line layers
114: 121: the first openings of perforating holes
212: second surface 213: sandwich layer
214: the first bronze medal layer 214a: the second bronze medal layer
221: the first conductive layer 221a: lower conductiving layer
223: the second patterns of 222: the second dry films
232: the first patterns of 231: the first dry films
Electric conducting material 241 in 233: the first: first surface
242: 261: the second conductive layers of second surface
263: the three patterns of 262: the three dry films
272: the second electric conducting materials of perforate in 271: the first
311: first surface 312: second surface
The perforate in 331: the second of 321: the three conductive layers
Electric conducting material 361 in 332: the three: first surface
362: second surface 1111: first surface
1112: second surface
Embodiment
To Fig. 8, show the sketch map of manufacturing approach of first embodiment of coreless capsulation substrates of the present invention with reference to figure 3.With reference to figure 3, the support plate 21 and first conductive layer 221 are provided, this support plate 21 has first surface 211 and second surface 212, and this first conductive layer 221 is positioned at the first surface 211 of this support plate 21.In the present embodiment, this support plate 21 comprises the sandwich layer 213 and the first bronze medal layer 214, and this first bronze medal layer 214 is positioned at the surface of this sandwich layer 213, and this first conductive layer 221 covers this first bronze medal layer 214.
In the present embodiment, also comprise the second bronze medal layer 214a and lower conductiving layer 221a at the second surface 212 of this support plate 21, this second bronze medal layer 214a is corresponding with this first bronze medal layer 214, and this lower conductiving layer 221a is corresponding with this first conductive layer 221, and carries out identical technology.Thus, utilize a support plate 21 can make two coreless capsulation substrates simultaneously.At this, because the technology on this first bronze medal layer 214 and this second bronze medal layer 214a is identical, the technology of only just on this first bronze medal layer 214, being done is explained.
Generally speaking, this first conductive layer 221 is in order to protecting this first bronze medal layer 214, avoiding its scratch, yet, in the present invention, owing to have certain adhesion between this first conductive layer 221 and this first bronze medal layer 214, but but delamination.Therefore, after forming circuit on this first conductive layer 221, the interface (i.e. the first surface 211 of this support plate 21) by this first conductive layer 221 and this first bronze medal layer 214 removes this support plate 21 again, can form coreless capsulation substrates 2 (Fig. 8).Thus, remove this support plate 21 after, the surface of this first conductive layer 221 does not have residue, and this support plate 21 can be applied in other products once more.
Then, sunken cord road 23 (Fig. 5) on this first conductive layer 221 in the formation first.In the present embodiment, it is of the back to form the step on this road 23 of sunkening cord in first.With reference to figure 4, form first dry film 231 on this first conductive layer 221, and remove this first dry film 231 of part, forming first pattern 232, and appear this first conductive layer 221 of part.With reference to figure 5, electroplate first electric conducting material 233 in this first pattern 232 (Fig. 4), to form this road 23 of sunkening cord in first, then, remove this first dry film 231 (Fig. 4), last, form first dielectric layer 24, to cover this road 23 of sunkening cord in first.In other are used, form after this road 23 of sunkening cord in first, also can form brown/melanism layer (Brown/Black Oxide Layer) (not shown) again to cover this sunken cord in first road 23 and this first conductive layer 221.With reference to figure 6, remove this support plate 21 (Fig. 5).
Then, turn over turnback after, remove the part this first conductive layer 221, to form at least one first weld pad 22 (Fig. 8).In the present embodiment, the step that forms this first weld pad 22 is as back said.With reference to figure 7, form second dry film 222 on this first conductive layer 221, and remove part this second in film 222, forming second pattern 223, and appear this first conductive layer 221 of part.With reference to figure 8, this first conductive layer 221 (Fig. 7) of the part that etching appears, then; Remove this second dry film 222 (Fig. 7), to form this first weld pad 22, last; Form first welding resisting layer 25, covering this sunken cord in first road 23 and this first dielectric layer 24, and appear this at least one first weld pad 22.In other are used, also can form nickel plating/gold layer (not shown) on the surface of this first weld pad 22.
With reference to figure 8, show the generalized section of first embodiment of coreless capsulation substrates of the present invention again.This coreless capsulation substrates 2 comprises sunken cord in first dielectric layer 24, first road 23, at least one first weld pad 22 and first welding resisting layer 25.This first dielectric layer 24 has first surface 241 and second surface 242.This road 23 of sunkening cord in first is positioned at this first dielectric layer 24, and is revealed in this first surface 241.First surface 241 and this first that this first weld pad 22 is positioned at this first dielectric layer 24 sunken cord on the road 23, and electrically connects this road 23 of sunkening cord in first.First surface 241 and this first that this first welding resisting layer 25 is positioned at this first dielectric layer 24 sunken cord on the road 23, and appears this first weld pad 22.
In the present embodiment, this road 23 of sunkening cord in first is to utilize to electroplate to form, and this material of sunkening cord road 23 and this first weld pad 22 in first is a copper.In other were used, this coreless capsulation substrates 2 also comprised brown/melanism layer (Brown/Black Oxide Layer) (not shown), and it is sunken cord between the road 23 in this first dielectric layer 24 and this first.
To Figure 15, show the sketch map of manufacturing approach of second embodiment of coreless capsulation substrates of the present invention with reference to figure 9.With reference to figure 9, the support plate 21 and first conductive layer 221 are provided, this support plate 21 has first surface 211 and second surface 212, and this first conductive layer 221 is positioned at the first surface 211 of this support plate 21.With reference to Figure 10, form in first and sunken cord road 23 on this first conductive layer 221, and form first dielectric layer 24, to cover this road 23 of sunkening cord in first.In the present embodiment, form this first dielectric layer 24 after, further comprising the steps of.With reference to Figure 11, form second conductive layer 261 on this first dielectric layer 24, then; Form at least one first perforate 271 at this first dielectric layer 24; This first perforate 271 runs through this second conductive layer 261, and appears this road 23 of sunkening cord in first of part, and is last; Form second electric conducting material 272 in this first perforate 271, to form at least one first via 27.In the present embodiment, this first perforate 271 utilizes laser to form.With reference to Figure 12, remove this support plate 21 (Figure 11).
Then, turn over turnback after, remove the part this first conductive layer 221, to form at least one first weld pad 22 (Figure 14).In the present embodiment, also remove this second conductive layer 261 of part, forming at least one second weld pad 26 (Figure 14), this second weld pad 26 is electrically connected to this road 23 (Figure 14) of sunkening cord in first through this first via 27.The step that forms this first weld pad 22 and this second weld pad 26 is of the back.With reference to Figure 13; Form second dry film 222 and the 3rd dry film 262 respectively on this first conductive layer 221 and this second conductive layer 261; Then; Remove this second dry film 222 of part and part the 3rd dry film 262, forming second pattern 223 and the 3rd pattern 263, and appear this first conductive layer 221 of part and this second conductive layer 261 of part.With reference to Figure 14, this first conductive layer 221 (Figure 13) of the part that etching appears and this second conductive layer 261 (Figure 13) of part then, remove this second dry film 222 (Figure 13) and the 3rd dry film 262 (Figure 13), to form this first weld pad 22 and this second weld pad 26.
With reference to Figure 15, form first welding resisting layer 25, covering this sunken cord in first road 23 and this first dielectric layer 24, and appear this at least one first weld pad 22.In the present embodiment, also form second welding resisting layer 28, covering this first dielectric layer 24, and appear this at least one second weld pad 26.
With reference to Figure 15, show the generalized section of second embodiment of coreless capsulation substrates of the present invention again.The coreless capsulation substrates 2 (Fig. 8) of the coreless capsulation substrates 3 of present embodiment and first embodiment is roughly the same, and wherein components identical is given identical numbering.Present embodiment and first embodiment different are in this substrate 3 and also comprise at least one second weld pad 26, at least one first via 27 and second welding resisting layer 28.In the present embodiment, this second weld pad 26 is positioned on the second surface 242 of this first dielectric layer 24, and the material of this second weld pad 26 is a copper.This first via 27 is positioned at this first dielectric layer 24, electrically connect the road 23 of sunkening cord in this second weld pad 26 and this first, and the material of this first via 27 is a copper.This second welding resisting layer 28 is positioned on the second surface 242 of this first dielectric layer 24, and appears this at least one second weld pad 26.
Referring to figures 16 to Figure 29, the sketch map of the manufacturing approach of the 3rd embodiment of demonstration coreless capsulation substrates of the present invention.With reference to Figure 16, the support plate 21 and first conductive layer 221 are provided, this support plate 21 has first surface 211 and second surface 212, and this first conductive layer 221 is positioned at the first surface 211 of this support plate 21.
With reference to Figure 17, form in first and sunken cord road 23 on this first conductive layer 221.With reference to Figure 18, form first dielectric layer 24, covering this road 23 of sunkening cord in first, and form second conductive layer 261 on this first dielectric layer 24.With reference to Figure 19, form at least one first perforate 271 at this first dielectric layer 24, this first perforate 271 runs through this second conductive layer 261, and appears this road 23 of sunkening cord in first of part.This first perforate 271 utilizes laser to form.
Then, form the road 29 (Figure 22) of sunkening cord at least one first via 27 and second, its step is of the back.With reference to Figure 20, form the 3rd dry film 262 on this second conductive layer 261.With reference to Figure 21; Remove part the 3rd dry film 262; Forming the 3rd pattern 263, and appear this second conductive layer 261 of part and this first perforate 271, then; Form this second electric conducting material 272 on this second conductive layer 261 and in this first perforate 271, to form this at least one first via 27.With reference to Figure 22, remove the 3rd dry film 262 (Figure 21), appear this second conductive layer 261 of part, then, this second conductive layer 261 of the part that etching appears is to form this road 29 of sunkening cord in second.This road 29 of sunkening cord in second comprises this second conductive layer 261 and this second electric conducting material 272.Preferably, the material of this second electric conducting material 272 and this second conductive layer 261 is identical, makes that its interface is not obvious, and road 29 seems only to have one deck so this is sunken cord in second.This road 29 of sunkening cord in second is electrically connected to this road 23 of sunkening cord in first through this first via 27.
In the present embodiment, also form the first lamination circuit 30 (Figure 25), its step is of the back.With reference to Figure 23, form second dielectric layer 31, covering this road 29 of sunkening cord in second, and form the 3rd conductive layer 321 on this second dielectric layer 31.With reference to Figure 24, form at least one second perforate 331 at this second dielectric layer 31, this second perforate 331 runs through the 3rd conductive layer 321, and appears this road 29 of sunkening cord in second of part.
With reference to Figure 25, form the 3rd electric conducting material 332 in this second perforate 331, to form at least one second via 33, also form this first lamination circuit 30 simultaneously.In the present embodiment, this first lamination circuit 30 comprise the lamination dielectric layer (second dielectric layer 31, Figure 25), the road of sunkening cord in the lamination (road 29 of sunkening cord in second, Figure 25) and at least one lamination via (second via 33, Figure 25).
With reference to Figure 26, remove this support plate 21 (Figure 25), and turn over turnback, shown in figure 27.With reference to Figure 28, remove this first conductive layer 221 (Figure 27) of part, to form at least one first weld pad 22.In the present embodiment, also remove part the 3rd conductive layer 321 (Figure 27), forming weld pad (the 3rd weld pad 32) at least once, the 3rd weld pad 32 is electrically connected to this road 29 of sunkening cord in second through this second via 33.With reference to Figure 29, form first welding resisting layer 25, covering this sunken cord in first road 23 and this first dielectric layer 24, and appear this at least one first weld pad 22.In the present embodiment, also form welding resisting layer (the 3rd welding resisting layer 34) down, covering this second dielectric layer 31, and appear this at least one the 3rd weld pad 32.
In the present embodiment; Only form a laminated layer circuit (this first lamination circuit 30); Yet in other are used, after forming this first lamination circuit 30, can repeat the step of Figure 22 to Figure 25; Have the coreless capsulation substrates 5 of multilayer laminated boards circuit (the first lamination circuit 30 and the second lamination circuit 40) with formation, shown in figure 30.
With reference to Figure 29, show the generalized section of the 3rd embodiment of coreless capsulation substrates of the present invention again.This coreless capsulation substrates 4 comprises the road 23 of sunkening cord in first dielectric layer 24, first, at least one first weld pad 22, first welding resisting layer 25, at least one first via 27, at least one lamination circuit (the first lamination circuit 30), at least one weld pad (the 3rd weld pad 32) down and welding resisting layer (the 3rd welding resisting layer 34) down.
This first dielectric layer 24 has first surface 241 and second surface 242.This road 23 of sunkening cord in first is positioned at this first dielectric layer 24, and is revealed in this first surface 241.First surface 241 and this first that this first weld pad 22 is positioned at this first dielectric layer 24 sunken cord on the road 23, and electrically connects this road 23 of sunkening cord in first.First surface 241 and this first that this first welding resisting layer 25 is positioned at this first dielectric layer 24 sunken cord on the road 23, and appears this first weld pad 22.This first via 27 electrically connects this sunken cord in first road 23 and this lamination circuit (the first lamination circuit 30).
This at least one lamination circuit is positioned at second surface 242 belows of this first dielectric layer 24, and it comprises sunken cord in lamination dielectric layer, the lamination road and at least one lamination via.In the present embodiment, have only a laminated layer circuit, it is the first lamination circuit 30, and this first lamination circuit 30 comprises sunken cord in lamination dielectric layer (second dielectric layer 31), the lamination road (road 29 of sunkening cord in second) and at least one lamination via (second via 33).This second dielectric layer 31 has first surface 311 and second surface 312.This road 29 of sunkening cord in second is positioned at this second dielectric layer 31, and is revealed in this first surface 311.This second via 33 is positioned at this second dielectric layer 31, and electrically connects this road 29 of sunkening cord in second.
This time weld pad (the 3rd weld pad 32) is positioned at the surface of this first lamination circuit 30, and electrically connects second via 27 of this first lamination circuit 30.This time welding resisting layer (the 3rd welding resisting layer 34) is positioned at the surface of this first lamination circuit 30, and appears this time weld pad (the 3rd weld pad 32).
With reference to Figure 30, show the generalized section of the 4th embodiment of coreless capsulation substrates of the present invention.The coreless capsulation substrates 4 (Figure 29) of the coreless capsulation substrates 5 of present embodiment and the 3rd embodiment is roughly the same, and wherein components identical is given identical numbering.Present embodiment also comprises the second lamination circuit 40 with different being in this substrate 5 of the 3rd embodiment, and this time weld pad is the 4th weld pad 37, and this time welding resisting layer is the 4th welding resisting layer 39.
This second lamination circuit 40 is positioned at the surface of this first lamination circuit 30, and it comprises sunken cord in lamination dielectric layer (the 3rd dielectric layer 36), the lamination road (road 35 of sunkening cord in the 3rd) and at least one lamination via (the 3rd via 38).The 3rd dielectric layer 36 has first surface 361 and second surface 362.The road 35 of sunkening cord in the 3rd is positioned at the 3rd dielectric layer 36, and is revealed in this first surface 361.The 3rd via 38 is positioned at the 3rd dielectric layer 36, and electrically connects the road 35 of sunkening cord in the 3rd.This time weld pad (the 4th weld pad 37) is positioned at the surface of this second lamination circuit 40, and electrically connects the 3rd via 38 of this second lamination circuit 40.This time welding resisting layer (the 4th welding resisting layer 39) is positioned at the surface of this second lamination circuit 40, and appears this time weld pad (the 4th weld pad 37).
Thus, coreless capsulation substrates 2,3,4,5 of the present invention can improve line layout density, reduces cost of manufacture, and reduces product thickness.
The foregoing description is merely explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, persons skilled in the art are made amendment to the foregoing description and are changed and still do not take off spirit of the present invention.Interest field of the present invention should be listed like described claim.
Claims (7)
1. the manufacturing approach of a coreless capsulation substrates comprises:
(a) support plate and first conductive layer are provided, this support plate has first surface and second surface, and this first conductive layer is positioned at the first surface of this support plate;
(b) sunken cord the road on this first conductive layer in the formation first;
(c) form first dielectric layer, to cover this road of sunkening cord in first;
(d) remove this support plate;
(e) remove this first conductive layer of part, to form at least one first weld pad; And
(f) form first welding resisting layer, covering this sunken cord in first road and this first dielectric layer, and appear this at least one first weld pad,
Wherein this step (c) also comprises afterwards:
(c1) form second conductive layer on this first dielectric layer;
(c2) form at least one first perforate at this first dielectric layer, this first perforate runs through this second conductive layer, and appears this road of sunkening cord in first of part; And
(c3) form second electric conducting material in this first perforate, to form at least one first via.
2. method as claimed in claim 1, wherein this step (b) comprising:
(b1) form first dry film on this first conductive layer;
(b2) remove this first dry film of part, forming first pattern, and appear this first conductive layer of part;
(b3) electroplate first electric conducting material in this first pattern, to form this road of sunkening cord in first; And
(b4) remove this first dry film.
3. method as claimed in claim 1, wherein this step (e) comprising:
(e1) form second dry film on this first conductive layer;
(e2) remove part this second in film, forming second pattern, and appear this first conductive layer of part;
(e3) this first conductive layer of part of appearing of etching; And
(e4) remove this second dry film, to form this first weld pad.
4. method as claimed in claim 1; Wherein in this step (c3); This second electric conducting material also forms the road of sunkening cord in second on the surface of this first dielectric layer; This step (c3) also comprises the step that forms at least one lamination circuit afterwards, and wherein this lamination circuit comprises sunken cord in lamination dielectric layer, the lamination road and at least one lamination via.
5. method as claimed in claim 4, wherein this step (c3) comprising:
(c31) form the 3rd dry film on this second conductive layer;
(c32) remove part the 3rd dry film, forming the 3rd pattern, and appear this second conductive layer of part and this first perforate;
(c33) form this second electric conducting material on this second conductive layer and in this first perforate, to form this at least one first via;
(c34) remove the 3rd dry film, appear this second conductive layer of part; And
(c35) this second conductive layer of part of appearing of etching, forming this road of sunkening cord in second, this road of sunkening cord in second is electrically connected to this road of sunkening cord in first through this first via.
6. method as claimed in claim 4, wherein this step (c3) comprises afterwards:
(c4) form second dielectric layer, to cover this road of sunkening cord in second;
(c5) form the 3rd conductive layer on this second dielectric layer;
(c6) form at least one second perforate in this second dielectric layer, this second perforate runs through the 3rd conductive layer, and appears this road of sunkening cord in second of part; And
(c7) form the 3rd electric conducting material in this second perforate, to form at least one second via.
7. coreless capsulation substrates comprises:
First dielectric layer has first surface and second surface;
The road of sunkening cord in first is positioned at this first dielectric layer, and is revealed in this first surface;
At least one first weld pad, first surface and this first that is positioned at this first dielectric layer are sunken cord on the road, and electrically connect this road of sunkening cord in first;
First welding resisting layer, first surface and this first that is positioned at this first dielectric layer are sunken cord on the road, and appear this at least one first weld pad;
At least one first via is positioned at this first dielectric layer;
At least one lamination circuit is positioned at below the second surface of this first dielectric layer, and this lamination circuit comprises:
The lamination dielectric layer has first surface and second surface;
The road of sunkening cord in the lamination is positioned at this lamination dielectric layer, and is revealed in this first surface; And
At least one lamination via is positioned at this lamination dielectric layer;
At least one weld pad down is positioned at the surface of this lamination circuit, and electrically connects the lamination via of this lamination circuit; And
Following welding resisting layer is positioned at the surface of this lamination circuit, and appears this time weld pad,
Wherein this at least one first via electrically connects the road of sunkening cord in this sunken cord in first road and this lamination, and road to this time weld pad of sunkening cord in should at least one this lamination of lamination via electric connection.
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| CN2009101185521A CN101826469B (en) | 2009-03-04 | 2009-03-04 | Coreless encapsulation substrate and manufacturing method thereof |
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| CN2009101185521A CN101826469B (en) | 2009-03-04 | 2009-03-04 | Coreless encapsulation substrate and manufacturing method thereof |
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| CN101826469A CN101826469A (en) | 2010-09-08 |
| CN101826469B true CN101826469B (en) | 2012-01-11 |
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| TWI475935B (en) | 2011-07-08 | 2015-03-01 | Unimicron Technology Corp | Coreless package substrate and fabrication method thereof |
| TWI607676B (en) * | 2016-06-08 | 2017-12-01 | 矽品精密工業股份有限公司 | Package substrate and its electronic package and the manufacture thereof |
| CN113314425B (en) * | 2021-04-30 | 2023-12-26 | 珠海越亚半导体股份有限公司 | Substrate with conducting column and embedded circuit and manufacturing method thereof |
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|---|---|---|---|---|
| CN101257775A (en) * | 2007-02-28 | 2008-09-03 | 新光电气工业株式会社 | Method of manufacturing wiring substrate and method of manufacturing electronic component device |
| CN101351086A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structural technique |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101257775A (en) * | 2007-02-28 | 2008-09-03 | 新光电气工业株式会社 | Method of manufacturing wiring substrate and method of manufacturing electronic component device |
| CN101351086A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structural technique |
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