KR101510625B1 - Method for manufacturing the Embedded FPCB - Google Patents

Abstract

The present invention relates to a method for manufacturing an embedded FPCB by a new method. A chip is temporally boned to a substrate by using a flexible tape or an adhesive for temporary boning which has no effect on damage to the FPCB. The alignment connection between the pattern and terminal pad of the chip is easily performed to be fixed. After that, for electrical connection between the terminal pad of the chip and the circuit pattern of the substrate, a coordinate is adjusted when forming the circuit pattern of the substrate. The electrical connection between the terminal of the chip and the pattern of a circuit substrate is performed by a sputtering deposition method through the internal space of a via hole formed in advance. After that, the chip is electrically connected to the circuit substrate by filling the via hole by an electric plating method on the back side of the substrate. The sputtering process can be replaced with a chemical copper plating method. For this process, additional processes of masking an unnecessary part for deposition with a protection film, can be performed. Also, after a laminating process is finished, an exposing and etching process is performed on the sputtered and electroplated layer to form a circuit pattern, so that the manufacture of an embedded FPCB is finished.

Description

TECHNICAL FIELD [0001] The present invention relates to a method for manufacturing an embedded flexible printed circuit board

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an embedded flexible circuit board and a method of manufacturing the same, and more particularly, to an embedded flexible circuit board And a method of manufacturing a substrate.

With the development of information and communication technology, various electronic products such as portable information communication devices have been miniaturized and their internal circuits have become very dense, and efforts have been made to reduce the space or area occupied by circuit boards. Various research and development on a circuit board technology capable of constructing a more efficient and reliable circuit even in a technique of electrically constructing using a rigid substrate and a flexible substrate having flexibility and flexibility are continuing.

As a result, the embedded flexible printed circuit board, which embeds the chip directly on the multilayer flexible circuit board, has become very popular and has been actively developed. .

It will be appreciated that the prior arts found by the present applicant in relation to the conventional embedded flexible circuit board technologies are being searched for a very wide variety of technical directions when referring to the contents of the prior art document.

As an example of conventional prior art that can be prepared in connection with the present invention, Korean Patent Application No. 10-2008-36952 uses a method of bonding a chip to a patterned copper-clad laminate by using a diathertic film for bonding . In this prior art, it is a disadvantage that a process of attaching a carrier panel to a lower surface of a copper-clad laminate on which a chip-attached pattern is formed, and a process of removing the carrier panel after the process is completed must be accompanied.

Particularly, conventionally, a method of attaching a flat fixed panel such as an aluminum plate to the bottom of a chip-laminated copper-clad laminate, processing the process, and then removing the fixed panel has been used. Such a process can be judged to be adopted as a base technique for preventing defects in mounting a chip on a flexible flexible circuit board in performing SMT process or the like for connection between terminals.

Conventionally, in a multilayer flexible printed circuit board, a chip is embedded between an insulating film and a film, and a barrier layer is separately formed on the side for protecting the chip. To this end, a barrier layer is formed of an insulating film or an adhesive, There are many disadvantages such as a large number of processes in the process of manufacturing an embedded flexible printed circuit board and a high productivity due to the necessity of several separate processes for selective formation for the position region of the layer.

Korean Patent Application No. 10-2006-0074036

Korean Patent Application No. 10-2010-0050005

Korean Patent Application No. 10-2010-0013439

Korean Patent Application No. 10-2006-0023456

Korean Patent Application No. 10-2008-0036952

Korean Patent Application No. 10-2010-0050006

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-described problems of the prior art, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, And which can mount the chip inside the multilayer substrate without causing misalignment in the electrical connection of the microcircuit, depending on whether or not the microcircuit is electrically connected.

According to an aspect of the present invention, there is provided a method of manufacturing a flexible printed circuit board, comprising: bonding a chip to a substrate using a flexible adhesive tape or tape to such an extent that no damage is given to the flexible circuit board; A method of sputtering through an internal space of a previously formed via hole by aligning the circuit patterns of the substrate in order to establish electrical connection between the terminal pads of the chip and the circuit pattern of the substrate There is provided a new technique for completing electrically connecting a chip to a circuit board by filling a via hole by a method of electrically connecting the pattern of the circuit board to the terminal of the chip and electroplating the backside of the substrate.

Among the techniques of the present invention, the sputtering process can be substituted for the chemical copper plating process. It goes without saying that a number of ancillary processes can be accompanied, for example, by masking a portion where deposition is unnecessary for a protective film.

According to the present invention configured as described above, a via hole is formed in a circuit pattern of a portion to be electrically connected, and a conductive coating layer is formed on the terminal pad and the circuit pattern through a via hole in the lower portion to be electrically connected, The flip chip can be fixed and the effect of completely completing the electrical connection between the terminal pad and the circuit pattern in the flexible circuit board requiring the fine circuit by electroplating based on the conductive coating layer and filling the via hole with the conductive material have.

   That is, in mounting the chip having the micro gap terminal pad corresponding to the micro circuit pattern in the embedded flexible circuit board which requires the micro circuit pattern configuration, a technique of mounting the chip through the back side approach of the substrate is provided Thereby reducing the number of process steps for manufacturing an embedded substrate and reducing the number of defects as much as the number of process steps can be achieved, thereby reducing cost and product yield at the time of mass production. In addition, the present invention is more advantageous for chip mounting in a microcircuit because the electrical contact area can be made wider and more uniform than the soldering method using the conventional robot surface mounting in the electrical connection between the terminal pad gap of the fine chip and the fine circuit pattern It is effective.

In addition, the present invention is advantageous in that a plating layer for a circuit pattern that is formed naturally in the chip mounting process is formed on the opposite side, that is, the lower surface of the substrate on which the chip is mounted, thereby reducing the number of steps and cost.

1A to 1F are views showing the steps of manufacturing an embedded flexible printed circuit board according to an embodiment of the present invention in a layered cross-sectional view.
FIGS. 2A and 2B are diagrams for explaining a concept of interconnection technology of a terminal pad using a via hole of a circuit pattern in an embedded flexible printed circuit board according to an embodiment of the present invention, and a technology concept of barrier layer formation.
FIGS. 3A and 3B are cross-sectional views illustrating a layer structure of a single-layer embedded flexible circuit board and a multi-layer embedded flexible circuit board, respectively, which are free of a barrier layer according to another embodiment of the present invention.

Various process techniques of embodiments of the present invention will be described below with reference to the accompanying drawings.

≪ Embodiment 1 >

   The process of the present invention will be described in sequence as steps a) through f) so that the embodiment of the present invention is also in contrast to each of the drawings shown in particular FIGS. 1A through 1F.

   1A, a copper clad laminate (FCCL) 20 in which a copper foil layer 20b is laminated on the upper surface or the upper and lower surfaces of a polyimide layer 20a is formed as a first substrate 20 A step of forming a desired circuit pattern 22 on the upper surface of the first substrate 20 is performed,

   Step b) As shown in FIG. 1B, a through hole 24 penetrating through the circuit pattern 22a of the upper surface of the first substrate to be connected to the flip chip terminal pad 32 is formed. For reference, although the reference numeral of the first substrate is given as 20 up to the step b), since the pattern is formed on the drawing in the step after the step b), the polyimide layer 20a is used as the first substrate, You will understand.

   c) Step: As shown in Fig. 1C, the flip chip 30 is aligned so that the terminal pad 32 is superposed on the circuit pattern 22a where the through holes 24 are perforated, 20). At this time, the adhesion of the flip chip 20 to the substrate corresponds to the concept of bonding, and a thermosetting adhesive (AD) or an adhesive film (ADF) which can be cured by heat received in a subsequent process such as a hot press for multi- It is preferable to use it.

   (d) Step: As shown in Fig. 1D, a perforated trough is formed from the lower surface (back surface of the substrate) of the first substrate 20 in the direction opposite to the attaching surface of the flip chip 30 to the upper surface of the first substrate 20 The conductive coating layer 26 is formed by performing sputtering plating in such a manner that the evaporation material is allowed to approach through the holes 24 (holes in a state where the holes 24 are only formed before being coated with the via holes 24a) The pad 32 is electrically connected to the upper circuit pattern 22a of the first substrate 20 through the via hole 24a. This electrical connection is made by forming the upper sidewall of the via hole 24a and the conductive coat layer 26 of the terminal pad as shown enlarged in the drawing. For this purpose, it will be necessary to control the sputtering process conditions depending on the via hole size or the deposition material (copper, silver, gold, chromium, nickel, or alloys thereof).

   Step e) Subsequently, as shown in FIG. 1E and the enlarged view of FIG. 1E, the bottom surface of the first substrate 20 is electroplated to form a via hole 24a of the flip chip 30 to electrically connect the terminal pad 32 of the flip chip 30 to the circuit pattern 22a via the via hole 24a as a large volume, It is a constitution of the present invention and an operation and an effect therefor that the flip chip 30 is fixed by interconnection of the terminal pad 32 and the circuit pattern 22a while the terminal pad 32 is connected . If the defect inspection of the flip chip 30 is performed immediately after the completion of the step process, it is required to perform the lamination process with the multilayer circuit board before the completion of the entire process of the product It is of course possible to carry out the inspection after another subsequent process, if necessary.

   f) Subsequently, as shown in FIG. 1F, on the upper surface of the first substrate 20 on which the flip chip 30 is mounted, a separate second substrate 40-1 to n-th substrate 40 (C / L) is attached to the uppermost surface of the result of the previous step process as shown in FIG. 1G, and then the flip chip 30 The lower copper plating layer 28 formed by the step shown in FIG. 1D or the step shown in FIG. 1E is subjected to an exposure etching process on the lower surface of the mounted first substrate 20 to form a lowermost circuit pattern 28a To complete the manufacture of the multilayer embedded flexible printed circuit board.

In this embodiment of the present invention, the structure of the single layer circuit may be used instead of the multilayer circuit described in the step (f). In addition, mold packaging may be performed on the flip chip mounted on the flip chip to protect the flip chip. In such a case, it is not necessary to apply a coverlay or an insulating ink to protect the flip chip. On the contrary, when the mold is not packaged, a method such as attaching a coverlay on the flip chip or applying an insulating ink may be possible.

≪ Embodiment 2 >

   In the first embodiment, instead of sputtering, a chemical plating method is performed in which a coating layer 26 is attached through the through hole 40 from the rear surface of the polyimide layer 20a of the first substrate 20. At this time, the chemical plating is performed by a conventional chemical plating method known in the art. For this, a method of attaching and removing the coverlay to the upper surface of the first substrate 20 before and after the chemical plating is performed .

As a matter of course, in the case where the entire portion of the upper surface of the substrate or the portion where the flip chip is placed is covered and protected by the mold packaging method as described later in the first embodiment, It is possible to carry out the steps of all the embodiments of the present invention except for the second embodiment by omitting the step of attaching and detaching the coverlay. This is because, in other embodiments except for the process of the second embodiment, the flip chip is protected as a mold packaging in the description of each claim as claimed in the claims, and the flip chip is left as it is in the sputtering or chemical plating of the back surface of the first substrate The present invention can be applied not only to a process of electroplating the lower surface of the first substrate but also to a process of utilizing the same without using any other coverlay. That is, at least one of a step of covering the molding material, a step of applying insulating ink, and a step of attaching a protective film may be performed between the step c) and the step d) in order to insulate the flip chip, Or on the entire upper surface of the first substrate.

≪ Third Embodiment >

In the case of the above-described sputtering of the first embodiment or the chemical plating of the second embodiment, the following processes may be commonly included. In order to prevent damage to the unnecessary parts due to the step d), the upper surface (not shown) of the first substrate 20 having the circuit pattern including the flip chip 30 before the step d) Is insulated with a protective film (C / L) and the protective film (C / L) is removed before or after the step (e).

<Fourth Embodiment>

    In the meantime, the present invention can be applied to the first to third embodiments, including the techniques of the following fourth embodiment.

  The method may further include forming a barrier layer of copper (Cu) pattern 22b having a certain thickness surrounding the flip chip 30 at the same time as forming the circuit pattern 22a in the step a).

  A coverlay film (C / L) or a copper foil (C / L) for plating the thickness of the barrier layer copper pattern 22b thicker than the thickness of the circuit pattern 22a to be aligned with the terminal pad 32 It is sufficient to prevent the insulating film from wrinkling.

However, when the thickness of the flip chip 30 is large, it is difficult to form a desired thickness of the barrier layer copper pattern 22b. That is, referring to FIG. 2B, when the thickness of the barrier layer copper pattern 22b is reduced, the barrier layer forming height compensating film 122b is further adhered to the upper height of the flip chip, (22b + 122b) can be formed. In such a case, since the height complementary film 122b is formed in the same shape as the barrier layer plating pattern 22b, the operator can easily apply the positional application, and since the barrier layer plating pattern has a certain thickness It is possible to use it as a film or a film type double-sided tape used for a conventional flexible circuit board without newly developing a thick double-sided adhesive which is difficult to manufacture for a circuit board.

However, if the thickness of the flip chip is not so thick, it is also possible to form the barrier layer only by attaching the rectangular film 122b described above in place of the barrier layer 22b made of the copper pattern 22b.

<Fifth Embodiment>

In the above-described manufacturing method of the present invention, during the sputtering in the step d), the through hole 24 is a via hole 24a treated with a copper coating layer 26, It is possible to deposit the copper coating by sputtering again upon sputtering.

<Sixth Embodiment>

    Meanwhile, the present invention can be embodied as a multi-layer embedded flexible circuit board and a single-layer embedded flexible circuit board by a method other than the above-described method of forming the embedded flexible circuit board by forming the barrier layer.

That is, instead of using the barrier layer 22b shown in FIG. 3A, the liquid-phase interlayer insulating film 22 is formed on the entire upper surface of the first substrate 20 on which the flip chip 30 is mounted and the flip- The upper surface of the chip-mounted first substrate 20 is flattened by planarizing and hardening the LAD, and the multilayer circuit boards 40-1 and 40-n for the multi-layer flexible circuit board are formed on the planarized upper surface, Or a coverlay film (C / L) for a single-layer flexible circuit board may be attached to the substrate.

In the present invention, it is preferable that the mounted electrical connection defect inspection of the flip chip 30 is performed before the step e), and the subsequent process is carried out if there is no abnormality in inspection, and the process is carried out again from the step d) something to do.

The above-mentioned various embodiments described above are the first interconnection operations for chip mounting, in which chemical plating is performed instead of sputtering, manufacturing an embedded flexible circuit board with a single layer circuit board instead of a multilayer, It is to be understood that each of the embodiments may be commonly applied except for the alternative technical parts such as the provision of a height with an interlaminar adhesive to the peripheral space, It is to be understood that the invention is not limited to the details of the embodiments disclosed herein but is to be accorded the widest scope consistent with the spirit and scope of the invention, It should be interpreted.

20 - Substrate 22a - Circuit pattern
22b - Copper pattern for use in barrier layer 24 - Through hole
24a - via hole 26 - conductive coating layer
28 - Lower electroplating layer 28a - Lower circuit pattern
30 - Flip chip 32 - Terminal pad
40-1 to 40-n other substrates 122b - films for barrier layer applications

Claims (10)

a) forming a circuit pattern (22) on a top surface of the first substrate (20) by using a copper clad laminate (FCCL) having a copper foil laminated on the top surface or the top and bottom surfaces thereof as a first substrate (20);
b) a plurality of through holes 24 passing through the circuit pattern 22 connected to the terminal pads 32 of the flip chip 30 to be mounted on the upper surface of the first substrate 20, Perforating;
c) The terminal pads (32) of the flip chip (30) are aligned on the part of the circuit pattern (22) in which the through holes (24) are perforated so that one or more flip chips (30) Using a thermosetting adhesive or an adhesive film;
d) approaching through the perforated through hole (24) from the lower surface of the first substrate (20) in the direction opposite to the attachment surface of the flip chip (30) to the upper surface of the first substrate The bottom surface of the terminal pad 32 of the flip chip 30 and the upper circuit pattern 22 of the first substrate 20 are interposed in the vicinity of the through hole 24 by performing sputtering, Further immobilizing the attachment of the first substrate (20) of the chip (30);
e) filling a via hole (24a) formed by sputtering or chemical plating onto the inner wall of the through hole (24) by electroplating the lower surface of the first substrate (20) Completing the first substrate mounting of the flip chip by causing the terminal pad (32) of the flip chip (30) to complete the electrical connection with the circuit patterns (22) of the first substrate (20);
f) stacking the second substrate (40) to the n-th substrate (40n) on the upper surface of the first substrate (20) on which the flip chip (30) ; And
g) depositing a coverlay 210 on the top surface of the result of step f), and forming a copper copper layer 210 on the bottom surface of the first substrate 20 mounted with the flip chip 30, (28) to form a lowermost circuit pattern (28a); / RTI &gt;
In step c), the flip chip 30 is cured by the heat transferred in the subsequent processes so that the thermosetting adhesive (AD) or the adhesive film (ADF) is adhered to the first substrate 20 Is attached to the upper surface of the first substrate (20)
The upper surface of the first substrate 20 including the flip chip 30 including the flip chip 30 is covered with the protective film C (C) before the step d) to prevent damage to the unnecessary parts due to the step d) / L), and removing the protective film (C / L) before or after the step e).
a) forming a circuit pattern (22) on a top surface of the first substrate (20) by using a copper clad laminate (FCCL) having a copper foil laminated on the top surface or the top and bottom surfaces thereof as a first substrate (20);
b) a plurality of through holes 24 passing through the circuit pattern 22 connected to the terminal pads 32 of the flip chip 30 to be mounted on the upper surface of the first substrate 20, Perforating;
c) The terminal pads (32) of the flip chip (30) are aligned on the part of the circuit pattern (22) in which the through holes (24) are perforated so that one or more flip chips (30) Using a thermosetting adhesive or an adhesive film;
d) approaching through the perforated through hole (24) from the lower surface of the first substrate (20) in the direction opposite to the attachment surface of the flip chip (30) to the upper surface of the first substrate The bottom surface of the terminal pad 32 of the flip chip 30 and the upper circuit pattern 22 of the first substrate 20 are interposed in the vicinity of the through hole 24 by performing sputtering, Further immobilizing the attachment of the first substrate (20) of the chip (30);
e) filling a via hole (24a) formed by sputtering or chemical plating onto the inner wall of the through hole (24) by electroplating the lower surface of the first substrate (20) Completing the first substrate mounting of the flip chip by causing the terminal pad (32) of the flip chip (30) to complete the electrical connection with the circuit patterns (22) of the first substrate (20);
f) stacking the second substrate (40) to the n-th substrate (40n) on the upper surface of the first substrate (20) on which the flip chip (30) ; And
g) depositing a coverlay 210 on the top surface of the result of step f), and forming a copper copper layer 210 on the bottom surface of the first substrate 20 mounted with the flip chip 30, (28) to form a lowermost circuit pattern (28a); / RTI &gt;
In step c), the flip chip 30 is cured by the heat transferred in the subsequent processes so that the thermosetting adhesive (AD) or the adhesive film (ADF) is adhered to the first substrate 20 Is attached to the upper surface of the first substrate (20)
In order to insulate the flip chip, at least one of a step of covering the molding material, a step of applying the insulating ink, and a step of attaching the protective film is performed between the step c) and the step d) Or on the entire upper surface of the first substrate. &Lt; Desc / Clms Page number 20 &gt;
The semiconductor device according to claim 1 or 2, further comprising a barrier layer made of a copper (Cu) pattern 22b having a constant thickness surrounding the periphery of the flip chip 30 at the same time of forming the circuit pattern 22a in step a) Further comprising a barrier layer formed by overlaying a film layer (122b) on the top of the copper pattern (22b), the copper layer (22b) and the film layer (122b).
4. The method of claim 3, wherein the barrier layer is formed only by attaching a rectangular-shaped film (122b) in place of the barrier layer made of the copper pattern (22b).
The flip chip (30) according to any one of claims 1 to 4, wherein the flip chip (30) is inspected for electrical connection failure before the step (e) Wherein the step of forming the flexible printed circuit board comprises the steps of:
The method according to claim 1 or 2, wherein the through hole (24) in the step (d) is a via hole (24a) treated with a copper coating (24b) And the side walls are copper-coated.
 The method according to claim 3, wherein a liquid-phase interlayer insulator (LAD) is applied to the entire upper surface of the first substrate (20), which is flip-chip mounted and flip chip mounted after flip chip mounting and defect inspection, instead of using the barrier layer And a plurality of circuit boards 40-1 and 40-n are stacked on the planarized upper surface of the first substrate 20 to form a multilayer flexible circuit board, And a coverlay film (C / L) is attached to the planarized upper surface to manufacture a single-layer flexible circuit board. delete delete delete

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