CN101808343A - Automated test circuit structure and method of SIM (Subscriber Identity Module)/USIM(Universal Subscriber Identity Module) controller in ARM digital baseband chip - Google Patents
Automated test circuit structure and method of SIM (Subscriber Identity Module)/USIM(Universal Subscriber Identity Module) controller in ARM digital baseband chip Download PDFInfo
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Abstract
The invention relates to automated test circuit structure and method of a SIM/USIM controller in an ARM digital baseband chip. The structure comprises a test host, an ARM emulator, and a test circuit module carrying the ARM digital baseband chip; CLK (Clock) signal and data I/O signal pins of the SIM/USIM controller are respectively connected with a first GPIO (General Purpose Input/Output) pin and a second GPIO pin of the baseband chip; and the test host is connected with the ARM digital baseband chip through the ARM emulator. The method comprises the steps of: initiating a SIM/USIM controller register and a GPIO control register; reading the input signal value of the first GPIO pin, and detecting the CLK signal pin; configuring and driving the I/O signal pin to send a preset test data sequence; sampling and saving the input signal values on the first GPIO pin and the second GPIO pin; comparing and judging the correctness; and feeding results back to the test host. The automated test circuit structure and the method of a SIM/USIM controller in an ARM digital baseband chip have the advantages of simple and practical structure, reduced test cost, stable and reliable performance, strong portability and wider application scope.
Description
Technical field
The present invention relates to integrated circuit fields, particularly the chip testing technology field specifically is meant SIM/USIM card controller automatic test circuit structure and method in a kind of ARM digital baseband chip.
Background technology
Chip for cell phone accounts for more than 50% of mobile phone total cost, and wherein, baseband chip is a part most crucial in the mobile phone, also is the highest part of technology content.Baseband chip provides other all functions except that radio frequency.In evolution, formed the comparatively fixing chip architecture of DSP+ARM.
General arm processor is all supported the JTAG debugging at present.JTAG is the debug standard of ARM, and its notion of finally wanting is boundary scan (Boundary-Scan).The basic thought of boundary scan technique is to increase a shift register cell on the close input and output pin of chip.When chip is in debugging mode,, also can " catch " output signal on (CAPTURE) this pin by the boundary scan register that is attached thereto for the output pin of chip.Under normal running status, these boundary scan register are transparent to chip, so normal operation can not be affected.Like this, boundary scan register provides a convenient mode in order to observe and to control the chip of required debugging.
GPIO (general programmable input/output interface, General Programmable Input Output) is the signal port pin of conventional configuration in the digital baseband chip, when microcontroller or chipset do not have enough I/O ports, or when system need adopt far-end serial communication or control, the GPIO product can provide extra control and function for monitoring.
(client discerns module to SIM, Subscriber Identity Model) card is a card that includes large scale integrated circuit in inside, the card storage inside contents such as digital mobile phone client's information, encryption key, it can differentiate client identity for the GSM network, and the voice messaging the when client conversed is encrypted.Similar with SIM card, USIM (UMTS client discerns module, UMTS Subscriber Identity Module) card is to answer the requirement in 3G epoch and produce, and specific capacity is bigger mutually with SIM card, and function is abundanter.
The SIM/USIM card controller is requisite in the 3G baseband chip SIM/USIM to be controlled and the module of data interaction, and for example storage or delete telephone number, short message etc. in the SIM/USIM card is all finished by the SIM/USIM card controller.SIM and USIM are a kind of of ISO smart card,
Chip testing is a step of crucial importance in the baseband chip R﹠D process, and the quality of testing scheme greatly affects the R﹠D cycle and the R﹠D costs of chip.Good testing scheme can improve the rate of finished products of chip, shortens the R﹠D cycle, reduces R﹠D costs.As important module in the baseband chip, the testing scheme of SIM/USIM card controller also is very important.
In the prior art, all need the PCB test board of an ARM debugger, a special use, the SIM/USIM test card of a special use of needs, see also shown in Figure 1 based on the baseband chip measuring technology of ARM.Wherein have 6 control signal pins in the card outside, card controller is controlled and data interaction sticking into row by CLK and two holding wires of I/O, mutual data format sees also shown in Figure 2: the data on the I/O holding wire are arranged in order to high-order (MSB) from low level (LSB), a partial data byte comprises: 1 low level start bit, 8 bit data positions, 1 digit pair check digit, 2 position of rests (high level); CLK is the clock signal of rule; In idle condition, CLK and I/O are defaulted as high level, and low level is effective.The data interaction pattern is a semiduplex mode, and promptly synchronization can only carry out one-way data transmission (the card controller synchronization can only be received data or send out data).
See also shown in Figure 3ly again, in the scheme of above-mentioned prior art, need the special pcb board that test is special-purpose of making, buy the SIM test card of a special use.And the fabrication cycle of pcb board is long usually, and the SIM test card is also relatively more expensive, and this has just caused, and test process is more loaded down with trivial details, test period is long, testing cost is higher, has brought certain inconvenience for running smooth of test job.
Summary of the invention
The objective of the invention is to have overcome above-mentioned shortcoming of the prior art, provide a kind of do not need special-purpose PCB test board and SIM/USIM test card, simple and practical, testing process is quick automatically, test error is less, portability is strong, stable and reliable working performance, the scope of application SIM/USIM card controller automatic test circuit structure and method in the ARM digital baseband chip comparatively widely.
In order to realize above-mentioned purpose, SIM/USIM card controller automatic test circuit structure and method are as follows in the ARM digital baseband chip of the present invention:
This realizes the circuit structure based on SIM/USIM card controller automatic test in the digital baseband chip of ARM, comprise Test Host and ARM simulator, its main feature is, also comprise the test circuit module that carries the ARM digital baseband chip in the described circuit structure, the clock CLK signal pin of the SIM/USIM card controller in the described ARM digital baseband chip is connected with a GPIO pin on this ARM digital baseband chip, and the data I of this SIM/USIM card controller/O signal pin is connected with the 2nd GPIO pin on this ARM digital baseband chip, and described Test Host is connected with this ARM digital baseband chip by this ARM simulator.
This realization is connected with the jtag interface of this ARM digital baseband chip based on the ARM simulator in the circuit structure of SIM/USIM card controller automatic test in the digital baseband chip of ARM.
This realization is a PC based on the Test Host in the circuit structure of SIM/USIM card controller automatic test in the digital baseband chip of ARM.
This utilizes the method for above-mentioned circuit structure realization based on SIM/USIM card controller automatic test in the digital baseband chip of ARM, and its main feature is that described method may further comprise the steps:
(1) the ARM digital baseband chip carries out initialization process to register in the described SIM/USIM card controller and GPIO control register;
(2) the ARM digital baseband chip reads the input signal values on the described GPIO pin, detects on the described clock CLK signal pin whether clock signal is arranged;
(3) the ARM digital baseband chip disposes described SIM/USIM card controller register, and drives described data I/O signal pin and send predefined sequence of test data;
(4) the ARM digital baseband chip is sampled to the input signal values on a described GPIO pin and the 2nd GPIO pin, and the sampling test point information that obtains is carried out storage operation;
(5) the ARM digital baseband chip carries out relatively judgment processing of correctness according to the sampling test point information of a GPIO pin of being stored and the 2nd GPIO pin;
(6) result that will relatively judge returns Test Host, and finishes.
This realization may further comprise the steps based in the method for SIM/USIM card controller automatic test in the digital baseband chip of ARM register in the SIM/USIM card controller and GPIO control register being carried out initialization process:
(11) the clock CLK frequency configuration with the register in the described SIM/USIM card controller is the twice of data I/O speed;
(12) sense that the GPIO control register makes win GPIO pin and the 2nd GPIO pin is set and is set to input.
This realization may further comprise the steps based on the storage operation of carrying out in the method for SIM/USIM card controller automatic test in the digital baseband chip of ARM:
(21) in the memory block of ARM digital baseband chip, create clock sampling signal array and data I/O sampled signal array;
(22) will deposit in the described clock sampling signal array the sampled signal values that obtains of sampling of the input signal values on the GPIO pin;
(23) will deposit in described data I/O sampled signal array the sampled signal values that obtains of sampling of the input signal values on the 2nd GPIO pin.
This realization is compared judgment processing based on the correctness of carrying out in the method for SIM/USIM card controller automatic test in the digital baseband chip of ARM, may further comprise the steps:
(31) go out to take place spacing value between the adjacent actual clock sampling signal test point that level changes at being stored in sampling test point information calculations in the clock sampling signal array;
(32) go out to take place spacing value between the adjacent real data I/O sampled signal test point that level changes at being stored in sampling test point information calculations in data I/O sampled signal array;
(33), go out to take place spacing value between the adjacent theoretical clock sampling signal test point that level changes at clock sampling signal test point information calculations corresponding in the predefined sequence of test data according to the SIM/USIM host-host protocol;
(34), go out to take place spacing value between the adjacent gross data I/O sampled signal test point that level changes at data I/O sampled signal test point information calculations corresponding in the predefined sequence of test data according to the SIM/USIM host-host protocol;
(35) spacing value between the described adjacent actual clock sampling signal test point is compared with spacing value between the corresponding adjacent theoretical clock sampling signal test point, simultaneously spacing value between the described adjacent real data I/O sampled signal test point and the spacing value between the adjacent theoretical clock sampling signal test point are compared;
(36) if comparative result in default reasonable error scope, then the result is correct; Otherwise the result is a mistake.
Adopted SIM/USIM card controller automatic test circuit structure and method in the ARM digital baseband chip of this invention, because its general GPIO pin that is carried based on the ARM digital baseband chip, the arm processor that has utilized the ARM digital baseband chip to be carried simultaneously, directly test code is imported in this ARM digital baseband chip by jtag interface by the ARM simulator, and allow this ARM digital baseband chip automatically perform test code, and output test result, thereby realized the automatic test of SIM/USIM controller, special-purpose PCB beta version and SIM/USIM test card have been saved, not only simple and practical, and saved testing cost, and make the testing process full-automation, simplify testing process, shortened the cycle of test; Simultaneously since the sampling clock of ARM digital baseband chip usually all at dozens or even hundreds of megahertz, thereby guaranteed the high accuracy of sampled data, stable and reliable working performance, and test code only needs to revise a little, just can conveniently be transplanted on the different hardware platforms, thereby obtained comparatively desirable portability, the scope of application is comparatively extensive, for further developing of digital baseband chip measuring technology established solid foundation.
Description of drawings
Fig. 1 is a SIM/USIM card test pin schematic diagram of the prior art.
Fig. 2 is a SIM/USIM card data format schematic diagram of the prior art.
Fig. 3 is the composition schematic diagram of SIM/USIM card controller test platform of the prior art.
Fig. 4 is a SIM/USIM card controller automatic test electrical block diagram in the ARM digital baseband chip of the present invention.
Fig. 5 is the overall flow figure of SIM/USIM card controller automated testing method in the ARM digital baseband chip of the present invention.
Fig. 6 is a data sampling schematic diagram in the SIM/USIM card controller automated testing method in the ARM digital baseband chip of the present invention.
Embodiment
In order more to be expressly understood technology contents of the present invention, describe in detail especially exemplified by following examples.
See also shown in Figure 4, this realizes the circuit structure based on SIM/USIM card controller automatic test in the digital baseband chip of ARM, comprise Test Host and ARM simulator, wherein, also comprise the test circuit module that carries the ARM digital baseband chip in the described circuit structure, the clock CLK signal pin of the SIM/USIM card controller in the described ARM digital baseband chip is connected with a GPIO pin on this ARM digital baseband chip, and the data I of this SIM/USIM card controller/O signal pin is connected with the 2nd GPIO pin on this ARM digital baseband chip, and described Test Host is connected with this ARM digital baseband chip by this ARM simulator.
Wherein, described ARM simulator can be connected with the jtag interface of this ARM digital baseband chip, moreover, can also be connected by other suitable data coffret; This Test Host can be PC simultaneously, also can have the equipment such as Industry Control single-chip microcomputer of test controlled function for other.
In the middle of reality is used, because the SIM/USIM card controller has two signal pins: clock CLK and data I/O.Data interactive mode is a semiduplex mode.Data interaction speed on the I/O signal is generally between 10～100kbit/s, and message transmission rate is slower, and clock CLK is generally 372 times of I/O speed.Common baseband chip all can carry GPIO and use for the user.
In circuit structure of the present invention, use two GPIO to link to each other with CLK, I/O, by the value on the sampling GPIO,, verify the correctness of CLK and I/O signal, thereby reach the purpose of test SIM/USIM card controller in conjunction with SIM/USIM card host-host protocol among the 3GPP.
In the circuit structure of Fig. 4, technical scheme of the present invention in fact only needs the baseband chip that a Daepori leads to PC, an ARM simulator, a pedestal and a band ARM to get final product.Do not need special PCB test board and SIM test card.
Because chip carries arm processor, support the JTAG debug standard, therefore just can test code (C language or ARM assembler language) be poured in the baseband chip by the JTAG mouth by the ARM simulator, so just can observe and debug all functions of baseband chip.By this method, only need to allow chip automatically perform, output test result at the PC end at last, so just realized the automatic test of SIM/USIM controller at PC end input test routine.
Because the sampling clock of general baseband chip is usually all about dozens or even hundreds of megahertz, the hundred times of SIM/USIM card transmission rate, in a bit data length of SIM/USIM card, the GPIO mouth generally can be sampled many times, so the accuracy height of sampled data.
See also shown in Figure 5ly again, this utilizes above-mentioned circuit structure to realize may further comprise the steps method based on SIM/USIM card controller automatic test in the digital baseband chip of ARM:
(1) the ARM digital baseband chip carries out initialization process to register in the described SIM/USIM card controller and GPIO control register, may further comprise the steps:
(a) the clock CLK frequency configuration with the register in the described SIM/USIM card controller is the twice of data I/O speed;
(b) sense that the GPIO control register makes win GPIO pin and the 2nd GPIO pin is set and is set to input;
(2) the ARM digital baseband chip reads the input signal values on the described GPIO pin, detects on the described clock CLK signal pin whether clock signal is arranged;
(3) the ARM digital baseband chip disposes described SIM/USIM card controller register, and drives described data I/O signal pin and send predefined sequence of test data;
(4) the ARM digital baseband chip is sampled to the input signal values on a described GPIO pin and the 2nd GPIO pin, and the sampling test point information that obtains is carried out storage operation, may further comprise the steps:
(a) in the memory block of ARM digital baseband chip, create clock sampling signal array and data I/O sampled signal array;
(b) will deposit in the described clock sampling signal array the sampled signal values that obtains of sampling of the input signal values on the GPIO pin;
(c) will deposit in described data I/O sampled signal array the sampled signal values that obtains of sampling of the input signal values on the 2nd GPIO pin;
(5) the ARM digital baseband chip carries out relatively judgment processing of correctness according to the sampling test point information of a GPIO pin of being stored and the 2nd GPIO pin, may further comprise the steps:
(a) go out to take place spacing value between the adjacent actual clock sampling signal test point that level changes at being stored in sampling test point information calculations in the clock sampling signal array;
(b) go out to take place spacing value between the adjacent real data I/O sampled signal test point that level changes at being stored in sampling test point information calculations in data I/O sampled signal array;
(c), go out to take place spacing value between the adjacent theoretical clock sampling signal test point that level changes at clock sampling signal test point information calculations corresponding in the predefined sequence of test data according to the SIM/USIM host-host protocol;
(d), go out to take place spacing value between the adjacent gross data I/O sampled signal test point that level changes at data I/O sampled signal test point information calculations corresponding in the predefined sequence of test data according to the SIM/USIM host-host protocol;
(e) spacing value between the described adjacent actual clock sampling signal test point is compared with spacing value between the corresponding adjacent theoretical clock sampling signal test point, simultaneously spacing value between the described adjacent real data I/O sampled signal test point and the spacing value between the adjacent theoretical clock sampling signal test point are compared;
(f) if comparative result in default reasonable error scope, then the result is correct; Otherwise the result is a mistake;
(6) result that will relatively judge returns Test Host, and finishes.
In the middle of reality is used, with circuit structure of the present invention connect finish after, just can be at PC end editor and modification test code (C language or ARM assembler language).After compiling is passed through, test code is poured in the baseband chip from jtag interface by the ARM simulator.Based on the debug standard of ARM JTAG, just can dispose and read any register in the chip, comprise SIM/USIM controller and GPIO controller.After like this test code being poured into baseband chip, chip can automatically perform instructions, outputs test result at the PC end at last.
Testing process of the present invention is divided into five steps.
● the first step: initialization SIM/USIM card controller register and GPIO control register.
● second step: read the value of GPIO0, detect on the CLK whether clock signal is arranged.
● the 3rd step: dispose SIM/USIM card controller register, send the data of fixed sequence program by I/O.
● the 4th step: the value of sampling GPIO0 and GPIO1, and deposit array CLK[respectively in], I/O[] in.
● the 5th step: whether the array value that calculates GPIO0 and GPIO1 is correct.
(1) at initial period, initialization SIM/USIM and GPIO control register are provided with every functional parameter.With the CLK frequency configuration of SIM/USIM control register is the twice of I/O, and GPIO0 and GPIO1 direction are set to input, so just can obtain the value of CLK and I/O signal by sampling GPIO0 and GPIO1.
(2) behind first step initialization SIM/USIM control register, CLK can send the clock signal of a fixed frequency, and the level upset of clock signal is frequent.Because GPIO0 links to each other with CLK,, see if there is variation (0 becomes 1 or 1 becomes 0) and just can learn whether clock is arranged so go on foot the input value that only need read GPIO0 second.
In (3) the 3rd steps, configuration SIM/USIM card controller register makes and sends the one piece of data sequence on the I/O.
In (4) the 4th steps, read the input value (data on promptly sample CLK and the I/O) of GPIO0 and GPIO1 constantly at T0, and deposit array CLK[continuously in] and I/O[] in.At two complete CLK in the clock cycle, GPIO0 and the GPIO1 number of times sampling (different hardware test platform sampling numbers have difference slightly) that can fix.
See also shown in Figure 6ly, suppose that a certain hardware platform can fixed sample in the clock cycle 6 times at two continuous CLK, can obtain following two groups of sampled datas so:
CLK[]＝{1，1，0，0，1，1，0，0}，I/O[]＝{1，1，1，1，0，0，0，0}。
(5) the 5th steps, CLK that the observation previous step obtains and the sampled value of I/O, CLK changes the 1st, 3,5,7 test point as can be known, and I/O changes the 1st, 5 test point.Can obtain other a pair of array thus, i.e. spacing value between the test point that changes of numerical value:
CLK_DURATION[]＝{2，2，2}——(3-1，5-3，7-5)
I/O_DURATION[]＝{4}——(5-1)。
Because the SIM/USIM host-host protocol is fixed, and the data sequence that sends is controlled, so just can calculated in advance go out the interval between the test point that CLK and I/O signal change, and and the actual test point that changes between the interval compare, just can verify that CLK and I/O go up the correctness of data, thus the function of checking SIM/USIM card controller.
Illustrate as follows:
Suppose that it is 0X55 that I/O goes up the data sequence that sends.According to the SIM/USIM card host-host protocol shown in Fig. 2, in above the 4th step,, obtain two groups of sampling arrays by reading the input value of GPIO0 and GPIO1:
CLK[]＝{1，1，0，0，1，1，0，0，1，1，0，0，1，1，0，0，1，1，0，0，1，1，0，0}；
I/O[]＝{0，0，0，0，1，1，1，1，0，0，0，0，1，1，1，1，0，0，0，0，1，1，1，1，0，0，0，0，1，1，1，1，0，0，0，0，0，0，0，0，1，1，1，1，1，1，1，1}。
In above the 5th step, by calculating CLK[] and I/O[], just can obtain the spacing value between the test point that CLK and I/O signal change:
CLK_DURATION[]＝{2，2，2，2，2，2，2，2，2，2，2，2}；
I/O_DURATION＝{4，4，4，4，4，4，4，4，8，8}。
With CLK_DURATION[] and I/O_DURATION[] the correct result that goes out with calculated in advance compares, if in the reasonable error scope, it is correct to show test results, if exceed, shows mistake.
Simultaneously because the CLK frequency is the twice of I/O, so the minimum interval value of I/O should be the twice of CLK minimum interval value, by this multiple relation, therefore can verify the accuracy of CLK and I/O signal frequency again, the function correctness of checking SIM/USIM card controller register.
In the above-mentioned testing process, it is not 0 to be exactly the characteristics of 1 value that the 4th step and the 5th wherein goes on foot the input value utilized GPIO cleverly, thereby has realized the function of verification of correctness.
The ardware feature of different PC, ARM simulator and baseband chip is different, actual minimum interval value can be different, promptly at two continuous CLK in the clock cycle, the hardware platform GPIO that has can read 6 times, what have can only read 5 times, but spacing value necessarily becomes the multiple relation, according to this characteristic, test program of the present invention only need be revised the minimum interval value, arrives different hardware test platforms with regard to portable.
SIM/USIM card controller automatic test circuit structure and method in the above-mentioned ARM digital baseband chip have been adopted, because its general GPIO pin that is carried based on the ARM digital baseband chip, the arm processor that has utilized the ARM digital baseband chip to be carried simultaneously, directly test code is imported in this ARM digital baseband chip by jtag interface by the ARM simulator, and allow this ARM digital baseband chip automatically perform test code, and output test result, thereby realized the automatic test of SIM/USIM controller, special-purpose PCB beta version and SIM/USIM test card have been saved, not only simple and practical, and saved testing cost, and make the testing process full-automation, simplify testing process, shortened the cycle of test; Simultaneously since the sampling clock of ARM digital baseband chip usually all at dozens or even hundreds of megahertz, thereby guaranteed the high accuracy of sampled data, stable and reliable working performance, and test code only needs to revise a little, just can conveniently be transplanted on the different hardware platforms, thereby obtained comparatively desirable portability, the scope of application is comparatively extensive, for further developing of digital baseband chip measuring technology established solid foundation.
In this specification, the present invention is described with reference to its certain embodiments.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (7)
1. a realization is based on the circuit structure of SIM/USIM card controller automatic test in the digital baseband chip of ARM, comprise Test Host and ARM simulator, it is characterized in that, also comprise the test circuit module that carries the ARM digital baseband chip in the described circuit structure, the clock CLK signal pin of the SIM/USIM card controller in the described ARM digital baseband chip is connected with a GPIO pin on this ARM digital baseband chip, and the data I of this SIM/USIM card controller/O signal pin is connected with the 2nd GPIO pin on this ARM digital baseband chip, and described Test Host is connected with this ARM digital baseband chip by this ARM simulator.
2. realization according to claim 1 is characterized in that based on the circuit structure of SIM/USIM card controller automatic test in the digital baseband chip of ARM described ARM simulator is connected with the jtag interface of this ARM digital baseband chip.
3. realization according to claim 1 and 2 is characterized in that based on the circuit structure of SIM/USIM card controller automatic test in the digital baseband chip of ARM described Test Host is a PC.
4. one kind is utilized the described circuit structure of claim 1 to realize method based on SIM/USIM card controller automatic test in the digital baseband chip of ARM it is characterized in that described method may further comprise the steps:
(1) the ARM digital baseband chip carries out initialization process to register in the described SIM/USIM card controller and GPIO control register;
(2) the ARM digital baseband chip reads the input signal values on the described GPIO pin, detects on the described clock CLK signal pin whether clock signal is arranged;
(3) the ARM digital baseband chip disposes described SIM/USIM card controller register, and drives described data I/O signal pin and send predefined sequence of test data;
(4) the ARM digital baseband chip is sampled to the input signal values on a described GPIO pin and the 2nd GPIO pin, and the sampling test point information that obtains is carried out storage operation;
(5) the ARM digital baseband chip carries out relatively judgment processing of correctness according to the sampling test point information of a GPIO pin of being stored and the 2nd GPIO pin;
(6) result that will relatively judge returns Test Host, and finishes.
5. realization according to claim 4 is based on the method for SIM/USIM card controller automatic test in the digital baseband chip of ARM, it is characterized in that, described register in the SIM/USIM card controller and GPIO control register are carried out initialization process, may further comprise the steps:
(11) the clock CLK frequency configuration with the register in the described SIM/USIM card controller is the twice of data I/O speed;
(12) sense that the GPIO control register makes win GPIO pin and the 2nd GPIO pin is set and is set to input.
6. realization according to claim 4 is characterized in that based on the method for SIM/USIM card controller automatic test in the digital baseband chip of ARM the described storage operation of carrying out may further comprise the steps:
(21) in the memory block of ARM digital baseband chip, create clock sampling signal array and data I/O sampled signal array;
(22) will deposit in the described clock sampling signal array the sampled signal values that obtains of sampling of the input signal values on the GPIO pin;
(23) will deposit in described data I/O sampled signal array the sampled signal values that obtains of sampling of the input signal values on the 2nd GPIO pin.
7. realization according to claim 6 is characterized in that based on the method for SIM/USIM card controller automatic test in the digital baseband chip of ARM the described relatively judgment processing of correctness of carrying out may further comprise the steps:
(31) go out to take place spacing value between the adjacent actual clock sampling signal test point that level changes at being stored in sampling test point information calculations in the clock sampling signal array;
(32) go out to take place spacing value between the adjacent real data I/O sampled signal test point that level changes at being stored in sampling test point information calculations in data I/O sampled signal array;
(33), go out to take place spacing value between the adjacent theoretical clock sampling signal test point that level changes at clock sampling signal test point information calculations corresponding in the predefined sequence of test data according to the SIM/USIM host-host protocol;
(34), go out to take place spacing value between the adjacent gross data I/O sampled signal test point that level changes at data I/O sampled signal test point information calculations corresponding in the predefined sequence of test data according to the SIM/USIM host-host protocol;
(35) spacing value between the described adjacent actual clock sampling signal test point is compared with spacing value between the corresponding adjacent theoretical clock sampling signal test point, simultaneously spacing value between the described adjacent real data I/O sampled signal test point and the spacing value between the adjacent theoretical clock sampling signal test point are compared;
(36) if comparative result in default reasonable error scope, then the result is correct; Otherwise the result is a mistake.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910046161 CN101808343B (en) | 2009-02-13 | 2009-02-13 | Automated test circuit structure and method of SIM (Subscriber Identity Module)/USIM(Universal Subscriber Identity Module) controller in ARM digital baseband chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910046161 CN101808343B (en) | 2009-02-13 | 2009-02-13 | Automated test circuit structure and method of SIM (Subscriber Identity Module)/USIM(Universal Subscriber Identity Module) controller in ARM digital baseband chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101808343A true CN101808343A (en) | 2010-08-18 |
| CN101808343B CN101808343B (en) | 2013-11-06 |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101907683A (en) * | 2009-06-02 | 2010-12-08 | 上海摩波彼克半导体有限公司 | Automatic circuit testing structure of I2C module in digital baseband chip and method thereof |
| CN105827333A (en) * | 2015-01-07 | 2016-08-03 | 展讯通信（上海）有限公司 | System and method of baseband chip automatic test |
| CN106546900A (en) * | 2016-09-13 | 2017-03-29 | 芯海科技（深圳）股份有限公司 | One kind realizes automated testing method by CodeOption |
| WO2017166153A1 (en) * | 2016-03-31 | 2017-10-05 | Intel Corporation | Technologies for error handling for high speed i/o data transfer |
| CN110320460A (en) * | 2018-03-29 | 2019-10-11 | 北京华虹集成电路设计有限责任公司 | A kind of method and apparatus of SIM card robustness testing |
| CN111352025A (en) * | 2020-03-13 | 2020-06-30 | 京微齐力(深圳)科技有限公司 | Method, system and equipment for verifying configuration controller in FPGA (field programmable Gate array) |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2859959Y (en) * | 2005-12-20 | 2007-01-17 | 华为技术有限公司 | User tag card recognition device in wireless communication system |
| CN101022634A (en) * | 2007-03-16 | 2007-08-22 | 烟台麦特电子有限公司 | Testing method based on remote control vehicular device |
| US7265570B2 (en) * | 2001-09-28 | 2007-09-04 | Inapac Technology, Inc. | Integrated circuit testing module |
| US20080145803A1 (en) * | 2004-01-23 | 2008-06-19 | Aos Holding Company | Apparatus and method of detecting igniter type |
| CN201114647Y (en) * | 2007-09-04 | 2008-09-10 | 宁波金信通讯技术有限公司 | An automatic dialing and detection instruction for SIM card remote control |
-
2009
- 2009-02-13 CN CN 200910046161 patent/CN101808343B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7265570B2 (en) * | 2001-09-28 | 2007-09-04 | Inapac Technology, Inc. | Integrated circuit testing module |
| US20080145803A1 (en) * | 2004-01-23 | 2008-06-19 | Aos Holding Company | Apparatus and method of detecting igniter type |
| CN2859959Y (en) * | 2005-12-20 | 2007-01-17 | 华为技术有限公司 | User tag card recognition device in wireless communication system |
| CN101022634A (en) * | 2007-03-16 | 2007-08-22 | 烟台麦特电子有限公司 | Testing method based on remote control vehicular device |
| CN201114647Y (en) * | 2007-09-04 | 2008-09-10 | 宁波金信通讯技术有限公司 | An automatic dialing and detection instruction for SIM card remote control |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101907683B (en) * | 2009-06-02 | 2013-05-08 | 上海摩波彼克半导体有限公司 | Automatic circuit testing structure of I2C module in digital baseband chip and method thereof |
| CN101907683A (en) * | 2009-06-02 | 2010-12-08 | 上海摩波彼克半导体有限公司 | Automatic circuit testing structure of I2C module in digital baseband chip and method thereof |
| CN105827333A (en) * | 2015-01-07 | 2016-08-03 | 展讯通信（上海）有限公司 | System and method of baseband chip automatic test |
| US11093313B2 (en) | 2016-03-31 | 2021-08-17 | Intel Corporation | Technologies for error handling for high speed I/O data transfer |
| WO2017166153A1 (en) * | 2016-03-31 | 2017-10-05 | Intel Corporation | Technologies for error handling for high speed i/o data transfer |
| CN106546900A (en) * | 2016-09-13 | 2017-03-29 | 芯海科技（深圳）股份有限公司 | One kind realizes automated testing method by CodeOption |
| CN106546900B (en) * | 2016-09-13 | 2019-04-16 | 芯海科技（深圳）股份有限公司 | One kind realizing automated testing method by CodeOption |
| CN110320460A (en) * | 2018-03-29 | 2019-10-11 | 北京华虹集成电路设计有限责任公司 | A kind of method and apparatus of SIM card robustness testing |
| CN111352025A (en) * | 2020-03-13 | 2020-06-30 | 京微齐力(深圳)科技有限公司 | Method, system and equipment for verifying configuration controller in FPGA (field programmable Gate array) |
| CN111352025B (en) * | 2020-03-13 | 2020-12-11 | 京微齐力(深圳)科技有限公司 | Method, system and equipment for verifying configuration controller in FPGA (field programmable Gate array) |
| CN111596196A (en) * | 2020-05-14 | 2020-08-28 | 成都思科瑞微电子股份有限公司 | Graphic processing chip GPU parameter testing device |
| CN114297104A (en) * | 2021-12-30 | 2022-04-08 | 高新兴物联科技有限公司 | Debugging data transmission method, device, equipment and storage medium |
| CN114297104B (en) * | 2021-12-30 | 2023-08-18 | 高新兴物联科技股份有限公司 | Debug data transmission method, device, equipment and storage medium |
| CN116224042A (en) * | 2023-04-28 | 2023-06-06 | 北京壁仞科技开发有限公司 | Method, system, apparatus and medium for generating test vector for testing device under test |
| CN116224042B (en) * | 2023-04-28 | 2023-08-29 | 北京壁仞科技开发有限公司 | Method, system, apparatus and medium for generating test vector for testing device under test |
| CN117251329A (en) * | 2023-11-17 | 2023-12-19 | 深圳市耀星微电子有限公司 | DRAM test equipment and method based on ARM architecture processor |
| CN117251329B (en) * | 2023-11-17 | 2024-03-08 | 深圳市耀星微电子有限公司 | DRAM test equipment and method based on ARM architecture processor |
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