CN115291082B

CN115291082B - Efficient test method and device for chip and storage medium

Info

Publication number: CN115291082B
Application number: CN202210931958.7A
Authority: CN
Inventors: 李鹏飞; 李建强; 葛亚山; 任丽姣
Original assignee: Beijing Jinghanyu Electronic Engineering Technology Co ltd
Current assignee: Beijing Jinghanyu Electronic Engineering Technology Co ltd
Priority date: 2022-08-04
Filing date: 2022-08-04
Publication date: 2023-06-13
Anticipated expiration: 2042-08-04
Also published as: CN115291082A

Abstract

The present application relates to the field of integrated circuit testing, and in particular, to a method, apparatus, and storage medium for efficient testing of chips. The high-efficiency test method of the chip comprises the following steps: acquiring data: acquiring a plurality of download files in a computer terminal; analysis: analyzing a plurality of downloaded files based on a preset algorithm, and obtaining a test program; performing a test: and starting testing the chip to be tested based on a plurality of testing programs. The test device has the effect of improving the overall working efficiency when testing the chip.

Description

Efficient test method and device for chip and storage medium

Technical Field

The present application relates to the field of integrated circuit testing, and in particular, to a method, apparatus, and storage medium for efficient testing of chips.

Background

Currently, a very large scale integrated circuit, such as CPLD, FPGA, MCU, generally integrates a JTAG protocol for on-line debugging and downloading functions of a chip, and when secondary screening is performed on the above type of devices, a certain functional program is generally developed by using special software developed by a manufacturer of the corresponding product, then burning data is generated, a loader manufactured by the corresponding factory is used for burning through a JTAG interface, and then testing is performed on an ATE (automatic test equipment) machine according to the corresponding functional program.

The inventor considers that when testing a certain function of a chip, the specific burner of a manufacturer needs to be used for burning once, after the test passes through the current function, the second burning is carried out, and then the test is carried out on an ATE machine table for the second burning, so the test is repeated repeatedly, and the process efficiency is lower and the operation is complex.

Disclosure of Invention

In order to improve the overall working efficiency when testing chips, the application provides a high-efficiency testing method, device and storage medium for chips.

In a first aspect, the method for testing chips efficiently provided in the present application adopts the following technical scheme:

the high-efficiency test method of the chip comprises the following steps:

acquiring data: acquiring a plurality of download files in a computer terminal;

analysis: analyzing a plurality of downloaded files based on a preset algorithm, and obtaining a test program;

performing a test: and starting testing the chip to be tested based on a plurality of testing programs.

By adopting the technical scheme: when downloading the test program, downloading all the test programs to be executed in the batch at one time; after batch analysis, the ATE machine can detect the corresponding function of the current chip to be tested once according to a plurality of test programs, so that the repeated downloading of the test programs during testing the chip is reduced, and the overall working efficiency during testing the chip is improved.

Optionally, the step of performing the test further includes the steps of:

adding test items to a plurality of test programs one by one based on a preset sequence;

and the test items correspond to different test functions.

By adopting the technical scheme, as the functions to be tested of the chip are more, a plurality of test programs can test different functions of the chip, so that test items are added to each test program, the later matching of test results and the convenience in calling any test program can be facilitated, and the working efficiency of chip test is improved.

Optionally, the step of sending the plurality of analyzed test programs one by one according to a preset sequence specifically includes the following steps:

acquiring a position to be added in an ATE machine test program;

and adding a corresponding test program to the position to be added.

By adopting the technical scheme, a plurality of test programs are added to the corresponding positions of the ATE machine at one time, and when the ATE machine starts to test the chip, the functions of the tested chip can be tested at one time, so that the coverage rate of the tested chip is improved.

Optionally, the step of acquiring data further includes the steps of:

the ATE board is modeled as a JTAG downloader.

By adopting the technical scheme, when the downloaded file is acquired in the computer end, if the ATE machine is used for simulating the JTAG downloader to directly execute the downloading action, the step of executing the downloading action by using the special downloader can be reduced, the time for downloading, plate changing and machine changing test programs is saved, and the working efficiency of the test chip is further improved.

Optionally, the step of simulating the ATE machine into the JTAG downloader specifically includes the following steps:

acquiring a download waveform, wherein the download waveform is acquired by a logic analyzer;

analyzing the subcarrier shape and converting the subcarrier shape into a graphic file which can be identified by an ATE machine;

and adding the graphic file to a corresponding position in an ATE machine table.

By adopting the technical scheme, the ATE machine can simulate the JTAG downloader to download programs to the tested chip and test the tested chip at the same time, so that the working efficiency of the ATE machine when executing test functions to the tested chip is improved.

Optionally, the step of performing the test further includes the steps of:

calculating the time of signal inversion;

and matching the signal overturning time of the ATE machine table and the chip to be tested to be consistent.

By adopting the technical scheme, when the ATE machine station tests the chips, the stability of the bidirectional connection between the ATE machine station and the chips to be tested is ensured, so that the overall working efficiency of the ATE machine station when the test chips correspond to the functions is improved.

Optionally, the step of performing the test specifically further includes the steps of:

calculating the circulation times T;

converting the plurality of subcarrier shapes into test vectors one by one;

and circularly transmitting the test vectors to the chip to be tested for T times.

By adopting the technical scheme, the test vector is transmitted to the chip to be tested in a round-robin manner, so that the signal turnover time of the chip to be tested in the ATE machine is the same as that of the signal turnover time of the chip to be tested, and the ATE machine can start to execute corresponding test actions; so that the test function of the chip can be started after the downloaded file is downloaded, and the overall working efficiency of the ATE machine platform when the test chip corresponds to the function is improved.

In a second aspect, the present application provides a computer apparatus, which adopts the following technical scheme:

computer apparatus comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, the processor implementing the method of efficient testing of chips as described above when executing the computer program.

By adopting the technical scheme, the computer device capable of executing the high-efficiency test method for the chip is provided.

In a third aspect, the present application provides a computer readable storage medium, which adopts the following technical scheme:

a computer-readable storage medium storing a computer program; the computer program, when executed by the processor, implements the efficient test method of the chip.

By adopting the technical scheme, the carrier of the computer program of the high-efficiency test method of the chip is provided.

In summary, the present application includes at least the following beneficial technical effects:

1. downloading all the test programs to be executed in the batch at one time; after batch analysis, the ATE machine can detect the corresponding function of the current chip to be tested once according to a plurality of test programs, so that the repeated downloading of the test programs during testing the chip is reduced;

2. when the downloaded file is obtained in the computer end, if the ATE machine is used for simulating the JTAG downloader to directly execute the downloading action, the step of executing the downloading action by using the special downloader can be reduced, the time for downloading, replacing the board and replacing the machine test program is saved, and the working efficiency of the test chip is further improved.

Drawings

FIG. 1 is a flow chart frame of a method for efficient testing of chips in an embodiment of the present application;

FIG. 2 is a flow chart of steps of a method for efficient testing of chips in an embodiment of the present application;

FIG. 3 is a diagram of all waveforms captured by the logic analyzer in an embodiment of the present application;

FIG. 4 is a partial waveform diagram captured by the logic analyzer of FIG. 3;

fig. 5 is a partial waveform diagram captured by the logic analyzer of fig. 3.

Reference numerals illustrate:

1. a computer terminal; 2. dedicated software; 3. an ATE machine; 4. logic analyzer.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to fig. 1 to 5 and the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

In JTAG debug, boundary-Scan (Boundary-Scan) is a very important concept. The basic idea of the boundary scan technique is to add a shift register unit on the input/output pins close to the chip. Because these shift register cells are distributed across the Boundary of the chip, they are called Boundary-scan registers (Boundary-register cells).

These boundary scan registers can isolate the chip from the peripheral inputs and outputs when the chip is in debug. By means of these boundary scan register units, observation and control of chip input and output signals can be achieved. For the input pin of the chip, signals (data) can be loaded into the pin through a boundary scan register unit connected with the input pin; for the output pins of the chip, the output signals on that pin may also be "captured" (CAPTURE) by the boundary scan registers connected thereto. In normal operating conditions, these boundary scan registers are transparent to the chip, so normal operation is not affected in any way. In this way, the boundary scan register provides a convenient way to observe and control the chip that needs to be debugged.

For the use of a logic analyzer to grasp JTAG data, the TMS, TCK, TDI pin is determined to be an input pin, and the TDO pin is determined to be an output pin; TCK is clock pin, TMS is pin of control state register, TDI is data of input device pin, TDO is data of output device.

The embodiment of the application discloses a high-efficiency test method of a chip.

Referring to fig. 1, the high-efficiency test method of the chip includes the steps of:

s100: data is acquired.

Specifically, step S100 includes the steps of:

s110: the ATE board 3 is modeled as a JTAG downloader.

Specifically, step S110 includes the steps of:

s111: acquiring a downloading waveform;

specifically, referring to fig. 1 and 2, the download waveform in the present embodiment is acquired by the logic analyzer 4; the logic analyzer 4 firstly accesses the appointed computer terminal 1 and grabs the downloaded waveform in the computer terminal 1; the acquired subcarrier pattern is then transmitted to the dedicated software 2 and step S112 is performed.

S112: analyzing the carrier wave shape and converting the carrier wave shape into a graphic file which can be identified by the ATE machine table 3;

for example, the received carrier waveform is analyzed by the dedicated software 2 and converted into a graphic file that can be recognized by the ATE board 3 at present, where the graphic file that can be recognized by the ATE board 3 is a standard format that can be recognized by the ATE board 3, and binary codes are sequentially combined.

In this embodiment, the dedicated software 2 runs outside the ATE board 3, and the dedicated software 2 may use a JTAG graphics vector converter.

S113: the graphics file is added to the ATE machine 3 in a corresponding location.

After the above steps are performed, the ATE machine 3 can be simulated into a JTAG downloader to access the computer terminal 1, so that the direct connection between the ATE machine 3 and the computer terminal 1 is completed, and the step S120 can be started to be performed; by integrating the steps, the method and the device can reduce the time for downloading, replacing the board and replacing the machine test program, thereby further improving the working efficiency of the test chip.

S120: downloading a plurality of download files in the computer terminal 1;

specifically, a tester can import a corresponding number of download files into the computer terminal 1 according to the function to be tested of the current chip to be tested; then, the ATE machine 3, which has been simulated as a JTAG downloader, can start downloading the corresponding download file directly on the computer terminal 1.

In this embodiment, the downloaded file is a program capable of enabling the chip to be tested to run, i.e., a chip-side program; the download may be performed using a JTAG downloader or ATE bench 3.

S200: and (5) analyzing.

The ATE machine 3 sends the acquired downloaded file to the special software 2, and the downloaded file is analyzed into a plurality of test programs/test vectors based on the special software 2;

specifically, the downloaded file may be rewritten/parsed into the test program/test vector by the dedicated software 2, and in this embodiment, the dedicated software 2 may be simulation software (model sim tool) to simulate the design to be tested of the user, and convert the waveform record file generated after simulation into the required test vector.

In this embodiment, the test program can run on the ATE machine 3 for testing various ac or dc parameters of the chip under test and the test function of the chip;

the test vectors, which are part of the test program and can be run on the ATE machine 3, are in this embodiment graphic files recognizable by the ATE machine 3.

S300: a test is performed.

Specifically, step S300 includes the steps of:

s310: calculating the time of signal inversion;

s320: matching the signal overturning time of the ATE machine table 3 and the signal overturning time of the chip to be tested to be consistent;

specifically, step S320 includes the steps of:

s321: calculating the circulation times T;

specifically, the shortest pulse width of the clock management is obtained; deriving a subcarrier shape (refer to fig. 3, 4 and 5) as CSV format data based on a deriving function of the logic analyzer 4; acquiring time information based on the CSV format data; presetting the execution rate of the chip to be tested;

for example, referring to fig. 1 and 2, according to the waveform of the downloaded all the recorded data captured by the logic analyzer 4, it is known that the shortest pulse width of the clock TCK is above 150 ns; based on the deriving function of the logic analyzer 4 itself, waveforms can be derived as CSV data as shown in the following table.

TABLE 1 download File CSV partial data

In this embodiment, CSV data is divided into 5 columns, tims [ s ], TCK, TMS, TDI, TDO; the CSV data records all the edge Time information of TCK, TMS, TDI, TDO changes and records in Time [ S ], and the data can be imported into the special software 2 developed by us (the special software 2 is operated outside the ATE machine 3, the special software 2 can adopt JTAG graphic vector converter), and the Time of each signal inversion can be calculated according to the recorded Time information in Tims [ S ], and then the step S322 is started to be executed.

According to the recorded time information in Tims [ s ] in table 1, the time of each signal inversion is calculated, the period of the preset test vector for executing one row is 10ns, and then the cycle times T in the test vector are obtained according to the difference value of the time between each row divided by 10 ns.

S322: and circularly transmitting the test vectors to the chip to be tested for T times.

Specifically, the signal inversion time of the ATE machine 3 and the signal inversion time of the computer terminal 1 are matched to be consistent, so that the normal connection between the ATE machine 3 and the chip to be tested can be maintained, and the test program can be downloaded by the ATE machine 3.

S330: adding test items to a plurality of test programs one by one based on a preset sequence;

for example, several test items correspond to different test functions, and different test items are used to distinguish between different test programs, so as to directly call the different test programs.

S340: and acquiring the position to be added in the test program of the ATE machine table 3.

S350: and adding a corresponding test program to the position to be added.

For example, if a chip has five functions and cannot be measured simultaneously, the original test scheme is to design five download programs and corresponding machine test programs, and only one function can be measured at a time. After the method is adopted, the logic analyzer 4 is used for analyzing the five downloaded programs, and then the test program is written to the corresponding position to be added of the program of the ATE machine table 3, so that the simultaneous test of five functions is realized, and the test coverage rate of the chip is improved.

S360: and sending the analyzed test programs to the chip to be tested one by one according to a preset sequence.

For example, in the present embodiment, the predetermined sequence may be that a plurality of test programs are arranged in descending order according to the downloading time; the test program runs on the ATE machine table 3 and is used for testing various alternating current or direct current parameters of the tested chip and other various functions of the chip; the ATE machine 3 performs a test action on the chip to be tested based on the test program.

Based on the same design concept, the embodiment also discloses a test system for converting JTAG protocol into test vectors.

Referring to fig. 1, a test system for converting jtag protocol into test vectors includes a computer terminal 1, dedicated software 2 and an ATE machine 3; wherein, the ATE machine table 3 is connected with a logic analyzer 4; the logic analyzer 4 can be in communication connection with the computer terminal 1 and the special software 2.

The ATE machine 3 can assist the chip to be tested to perform multiple functional tests based on the test program and the test vector.

The present application also provides a computer readable storage medium storing instructions that when loaded and executed by a processor perform the above steps.

The computer-readable storage medium includes, for example: a U-disk, a removable hard disk, a Read-only memory (ROM), a random access memory (RandomAccessMemory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

Based on the same inventive concept, embodiments of the present application provide a computer apparatus comprising a memory and a processor, the memory having stored thereon a computer program that can be loaded by the processor and perform the above method.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional modules is illustrated, and in practical application, the above-described functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to perform all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.

In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

The foregoing embodiments are only used for describing the technical solution of the present application in detail, but the descriptions of the foregoing embodiments are only used for helping to understand the method and the core idea of the present application, and should not be construed as limiting the present application. Variations or alternatives that are readily contemplated by those skilled in the art within the scope of the present disclosure are intended to be encompassed within the scope of the present disclosure.

Claims

1. The high-efficiency test method of the chip is characterized by comprising the following steps of:

s100: acquiring data; step S100 comprises the following sub-steps:

s110: simulating the ATE machine (3) into a JTAG downloader; step S110 includes the sub-steps of:

s111: acquiring a download waveform, wherein the download waveform is acquired by a logic analyzer (4);

s112: analyzing the subcarrier shape and converting the subcarrier shape into a graphic file which can be identified by an ATE machine table (3);

s113: adding the graphic file to a corresponding position in an ATE machine table (3);

s120: acquiring a plurality of download files in a computer terminal (1); the downloaded file is a program capable of enabling the chip to be tested to run;

s200: analysis:

analyzing a plurality of downloaded files based on a preset algorithm, and obtaining a test program;

the ATE machine table (3) sends the acquired downloaded file to the special software (2), and the downloaded file is analyzed into a plurality of test programs/test vectors based on the special software (2);

the special software (2) is simulation software, the design to be tested of the user is simulated through the simulation software, and the waveform record file generated after simulation is converted into a required test program/test vector;

s300: performing a test: starting testing the chip to be tested based on a plurality of testing programs;

step S300 comprises the following sub-steps:

s310: calculating the time of signal inversion;

s320: matching the signal overturning time of the ATE machine table (3) and the chip to be tested to be consistent; step S320 includes the sub-steps of:

s321: calculating the circulation times T;

acquiring the shortest pulse width of a clock pin; exporting the subcarrier pattern into CSV format data based on an export function of the logic analyzer (4); acquiring time information based on the CSV format data; presetting the execution rate of the chip to be tested;

the CSV data records all TCK, TMS, TDI, TDO changed edge Time information, records the Time in Tims [ s ], and calculates the Time of each signal turning according to the recorded Time information in Tims [ s ];

converting the plurality of subcarrier shapes into test vectors one by one;

2. The method for testing chips according to claim 1, wherein after the step of matching the signal flip times of the ATE machine (3) and the chip to be tested to be identical, the method further comprises the steps of:

and the test items correspond to different test functions.

3. The method for testing chips of claim 2, further comprising the steps of, after said step of adding test items one by one to a plurality of said test programs based on a predetermined sequence:

s340: acquiring a position to be added in a program of an ATE machine (3);

s350: and adding a corresponding test program to the position to be added.

4. Computer device, characterized in that it comprises a processor, a memory and a computer program stored in said memory and executable on said processor, said processor implementing an efficient test method of a chip according to any one of claims 1-3 when executing said computer program.

5. A computer-readable storage medium, wherein the computer storage medium stores a computer program; the computer program, when executed by a processor, implements a method for efficient testing of chips according to any of claims 1-3.