CN101807604B - 一种点接触ldmos结构晶体管单元 - Google Patents

一种点接触ldmos结构晶体管单元 Download PDF

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CN101807604B
CN101807604B CN2010101382310A CN201010138231A CN101807604B CN 101807604 B CN101807604 B CN 101807604B CN 2010101382310 A CN2010101382310 A CN 2010101382310A CN 201010138231 A CN201010138231 A CN 201010138231A CN 101807604 B CN101807604 B CN 101807604B
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CN101807604A (zh
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傅义珠
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CETC 55 Research Institute
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Abstract

本发明公开了一种点接触LDMOS结构晶体管单元。其结构是漏接触区为圆形或正多边形,位于晶体管单元中心,外围依次环绕着漂移区、栅沟道区和源区。晶体管单元中栅宽与漏源PN结面积比比常规LDMOS结构提高一倍;晶体管单元分别按照一定周期沿X方向和Y方向分布构成器件芯片。本发明的优点:能够有效分散热源,减小热阻,提高器件工作带宽、增益和功率等性能指标。

Description

一种点接触LDMOS结构晶体管单元
技术领域
本发明涉及的是一种适用于微波功率晶体管生产的点接触LDMOS结构晶体管单元,属于半导体微电子设计制造技术领域。
背景技术
目前,现有横向双扩散金属氧化物晶体管(LDMOS)单元通常是矩形长条结构,此晶体管单元按照一定周期沿矩形长边向分布构成器件芯片。为了提高器件芯片的微波性能,通常需减小寄生电容、寄生电感等电参数。器件设计制造中主要采取措施包括:采用浓硼掺杂(P+)衬底;淡硼掺杂外延层(P-);浓硼掺杂(P+)背面源;亚微米尺寸的短沟道;全耗尽漂移区等;为了提高器件芯片的功率性能,需要增加栅宽、提高漏源击穿电压和减小源、漏和沟道串连电阻。栅宽和耐压的提高势必增加漏源电容面积,对器件增益和带宽不利。器件芯片微波功率性能优值可以用栅宽与漏源PN结面积比来表征。由于击穿电压限制,沟道至漏接触窗口之间的漂移区宽度无法缩小,因此在矩形长条晶体管单元中漂移区和漏接触区与衬底之间的漏源PN结电容难以进一步减小。因此大功率器件芯片的面积往往比较大,漏源PN结电容也比较大,限制器件宽带微波大功率应用。
发明内容
本发明提出的是一种点接触LDMOS结构晶体管单元,其目的旨在克服现有技术中所存在的不足,采用点接触晶体管单元,可大幅减小晶体管单元热阻和漏源PN结电容,提高微波功率增益和输出功率。有效减小晶体管单元漏源PN结电容的结构。
本发明的技术解决方案:其特征是晶体管单元漏电极接触区是圆形或正多边形N+掺杂漏区,N+掺杂漏区外围是环绕N-掺杂漂移区;环绕N-掺杂漂移区外围是P型掺杂沟道区,P型掺杂沟道区上方是N+掺杂多晶硅栅区;在P型掺杂沟道区与N+掺杂多晶硅栅区之间隔着二氧化硅绝缘层;在P型掺杂沟道区区外围环绕着N+掺杂源区;在N+掺杂源区外围是P+掺杂源区,P+掺杂源区掺杂深度超过外延层厚度,P+掺杂源区与P+衬底相连;P+掺杂源区与N+掺杂源区表面通过金属硅化物相连。
本发明的有益效果:本发明提出的点接触LDMOS结构晶体管单元栅宽与漏源PN结面积比现有LDMOS晶体管单元提高一倍;圆形或正多边形环状漂移区面积较小,易于耗尽,可以提高漂移区掺杂浓度;沟道掺杂无边缘尖角,有利于提高沟道击穿电压;同时点接触晶体管单元分布所构成的器件芯片,能够有效分散热源,减小热阻,满足器件宽带、高增益和大功率应用要求。
附图说明
附图1是点接触LDMOS结构晶体管单元局部结构示意图;
附图2是点接触LDMOS结构晶体管单元分布芯片局部结构示意图;
附图3是本发明点接触LDMOS结构晶体管单元分布芯片金属电极局部结构示意图;
附图4是LDMOS剖面结构示意图。
图中的1是P+掺杂源区,掺杂深度超过外延层厚度,与P+衬底相连;2是N+掺杂源区;3是P型掺杂沟道区;4是N-掺杂漂移区;5是N+掺杂漏 区;6是位于3区之上的多晶硅栅区;7是源金属电极S;8是栅金属电极G;9是漏金属电极D;10是栅氧化层;11是芯片表面绝缘层;12是P-外延层;13是P+衬底;14是源接触窗口;15是栅接触窗口;16是漏接触窗口。
具体实施方式
对照附图1,其结构是点接触LDMOS结构晶体管单元其结构是N+掺杂漏区5为圆形或正多边形,构成漏接触区;N+掺杂漏区5外围是环绕N-掺杂漂移区4;环绕N-掺杂漂移区4外围是环绕P型掺杂沟道区3,P型掺杂沟道区3上方是N+掺杂多晶硅栅6;在P型掺杂沟道区3与N+掺杂多晶硅栅6之间隔着二氧化硅绝缘层;在P型掺杂沟道区3外围环绕着N+掺杂源区2;在N+掺杂源区2外围是P+掺杂源区1,P+掺杂源区1掺杂深度超过外延层厚度,P+掺杂源区1与P+衬底相连;P+掺杂源区1与N+掺杂源区2表面通过金属硅化物相连。以上各区共同构成点接触LDMOS结构晶体管单元。
对照附图2,是点接触LDMOS结构晶体管单元按照一定周期T1(距离大于N+掺杂源区2外边界直径)沿Y方向复制某个数量N1,这N1个晶体管单元构成一组,再按照一定周期T2(距离大于N+掺杂源区2外边界直径)沿X方向复制某组数N2,由这N1×N2个单元构成的器件芯片局部图。该芯片表面覆盖着一层绝缘层,在对应P+掺杂源区1、N+掺杂多晶硅栅区6和N+掺杂漏区5分别开有金属接触窗口。
对照附图3,其结构是源金属电极S是通过源接触窗口14与P+掺杂源区1相连接而成;栅金属电极G是通过栅接触窗口15与N+掺杂多晶硅栅6相连接而成;漏金属电极D是通过漏接触窗口16与N+掺杂漏区5相连而成。
以上所述仅是本发明的优选实施方式,应当指出对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰。

Claims (4)

1.一种点接触LDMOS结构晶体管单元,其特征是晶体管单元漏电极接触区是圆形或正多边形N+掺杂漏区(5),N+掺杂漏区(5)外围是环绕N-掺杂漂移区(4);环绕N-掺杂漂移区(4)外围是P型掺杂沟道区(3),P型掺杂沟道区(3)上方是N+掺杂多晶硅栅区(6);在P型掺杂沟道区(3)与N+掺杂多晶硅栅区(6)之间隔着二氧化硅绝缘层;在P型掺杂沟道区(3)区外围环绕着N+掺杂源区(2);在N+掺杂源区(2)外围是P+掺杂源区(1),P+掺杂源区(1)掺杂深度超过外延层厚度,P+掺杂源区(1)与P+衬底相连;P+掺杂源区(1)与N+掺杂源区(2)表面通过金属硅化物相连。
2.根据权利要求1所述的一种点接触LDMOS结构晶体管单元,其特征是在对应P+掺杂源区(1)、N+掺杂多晶硅栅区(6)和N+掺杂漏区(5)分别开有金属接触窗口。
3.根据权利要求1所述的一种点接触LDMOS结构晶体管单元,按照周期T1即距离大于N+掺杂源区(2)外边界直径,沿Y方向复制某个数量N1,这N1个晶体管单元构成一组,再按照周期T2即距离大于N+掺杂源区(2)外边界直径,沿X方向复制某个数量N2,这N2个晶体管单元构成一组,由N1×N2个单元构成器件芯片。
4.根据权利要求4所述的一种点接触LDMOS结构晶体管单元,其特征是器件芯片表面覆盖着一层绝缘层,在对应P+掺杂源区(1)、N+掺杂多晶硅栅区(6)和N+掺杂漏区(5)分别开有金属接触窗口。
CN2010101382310A 2010-04-02 2010-04-02 一种点接触ldmos结构晶体管单元 Expired - Fee Related CN101807604B (zh)

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