CN101807581A - Contactless split-gate flash memory of shared word line and manufacture method thereof - Google Patents
Contactless split-gate flash memory of shared word line and manufacture method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000007667 floating Methods 0.000 claims description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 229920005591 polysilicon Polymers 0.000 claims description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 238000001312 dry etching Methods 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- 230000005641 tunneling Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 230000000295 complement effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005755 formation reaction Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
The invention provides a contactless split-gate flash memory of a shared word line and a manufacture method thereof. An obtained flash memory device enables two storage bit units to share one word line, and the reading, the programming and the erasing of the storage bit units are realized by applying different working voltages on the word line, a first bit line and a second bit line; the structure of a shared work line enables the split-gate flash memory to effectively reduce the area of a chip under the condition of keeping the electrical isolating property of the chip unchanged, and meanwhile, the over erasing problem can also be avoided. Meanwhile, the flash memory device has the characteristics that the dimensions are small, and the process is compatible with the CMOS (Complementary Metal-Oxide-Semiconductor Transistor) traditional process, which is beneficial to further reducing the dimensions of the device.
Description
Technical field
The present invention relates to semiconductor design and make the field, and be particularly related to a kind of contactless split-gate flash memory and manufacture method thereof of shared word line.
Background technology
Flash memory is convenient with it, the storage density height, and advantages such as good reliability become the focus of studying in the non-volatility memorizer.Since first flash memory products comes out from the 1980s, development and the demand of each electronic product along with technology to storing, flash memory is widely used in mobile phone, notebook, palmtop PC and USB flash disk etc. move and communication apparatus in, flash memory is a kind of non-volatility memory, its operation principles is to control the switch of gate pole passage to reach the purpose of storage data by the critical voltage that changes transistor or memory cell, make the data that are stored in the memory can be, and flash memory be a kind of special construction of electric erasable and programmable read-only memory because of power interruptions does not disappear.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Yet existing flash memory is in the high storage density of marching toward more, owing to be subjected to the restriction of program voltage, improve storage density by reduction of device size and will face very big challenge, thereby the flash memory of development high storage density is the important motive force of flash memory technology development.Traditional flash memory owing to be subjected to the restriction of structure, realizes that the program voltage of device further reduces to be faced with very big challenge in the high storage density of marching toward more.
Generally speaking, flash memory is the combination of grid dividing structure or stacking gate structure or two kinds of structures.Gate-division type flash memory is because its special structure, compare the stacking gate flash memory and all embody its particular performances advantage in programming with when wiping, therefore divide grid formula structure owing to have high programming efficiency, the structure of word line can be avoided advantages such as " cross and wipe ", uses particularly extensive.Thereby but since gate-division type flash memory with respect to the stacking gate flash memory many a word line make area of chip also can increase, the size that therefore how further reduces chip in the raising chip performance is to need the problem of solution badly.
Simultaneously, along with the memory device size is constantly dwindled continuous rising with storage density, the size that is formed at the contact hole in the inner layer dielectric layer also can become littler, yet this inner layer dielectric layer must keep rational thickness, make this contact hole need keep sizable depth-to-width ratio (depth/width), thereby make the contact point on the Semiconductor substrate occupy the sizable ratio of whole memory unit area, become the key factor that restriction memory device size and storage density further develop.
Summary of the invention
The present invention proposes a kind of contactless split-gate flash memory and manufacture method thereof of shared word line, and its flush memory device that obtains can dwindle area of chip effectively under the constant situation of the electric isolation performance that keeps chip, also can avoid the problem of wiping simultaneously.
In order to achieve the above object, the present invention proposes a kind of contactless split-gate flash memory of shared word line, comprising:
Semiconductor substrate has the source region and the drain region that are provided with at interval on it;
Channel region is between described source region and drain region;
First bit line and second bit line are connected to described source region and drain region;
First floating boom is arranged at described channel region and source region top;
Second floating boom is arranged at described channel region and drain region top, and described first floating boom and second floating boom constitute first storage bit unit and second storage bit unit respectively;
Word line, comprise first and second portion, described first is above the described channel region and between described first floating boom and second floating boom, described second portion is connected in described first top, and be positioned at above described first floating boom and second floating boom, described second portion top extends to described first bit line and second bit line top, and is connected with the second bit line top with described first bit line by insulating barrier.
Further, respectively described word line, described first bit line and described second bit line are applied first storage bit unit and read voltage, realize that first storage bit unit reads.
Further, first storage bit unit that described word line, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 0V and 1.5V, realizes that first storage bit unit reads.
Further, respectively described word line, described first bit line and described second bit line are applied second storage bit unit and read voltage, realize that second storage bit unit reads.
Further, second storage bit unit that described word line, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 1.5V and 0V, realizes that second storage bit unit reads.
Further, respectively described word line, described first bit line and described second bit line are applied the first storage bit unit program voltage, realize the programming of first storage bit unit.
Further, the first storage bit unit program voltage that described word line, described first bit line and described second bit line are applied is respectively 4V, 7.5V and 0V, realizes the programming of first storage bit unit.
Further, respectively described word line, described first bit line and described second bit line are applied the second storage bit unit program voltage, realize the programming of second storage bit unit.
Further, the second storage bit unit program voltage that described word line, described first bit line and described second bit line are applied is respectively 4V, 0V and 7.5V, realizes the programming of second storage bit unit.
Further, respectively described word line, described first bit line and described second bit line are applied the storage bit unit erasing voltage, realize that first storage bit unit and second storage bit unit wipe.
Further, the storage bit unit erasing voltage that described word line, described first bit line and described second bit line are applied is respectively 11V, 0V and 0V, realizes that first storage bit unit and second storage bit unit wipe.
In order to achieve the above object, the present invention also proposes a kind of contactless split-gate flash memory manufacture method of shared word line, comprises the following steps:
Semi-conductive substrate is provided, and deposited oxide layer, floating gate polysilicon layer and silicon nitride layer successively;
Described silicon nitride layer is carried out dry etching until exposing described floating gate polysilicon layer, form a plurality of grooves;
Form the first side wall oxide skin(coating) in described recess sidewall deposition;
Described floating gate polysilicon layer in the described groove is carried out dry etching, and the further described oxide layer of etching is until exposing described Semiconductor substrate;
The Semiconductor substrate of bottom portion of groove is carried out ion inject, form bit line;
Form the second side wall oxide skin(coating) in described recess sidewall deposition;
At said structure surface deposition bit line polysilicon, to described bit line polysilicon grind and further dry etching reduce to below the described groove end face until the height of described bit line polysilicon;
At said structure surface deposition insulating barrier, and it is ground until filling up described groove;
Wet etching is removed described silicon nitride layer, and at said structure surface deposition side wall nitride silicon layer;
Described side wall nitride silicon layer is carried out dry etching form the silicon nitride side wall, and further dry etching is removed the part floating gate polysilicon layer and wet etching is removed the partial oxidation layer until exposing described Semiconductor substrate;
Wet etching is removed described silicon nitride side wall;
Deposition tunneling oxide layer and word line polysilicon on said structure.
Further, described thickness of oxide layer is more than or equal to 100 dusts.
Further, the thickness of described floating gate polysilicon layer is 500 dusts～1000 dusts.
Further, the thickness of described silicon nitride layer is 4000 dusts～6000 dusts.
Further, the thickness of the described first side wall oxide skin(coating) is 200 dusts～500 dusts.
Further, the thickness of described bit line polysilicon is 1800 dusts～2500 dusts.
Further, the thickness after described insulating barrier grinds is 300 dusts～500 dusts.
Further, the thickness of described side wall nitride silicon layer is 1800 dusts～2000 dusts.
Further, the thickness of described word line polysilicon is more than or equal to 2000 dusts.
The contactless split-gate flash memory and the manufacture method thereof of the shared word line that the present invention proposes, two storage bit unit are shared word line of use, realize reading, programming and wiping by word line, first bit line and second bit line being applied different operating voltages to storage bit unit, the structure of share bit lines make gate-division type flash memory its can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.Adopt contactless design simultaneously, it is little to make that flush memory device has size, and the characteristics of technology and CMOS traditional handicraft compatibility help device size and further dwindle.
Description of drawings
Figure 1 shows that the contactless split-gate flash memory structural representation of the shared word line of preferred embodiment of the present invention.
Fig. 2～Figure 12 shows that contactless split-gate flash memory manufacture method schematic diagram of the shared word line of preferred embodiment of the present invention.
Embodiment
In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
The present invention proposes a kind of contactless split-gate flash memory and manufacture method thereof of shared word line, and its flush memory device that obtains can dwindle area of chip effectively under the constant situation of the electric isolation performance that keeps chip, also can avoid the problem of wiping simultaneously.
Please refer to Fig. 1, Figure 1 shows that the contactless split-gate flash memory structural representation of the shared word line of preferred embodiment of the present invention.The present invention proposes a kind of contactless split-gate flash memory of shared word line, comprising: Semiconductor substrate 100 has the source region 110 and the drain region 120 that are provided with at interval on it; Channel region 130 is between described source region 110 and drain region 120; First bit line 210 and second bit line 220 are connected to described source region 110 and drain region 120; First floating boom 310 is arranged at described channel region 130 and 110 tops, source region; Second floating boom 320 is arranged at described channel region 130 and 120 tops, drain region, and described first floating boom 310 and second floating boom 320 constitute first storage bit unit and second storage bit unit respectively; Word line 500, comprise first 510 and second portion 520, described first 510 is above the described channel region 130 and between described first floating boom 310 and second floating boom 320, described second portion 520 is connected in described first 510 tops, and be positioned at described first floating boom 310 and second floating boom, 320 tops, described second portion 520 tops extend to described first bit line 210 and second bit line, 220 tops, and are connected with second bit line, 220 tops with described first bit line 210 by insulating barrier 610,620.
The preferred embodiment according to the present invention, first storage bit unit and second storage bit unit that described first floating boom 310 and second floating boom 320 constitute respectively are multi-crystal silicon floating bar.Polysilicon belongs to conductor, and traditional memory all is that the employing polysilicon is a storage medium, and it adopts and the general identical polysilicon of grid, therefore can be good at and the traditional handicraft compatibility; First bit line 210 of the present invention and second bit line 220, be directly connected in described source region 110 and drain region 120 respectively, and the mode that does not need to form contact point by the making contact hole on Semiconductor substrate 100 connects, design with non-contact-point, make flush memory device have littler size, help device size and further dwindle.
In the preferred embodiment of the present invention, there is electric current between source region 110 and drain region 120, to flow in the raceway groove 130, first storage bit unit that described first floating boom 310 and second floating boom 320 constitute respectively and second storage bit unit have or not charge storage can influence size of current in the raceway groove 130, when first storage bit unit that constitutes respectively when described first floating boom 310 and second floating boom 320 and second storage bit unit have electric charge, electric current is very little in the raceway groove 130, when otherwise first storage bit unit that constitutes respectively when described first floating boom 310 and second floating boom 320 and second storage bit unit do not have electric charge, electric current is very big in the raceway groove 130, setting raceway groove 130 interior little current status is " 0 ", setting raceway groove 130 interior current states is " 1 ", first storage bit unit that described like this first floating boom 310 and second floating boom 320 constitute respectively and second storage bit unit have or not the state of charge storage to can be used as differentiation storage " 0 " or " 1 " information state, realize the function that first storage bit unit and the second storage bit unit information stores read.
The preferred embodiment according to the present invention applies first storage bit unit to described word line 500, described first bit line 210 and described second bit line 220 respectively and reads voltage, realizes that first storage bit unit reads.
Further, first storage bit unit that described word line 500, described first bit line 210 and described second bit line 220 are applied reads voltage and is respectively 2.5V, 0V and 1.5V, realizes that first storage bit unit reads.
The preferred embodiment according to the present invention applies second storage bit unit to described word line 500, described first bit line 210 and described second bit line 220 respectively and reads voltage, realizes that second storage bit unit reads.
Further, second storage bit unit that described word line 500, described first bit line 210 and described second bit line 220 are applied reads voltage and is respectively 2.5V, 1.5V and 0V, realizes that second storage bit unit reads.
Source-drain electrodes voltage between source region 110 and drain region 120 is enough high, is enough to cause some high energy electron to cross insulation dielectric layer, and enters the storage space unit on the insulation dielectric layer, and this process is called hot electron and injects.And the composition of described insulation dielectric layer is the oxide of silicon or the nitride of silicon, as materials such as silicon dioxide or silicon nitrides, it is between first storage bit unit and second storage bit unit that Semiconductor substrate 100 and described first floating boom 310 and second floating boom 320 constitute respectively.
The preferred embodiment according to the present invention applies the first storage bit unit program voltage to described word line 500, described first bit line 210 and described second bit line 220 respectively, realizes the programming of first storage bit unit.In the preferred embodiment of the present invention, apply read operating voltage after, there is electronics 120 to flow to source region 110 in the raceway groove 130 from the drain region, portions of electronics is injected in first storage bit unit of described first floating boom, 310 formations by the hot electron injection mode, realizes the programming operation of first storage bit unit.
Further, the first storage bit unit program voltage that described word line 500, described first bit line 210 and described second bit line 220 are applied is respectively 4V, 7.5V and 0V, realizes the programming of first storage bit unit.
The preferred embodiment according to the present invention applies the second storage bit unit program voltage to described word line 500, described first bit line 210 and described second bit line 220 respectively, realizes the programming of second storage bit unit.In the preferred embodiment of the present invention, apply read operating voltage after, there is electronics 110 to flow to drain region 120 in the raceway groove 130 from the source region, portions of electronics is injected in second storage bit unit of second floating boom, 320 formations by the hot electron injection mode, realizes the programming operation of second storage bit unit.
Further, the second storage bit unit program voltage that described word line 500, described first bit line 210 and described second bit line 220 are applied is respectively 4V, 0V and 7.5V, realizes the programming of second storage bit unit.
The preferred embodiment according to the present invention applies the storage bit unit erasing voltage to described word line 500, described first bit line 210 and described second bit line 220 respectively, realizes that first storage bit unit and second storage bit unit wipe.Apply under the operating voltage condition at this, be stored in first storage bit unit that described first floating boom 310 and second floating boom 320 constitute respectively and electronics FN (Fowler-Nordheim) under high electric field of second storage bit unit and be tunneling to word line 500 ends, flow away by word line 500 ends, realize the erase operation of first storage bit unit and second storage bit unit.
Further, the storage bit unit erasing voltage that described word line 500, described first bit line 210 and described second bit line 220 are applied is respectively 11V, 0V and 0V, realizes that first storage bit unit and second storage bit unit wipe.
Please refer to Fig. 2～Figure 12 again, Fig. 2～Figure 12 shows that contactless split-gate flash memory manufacture method schematic diagram of the shared word line of preferred embodiment of the present invention.The present invention also proposes a kind of contactless split-gate flash memory manufacture method of shared word line, comprises the following steps:
With reference to figure 2, semi-conductive substrate 10 is provided, and deposited oxide layer 11, floating gate polysilicon layer 12 and silicon nitride layer 13 successively; The thickness of described oxide layer 11 is more than or equal to 100 dusts, and the thickness of described floating gate polysilicon layer 12 is 500 dusts～1000 dusts, and the thickness of described silicon nitride layer 13 is 4000 dusts～6000 dusts.
Please refer to Fig. 3 more described silicon nitride layer 13 is carried out dry etching until exposing described floating gate polysilicon layer 12, form a plurality of grooves 20;
Then, form the first side wall oxide skin(coating) 21 in described groove 20 side wall deposition with reference to figure 4; The thickness of the described first side wall oxide skin(coating) 21 is 200 dusts～500 dusts.
With reference to figure 5, the described floating gate polysilicon layer 12 in the described groove 20 is carried out dry etching, and the further described oxide layer 11 of etching is until exposing described Semiconductor substrate 10;
The Semiconductor substrate 10 of groove 20 bottoms is carried out ion inject, form bit line;
Please refer to Fig. 6 and Fig. 7 again, form the second side wall oxide skin(coating) 22 in described groove 20 side wall deposition;
And at said structure surface deposition bit line polysilicon 30, the thickness of described bit line polysilicon 30 is 1800 dusts～2500 dusts, to described bit line polysilicon 30 grind and further dry etching reduce to below described groove 20 end faces until the height of described bit line polysilicon 30;
Please refer to Fig. 8, at said structure surface deposition insulating barrier 40, and it is ground until filling up described groove 20, the thickness after described insulating barrier 40 grinds is 300 dusts～500 dusts;
With reference to figure 9 and Figure 10, wet etching is removed described silicon nitride layer 13, and at said structure surface deposition side wall nitride silicon layer (not shown); The thickness of described side wall nitride silicon layer is 1800 dusts～2000 dusts.
Described side wall nitride silicon layer is carried out dry etching form silicon nitride side wall 50, and further dry etching is removed part floating gate polysilicon layer 12 and wet etching is removed partial oxidation layer 11 until exposing described Semiconductor substrate 10;
Please refer to Figure 11, wet etching is removed described silicon nitride side wall 50;
Please refer to Figure 12 at last, deposition tunneling oxide layer 60 and word line polysilicon 70 on said structure, the thickness of described word line polysilicon 70 is more than or equal to 2000 dusts.
The contactless split-gate flash memory and the manufacture method thereof of the shared word line that the present invention proposes, two storage bit unit are shared word line of use, realize reading, programming and wiping by word line, first bit line and second bit line being applied different operating voltages to storage bit unit, the structure of share bit lines make gate-division type flash memory its can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.Adopt contactless design simultaneously, it is little to make that flush memory device has size, and the characteristics of technology and CMOS traditional handicraft compatibility help device size and further dwindle.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (20)
1. the contactless split-gate flash memory of a shared word line is characterized in that, comprising:
Semiconductor substrate has the source region and the drain region that are provided with at interval on it;
Channel region is between described source region and drain region;
First bit line and second bit line are connected to described source region and drain region;
First floating boom is arranged at described channel region and source region top;
Second floating boom is arranged at described channel region and drain region top, and described first floating boom and second floating boom constitute first storage bit unit and second storage bit unit respectively;
Word line, comprise first and second portion, described first is above the described channel region and between described first floating boom and second floating boom, described second portion is connected in described first top, and be positioned at above described first floating boom and second floating boom, described second portion top extends to described first bit line and second bit line top, and is connected with the second bit line top with described first bit line by insulating barrier.
2. the contactless split-gate flash memory of shared word line according to claim 1 is characterized in that, respectively described word line, described first bit line and described second bit line is applied first storage bit unit and reads voltage, realizes that first storage bit unit reads.
3. the contactless split-gate flash memory of shared word line according to claim 2, it is characterized in that, first storage bit unit that described word line, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 0V and 1.5V, realizes that first storage bit unit reads.
4. the contactless split-gate flash memory of shared word line according to claim 1 is characterized in that, respectively described word line, described first bit line and described second bit line is applied second storage bit unit and reads voltage, realizes that second storage bit unit reads.
5. the contactless split-gate flash memory of shared word line according to claim 4, it is characterized in that, second storage bit unit that described word line, described first bit line and described second bit line are applied reads voltage and is respectively 2.5V, 1.5V and 0V, realizes that second storage bit unit reads.
6. the contactless split-gate flash memory of shared word line according to claim 1 is characterized in that, respectively described word line, described first bit line and described second bit line is applied the first storage bit unit program voltage, realizes the programming of first storage bit unit.
7. the contactless split-gate flash memory of shared word line according to claim 6, it is characterized in that, the first storage bit unit program voltage that described word line, described first bit line and described second bit line are applied is respectively 4V, 7.5V and 0V, realizes the programming of first storage bit unit.
8. the contactless split-gate flash memory of shared word line according to claim 1 is characterized in that, respectively described word line, described first bit line and described second bit line is applied the second storage bit unit program voltage, realizes the programming of second storage bit unit.
9. the contactless split-gate flash memory of shared word line according to claim 8, it is characterized in that, the second storage bit unit program voltage that described word line, described first bit line and described second bit line are applied is respectively 4V, 0V and 7.5V, realizes the programming of second storage bit unit.
10. the contactless split-gate flash memory of shared word line according to claim 1, it is characterized in that, respectively described word line, described first bit line and described second bit line are applied the storage bit unit erasing voltage, realize that first storage bit unit and second storage bit unit wipe.
11. the contactless split-gate flash memory of shared word line according to claim 11, it is characterized in that, the storage bit unit erasing voltage that described word line, described first bit line and described second bit line are applied is respectively 11V, 0V and 0V, realizes that first storage bit unit and second storage bit unit wipe.
12. the contactless split-gate flash memory manufacture method of a shared word line is characterized in that, comprises the following steps:
Semi-conductive substrate is provided, and deposited oxide layer, floating gate polysilicon layer and silicon nitride layer successively;
Described silicon nitride layer is carried out dry etching until exposing described floating gate polysilicon layer, form a plurality of grooves;
Form the first side wall oxide skin(coating) in described recess sidewall deposition;
Described floating gate polysilicon layer in the described groove is carried out dry etching, and the further described oxide layer of etching is until exposing described Semiconductor substrate;
The Semiconductor substrate of bottom portion of groove is carried out ion inject, form bit line;
Form the second side wall oxide skin(coating) in described recess sidewall deposition;
At said structure surface deposition bit line polysilicon, to described bit line polysilicon grind and further dry etching reduce to below the described groove end face until the height of described bit line polysilicon;
At said structure surface deposition insulating barrier, and it is ground until filling up described groove;
Wet etching is removed described silicon nitride layer, and at said structure surface deposition side wall nitride silicon layer;
Described side wall nitride silicon layer is carried out dry etching form the silicon nitride side wall, and further dry etching is removed the part floating gate polysilicon layer and wet etching is removed the partial oxidation layer until exposing described Semiconductor substrate;
Wet etching is removed described silicon nitride side wall;
Deposition tunneling oxide layer and word line polysilicon on said structure.
13. the contactless split-gate flash memory manufacture method of shared word line according to claim 12 is characterized in that, described thickness of oxide layer is more than or equal to 100 dusts.
14. the contactless split-gate flash memory manufacture method of shared word line according to claim 12 is characterized in that, the thickness of described floating gate polysilicon layer is 500 dusts～1000 dusts.
15. the contactless split-gate flash memory manufacture method of shared word line according to claim 12 is characterized in that, the thickness of described silicon nitride layer is 4000 dusts～6000 dusts.
16. the contactless split-gate flash memory manufacture method of shared word line according to claim 12 is characterized in that, the thickness of the described first side wall oxide skin(coating) is 200 dusts～500 dusts.
17. the contactless split-gate flash memory manufacture method of shared word line according to claim 12 is characterized in that, the thickness of described bit line polysilicon is 1800 dusts～2500 dusts.
18. the contactless split-gate flash memory manufacture method of shared word line according to claim 12 is characterized in that, the thickness after described insulating barrier grinds is 300 dusts～500 dusts.
19. the contactless split-gate flash memory manufacture method of shared word line according to claim 12 is characterized in that, the thickness of described side wall nitride silicon layer is 1800 dusts～2000 dusts.
20. the contactless split-gate flash memory manufacture method of shared word line according to claim 12 is characterized in that, the thickness of described word line polysilicon is more than or equal to 2000 dusts.
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| CN103531456B (en) * | 2012-07-05 | 2016-08-10 | 上海华虹宏力半导体制造有限公司 | The method forming stable residual oxide on floating boom |
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