CN101692452B - Storage unit sharing split gate type flash memory - Google Patents
Storage unit sharing split gate type flash memory Download PDFInfo
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- CN101692452B CN101692452B CN200910197120.4A CN200910197120A CN101692452B CN 101692452 B CN101692452 B CN 101692452B CN 200910197120 A CN200910197120 A CN 200910197120A CN 101692452 B CN101692452 B CN 101692452B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 10
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
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- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 238000002347 injection Methods 0.000 description 2
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- 239000005543 nano-size silicon particle Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910007991 Si-N Inorganic materials 0.000 description 1
- 229910006294 Si—N Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000010276 construction Methods 0.000 description 1
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- 230000007704 transition Effects 0.000 description 1
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Abstract
The invention provides a storage unit sharing split gate type flash memory, which comprises a semiconductor substrate provided with a source electrode area and a drain electrode area which are arranged at intervals, a channel area arranged between the source electrode area and the drain electrode area, a storage unit arranged above the channel area, a word line arranged above the storage unit, and a first selection gate and a second selection gate which are arranged on two sides of the word line and the storage unit respectively, wherein the storage unit comprises a first storage part and a second storage part, the first storage part is close to the first selection gate, the second storage part is close to the second selection gate, and the storage unit is the nanometer crystal storage unit. In the split gate type flash memory, the storage area of single byte is reduced, and simultaneously the over-erasing problem is avoided.
Description
Technical field
The present invention relates to semiconductor design and make the field, and be particularly related to a kind of gate-division type flash memory of shared memory cell.
Background technology
Flash memory is convenient with it, and storage density is high, and advantages such as good reliability become the focus of studying in the non-volatility memorizer.Since first flash memory products comes out from the 1980s; Development and the demand of each electronic product along with technology to storage; Flash memory is widely used in mobile phone, notebook, palmtop PC and USB flash disk etc. move with communication apparatus in; Flash memory is a kind of nonvolatile memory; Its operation principles is a switch of controlling the gate pole passage through the critical voltage that changes transistor or memory cell can be because of power interruptions disappear to reach the purpose of storage data, to make the data that are stored in the memory, and flash memory is a kind of special construction of electric erasable and programmable read-only memory.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Yet existing flash memory is in the high storage density of marching toward more; Owing to receive the restriction of program voltage; Improve storage density through reduction of device size and will face very big challenge, thereby the flash memory of development high storage density is the important motive force of flash memory technology development.Traditional flash memory owing to receive the restriction of structure, realizes that the program voltage of device further reduces to be faced with very big challenge in the high storage density of marching toward more.
Generally speaking, flash memory is the combination of grid dividing structure or stacking gate structure or two kinds of structures.Gate-division type flash memory is because its particular structural; Compare the stacking gate flash memory and all embody its particular performances advantage in programming with when wiping; Therefore divide grid formula structure owing to have high programming efficiency, the structure of word line can be avoided advantages such as " cross and wipe ", uses particularly extensive.Thereby but since gate-division type flash memory with respect to the stacking gate flash memory many a word line make area of chip also can increase, the size that therefore how in the raising chip performance, further reduces chip is to need the problem of solution badly.
Summary of the invention
The present invention proposes a kind of gate-division type flash memory of shared memory cell, when realizing that byte storage area dwindles, also can avoid the problem of wiping.
In order to achieve the above object, the present invention proposes a kind of gate-division type flash memory of shared memory cell, comprising:
Semiconductor substrate has the source region and the drain region that are provided with at interval on it;
Channel region is between said source region and drain region;
Memory cell is positioned at said channel region top;
Word line is positioned at said memory cell top;
First selects grid and second to select grid, lays respectively at said word line and memory cell both sides,
Wherein, said memory cell comprises first storage area and second storage area, and said first storage area contiguous first is selected grid, and said second storage area contiguous second is selected grid, and said memory cell is nanocrystalline memory cell.
Further, select grid, said second to select grid, said source region and said drain region to apply first storage area to said word line, said first respectively and read voltage, realize that first storage area reads.
Further, first storage area of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first reads voltage and is respectively 2.5V, 2V, 4V, 0V and 1V, realizes that first storage area reads.
Further, select grid, said second to select grid, said source region and said drain region to apply second storage area to said word line, said first respectively and read voltage, realize that second storage area reads.
Further, second storage area of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first reads voltage and is respectively 2.5V, 4V, 2V, 1V and 0V, realizes that second storage area reads.
Further, select grid, said second to select grid, said source region and said drain region to apply the first storage area program voltage to said word line, said first respectively, realize the programming of first storage area.
Further, the first storage area program voltage of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first is respectively 8V, 1.4V, 5V, 0V and 4V, realizes the programming of first storage area.
Further, select grid, said second to select grid, said source region and said drain region to apply the second storage area program voltage to said word line, said first respectively, realize the programming of second storage area.
Further, the second storage area program voltage of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first is respectively 8V, 5V, 1.4V, 4V and 0V, realizes the programming of second storage area.
Further, select grid, said second to select grid, said source region and said drain region to apply cell erase voltage to said word line, said first respectively, realize that first storage area and second storage area wipe.
Further, the cell erase voltage of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first is respectively-5V, F, F, F and F, realizes that first storage area and second storage area wipe.
The gate-division type flash memory of the shared memory cell that the present invention proposes; Because its shared two structures of grid of selecting can realize nanocrystalline part is stored; Thereby realized the function of single nanocrystalline device multibyte storage, realized keeping gate-division type flash memory not have the advantage of wiping when byte storage area dwindles.
Description of drawings
Shown in Figure 1 is the gate-division type flash memory structural representation of the shared memory cell of preferred embodiment of the present invention.
First storage bit unit of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 2 reads sketch map.
Second storage bit unit of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 3 reads sketch map.
First storage bit unit programming sketch map of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 4.
Second storage bit unit programming sketch map of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 5.
First storage bit unit and second storage bit unit of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 6 are wiped sketch map.
Embodiment
In order more to understand technology contents of the present invention, special act specific embodiment also cooperates appended graphic explanation following.
The present invention proposes a kind of gate-division type flash memory of shared memory cell, when realizing that byte storage area dwindles, also can avoid the problem of wiping.
Please refer to Fig. 1, shown in Figure 1 is the gate-division type flash memory structural representation of the shared memory cell of preferred embodiment of the present invention.The present invention proposes a kind of gate-division type flash memory of shared memory cell, comprising: Semiconductor substrate 100 has the source region 110 and drain region 120 that are provided with at interval on it; Channel region 130 is between said source region 110 and drain region 120; Memory cell 200 is positioned at said channel region 130 tops; Word line 300 is positioned at said memory cell 200 tops; First selects grid 410 and second to select grid 420; Lay respectively at said word line 300 and memory cell 200 both sides; Wherein, Said memory cell 200 comprises first storage area 210 and second storage area 220, and said first storage area 210 contiguous first is selected grid 410, and said second storage area 220 contiguous second is selected grid 420.
Traditional memory all is that the employing polysilicon is a storage medium, and it adopts and the general identical polysilicon of grid, therefore can be good at and the traditional handicraft compatibility; But because its property led for guaranteeing the data confining force of memory device, must guarantee no any defect oxide; Therefore the further attenuate (generally being greater than 70A) of the thickness of tunneling oxide; So just be unfavorable for the reduction of operating voltage, thereby cause dwindling of device size to be restricted, thereby the memory of localization just occurred: silicon nitride and nanocrystalline; Owing to adopt the storage of localization separated charge; The defect oxide of any part can not cause the drift of tangible device performance, therefore can be at the thickness of certain limit class attenuate tunneling oxide, thus help dwindling of device size.Silicon nitride is compared with nano-silicon; Because at high temperature the auxiliary transition (owing to the reason of Si-N key) of trap can take place in trapped electron in the silicon nitride; The memory data confining force reliability that with the silicon nitride is storage medium receives certain limitation; Concerning nano-silicon, there is the drawback of technology more complicated in it equally.
The preferred embodiment according to the present invention; Said memory cell 200 is nanocrystalline memory cell (Nanocrystals; NCS); Nanocrystalline silicon crystal grain with little amorphous state, under the normal temperature MOSFET memory of nanocrystalline formation have that low pressure, low-power consumption, volume are little, good characteristic such as high dose and fast reading and writing.
The present invention realizes the reading of two storage areas 210,220, programming and erase operation through word line 300, the first being selected grid 410, second select grid 420, source region 110 and drain region 120 to apply different operating voltages.
In the preferred embodiment of the present invention; There is electric current between source region 110 and drain region 120, to flow in the raceway groove 130; First storage area 210 and second storage area 220 have or not charge storage can influence size of current in its underpart raceway groove 130; When first storage area 210 and second storage area 220 have electric charge; Electric current is very little in its underpart raceway groove 130, otherwise when first storage area 210 and second storage area, 220 no electric charges, electric current is very big in its underpart raceway groove 130; Set in first storage area 210 and second storage area, the 220 bottom raceway grooves 130 little current status and be " 0 "; Set that current states are " 1 " in first storage area 210 and second storage area, the 220 bottom raceway grooves 130, such first storage area 210 and second storage area 220 have or not the state of charge storage can be used as to distinguish stores " 0 " or " 1 " information state, realizes the function that first storage area 210 and second storage area, 220 information stores read.
Please refer to Fig. 2, first storage bit unit of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 2 reads sketch map.The present invention selects grid 410, second to select grid 420, source region 110 and drain region 120 to apply first storage area to said word line 300, the first respectively to read voltage, realize that first storage area reads.
Further, first storage area of selecting grid 410, second to select grid 420, source region 110 and drain region 120 to apply to said word line 300, the first reads voltage and is respectively 2.5V, 2V, 4V, 0V and 1V, realizes that first storage area reads.
In the preferred embodiment of the present invention; Because second selects grid 420 to apply high voltage; Make drain region 120 be diffused in the raceway groove 130 of second storage area, 220 bottoms; Thereby offset the influence of electric current in 220 pairs of raceway grooves 130 of second storage area, only can obtain electric current situation of change in raceway groove 130 zones of first storage area, 210 bottoms, therefore only first storage area 210 has been read.
Please refer to Fig. 3 again, second storage bit unit of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 3 reads sketch map.The present invention selects grid 410, second to select grid 420, source region 110 and drain region 120 to apply second storage area to said word line 300, the first respectively to read voltage, realize that second storage area reads.
Further, second storage area of selecting grid 410, second to select grid 420, source region 110 and drain region 120 to apply to said word line 300, the first reads voltage and is respectively 2.5V, 4V, 2V, 1V and 0V, realizes that second storage area reads.
In the preferred embodiment of the present invention; Because first selects grid 410 to apply high voltage; Make source region 110 be diffused in the raceway groove 130 of first storage area, 210 bottoms; Thereby offset the influence of electric current in 210 pairs of raceway grooves 130 of first storage area, only can obtain electric current situation of change in raceway groove 130 zones of second storage area, 220 bottoms, therefore only second storage area 220 has been read.
When source-drain electrodes voltage is enough high, be enough to cause some high energy electron to cross insulation dielectric layer, and get into the storage bit location on the insulation dielectric layer, this process is called hot electron and injects.And the composition of said insulation dielectric layer is the oxide of silicon or the nitride of silicon, and like materials such as silicon dioxide or silicon nitrides, it is between Semiconductor substrate 100 and memory cell 200.
Please refer to Fig. 4 again, first storage bit unit programming sketch map of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 4.The present invention selects grid 410, second to select grid 420, source region 110 and drain region 120 to apply the first storage area program voltage to said word line 300, the first respectively, realizes the programming of first storage area.
Further, the first storage area program voltage of selecting grid 410, second to select grid 420, source region 110 and drain region 120 to apply to said word line 300, the first is respectively 8V, 1.4V, 5V, 0V and 4V, realizes the programming of first storage area.In preferred embodiment of the present invention; First selects the raceway groove 130 between grid 410 and the word line 300 to set up highfield; This electric field makes electronics quicken to produce the hot electron injection effect and gets in first storage area 210, realizes the programming operation to first storage area 210.
Please refer to Fig. 5 again, second storage bit unit programming sketch map of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 5.The present invention selects grid, said second to select grid, said source region and said drain region to apply the second storage area program voltage to said word line, said first respectively, realizes the programming of second storage area.
Further, the second storage area program voltage of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first is respectively 8V, 5V, 1.4V, 4V and 0V, realizes the programming of second storage area.In preferred embodiment of the present invention; Second selects the raceway groove 130 between grid 420 and the word line 300 to set up highfield; This electric field makes electronics quicken to produce the hot electron injection effect and gets in second storage area 220, realizes the programming operation to second storage area 220.
Please refer to Fig. 6, first storage bit unit and second storage bit unit of the gate-division type flash memory of the said shared memory cell for preferred embodiment of the present invention of Fig. 6 are wiped sketch map.The present invention selects grid, said second to select grid, said source region and said drain region to apply cell erase voltage to said word line, said first respectively, realizes that first storage area and second storage area wipe.
Further, the cell erase voltage of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first is respectively-5V, F, F, F and F, realizes that first storage area and second storage area wipe.Wherein, F is an earthed voltage.Apply under the operating voltage condition at this; The electronics FN (Fowler-Nordheim) under high electric field that is stored in first storage area 210 and second storage area 220 is tunneling to Semiconductor substrate 100 ends; Flow away through Semiconductor substrate 100 ends, realize the erase operation of first storage area 210 and second storage area 220.
In sum; The gate-division type flash memory of the shared memory cell that the present invention proposes; Because its shared two structures of grid of selecting can realize nanocrystalline part is stored; Thereby realized the function of single nanocrystalline device multibyte storage, realized keeping gate-division type flash memory not have the advantage of wiping when byte storage area dwindles.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (11)
1. the gate-division type flash memory of a shared memory cell is characterized in that, comprising:
Semiconductor substrate has the source region and the drain region that are provided with at interval on it;
Channel region is between said source region and drain region;
Memory cell is positioned at said channel region top;
Word line is positioned at said memory cell top;
First selects grid and second to select grid, lays respectively at said word line and memory cell both sides,
Wherein, said memory cell comprises first storage area and second storage area, and said first storage area contiguous first is selected grid, and said second storage area contiguous second is selected grid, and said memory cell is nanocrystalline memory cell.
2. the gate-division type flash memory of shared memory cell according to claim 1; It is characterized in that; Selecting grid, said second to select grid, said source region and said drain region to apply first storage area to said word line, said first respectively reads voltage, realizes that first storage area reads.
3. the gate-division type flash memory of shared memory cell according to claim 2; It is characterized in that; First storage area of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first reads voltage and is respectively 2.5V, 2V, 4V, 0V and 1V, realizes that first storage area reads.
4. the gate-division type flash memory of shared memory cell according to claim 1; It is characterized in that; Selecting grid, said second to select grid, said source region and said drain region to apply second storage area to said word line, said first respectively reads voltage, realizes that second storage area reads.
5. the gate-division type flash memory of shared memory cell according to claim 4; It is characterized in that; Second storage area of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first reads voltage and is respectively 2.5V, 4V, 2V, 1V and 0V, realizes that second storage area reads.
6. the gate-division type flash memory of shared memory cell according to claim 1; It is characterized in that; Select grid, said second to select grid, said source region and said drain region to apply the first storage area program voltage to said word line, said first respectively, realize the programming of first storage area.
7. the gate-division type flash memory of shared memory cell according to claim 6; It is characterized in that; The first storage area program voltage of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first is respectively 8V, 1.4V, 5V, 0V and 4V, realizes the programming of first storage area.
8. the gate-division type flash memory of shared memory cell according to claim 1; It is characterized in that; Select grid, said second to select grid, said source region and said drain region to apply the second storage area program voltage to said word line, said first respectively, realize the programming of second storage area.
9. the gate-division type flash memory of shared memory cell according to claim 8; It is characterized in that; The second storage area program voltage of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first is respectively 8V, 5V, 1.4V, 4V and 0V, realizes the programming of second storage area.
10. the gate-division type flash memory of shared memory cell according to claim 1; It is characterized in that; Select grid, said second to select grid, said source region and said drain region to apply cell erase voltage to said word line, said first respectively, realize that first storage area and second storage area wipe.
11. the gate-division type flash memory of shared memory cell according to claim 10; It is characterized in that; The cell erase voltage of selecting grid, said second to select grid, said source region and said drain region to apply to said word line, said first is respectively-and 5V, F, F, F and F, realize that first storage area and second storage area wipe.
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| CN101819978B (en) * | 2010-04-29 | 2015-05-27 | 上海华虹宏力半导体制造有限公司 | Non-contact nano-crystalline split-gate flash memory for sharing word line |
| CN103366810B (en) * | 2013-07-26 | 2017-07-28 | 上海华虹宏力半导体制造有限公司 | EEPROM memory array |
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