CN101777521B - Manufacturing method of split-gate type flash memory of shared word line - Google Patents
Manufacturing method of split-gate type flash memory of shared word line Download PDFInfo
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- CN101777521B CN101777521B CN 201010102356 CN201010102356A CN101777521B CN 101777521 B CN101777521 B CN 101777521B CN 201010102356 CN201010102356 CN 201010102356 CN 201010102356 A CN201010102356 A CN 201010102356A CN 101777521 B CN101777521 B CN 101777521B
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Abstract
The invention provides manufacturing method of a split-gate type flash memory of a shared word line. The split-gate type flash memory of the obtained shared word line enables two memory bit units to share one word line, realizes the read, programming and the erasure of the memory bit units by applying different working voltages to the word line, two control gates and a source drain area, can effectively reduce the area of a small chip under the condition of keeping the electric isolation of the chip unchanged due to a shared bit line structure and also prevent the problem of erasure and is beneficial to strengthening a tunnelling electric field when a device is erased due to a self-aligned structure formed by a floating gate positioned on a top end and the work line, thereby effectively reducing the erasure voltage.
Description
Technical field
The present invention relates to semiconductor design and make the field, and be particularly related to a kind of manufacturing method of split-gate type flash memory of shared word line.
Background technology
Flash memory is convenient with it, the storage density height, and advantages such as good reliability become the focus of studying in the non-volatility memorizer.Since first flash memory products comes out from the 1980s, development and the demand of each electronic product to storing along with technology, flash memory is widely used in mobile phone, notebook, in movement such as palmtop PC and USB flash disk and the communication apparatus, flash memory is a kind of non-volatility memory, its operation principles is to control the switch of gate pole passage to reach the purpose of storage data by the critical voltage that changes transistor or memory cell, make the data that are stored in the memory can be because power interruptions does not disappear, and flash memory be a kind of special construction of electric erasable and programmable read-only memory.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Yet existing flash memory is in the high storage density of marching toward more, owing to be subjected to the restriction of program voltage, improve storage density by reduction of device size and will face very big challenge, thereby the flash memory of development high storage density is the important motive force of flash memory technology development.Traditional flash memory owing to be subjected to the restriction of structure, realizes that the program voltage of device further reduces to be faced with very big challenge in the high storage density of marching toward more.
Generally speaking, flash memory is the combination of grid dividing structure or stacking gate structure or two kinds of structures.Gate-division type flash memory is because its special structure, compare the stacking gate flash memory and all embody its particular performances advantage in programming with when wiping, therefore divide grid formula structure owing to have high programming efficiency, the structure of word line can be avoided advantages such as " cross and wipe ", uses particularly extensive.Thereby but since gate-division type flash memory with respect to the stacking gate flash memory many a word line make area of chip also can increase, the size that therefore how further reduces chip in the raising chip performance is to need the problem of solution badly.
Summary of the invention
The present invention proposes a kind of manufacturing method of split-gate type flash memory of shared word line, can dwindle area of chip effectively under the constant situation of the electric isolation performance that keeps chip, also can reduce erasing voltage simultaneously, avoids the problem of wiping.
In order to achieve the above object, the present invention proposes a kind of manufacturing method of split-gate type flash memory of shared word line, comprises the following steps:
Semi-conductive substrate is provided, and deposition of silica layer, floating gate polysilicon layer and silicon nitride layer successively;
Described silicon nitride layer is carried out dry etching until exposing described floating gate polysilicon layer, form a plurality of grooves;
Floating gate polysilicon layer in the described groove is carried out dry etching, form the floating boom inclined-plane;
At the even oxide of said structure surface deposition one deck and it is carried out dry etching expose described silicon nitride layer top and the described floating gate polysilicon layer of part, form the side wall oxide in described recess sidewall;
In said structure surface deposition isolation oxide;
At said structure surface deposition control gate polysilicon layer;
Described control gate polysilicon layer and isolation oxide are carried out dry etching, until the floating gate polysilicon layer that exposes described silicon nitride layer top and part bottom portion of groove;
The described floating gate polysilicon layer that exposes is carried out dry etching, and the further silicon dioxide layer of wet etching under it, until exposing described Semiconductor substrate;
The Semiconductor substrate of bottom portion of groove is carried out ion inject, form bit line;
Grind at said structure surface deposition high density plasma oxide and to it, until exposing described silicon nitride layer top;
Wet etching is removed described silicon nitride layer, and the floating gate polysilicon layer and the wet etching removal silicon dioxide layer that further utilize the dry etching removal to expose, until exposing Semiconductor substrate;
At said structure deposition tunneling oxide layer and word line polysilicon;
Described word line polysilicon ground expose described high density plasma oxide.
Further, described floating gate polysilicon layer has cutting-edge structure through an end of the close word line of floating boom that this method manufacturing obtains, and itself and described word line form self-alignment structure.
Further, the thickness of described silicon dioxide layer is more than or equal to 100 dusts.
Further, the thickness of described floating gate polysilicon layer is 600～800 dusts.
Further, the thickness of described silicon nitride layer is 4000～5000 dusts.
Further, the thickness of described even oxide is 200～500 dusts.
Further, the thickness of described isolation oxide is more than or equal to 100 dusts.
Further, the thickness of described control gate polysilicon layer is 500～1000 dusts.
Further, the thickness of described high density plasma oxide is 2000～5000 dusts.
Further, the thickness of described tunneling oxide layer is 100～200 dusts.
Further, the thickness of described word line polysilicon is 1500～3000 dusts.
The manufacturing method of split-gate type flash memory of the shared word line that the present invention proposes, the gate-division type flash memory of resulting shared word line, two storage bit unit are shared word line of use, by to the word line, two control gates and source drain region apply different operating voltages and realize reading, programming and wiping storage bit unit, the structure of share bit lines make gate-division type flash memory its can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.Have most advanced and sophisticated floating boom and word line and form self-alignment structure, strengthen F-N tunnelling principle according to the tip, under the situation of identical erasing voltage, have most advanced and sophisticated floating boom and can obtain stronger tunnelling electric field, thereby be more conducive to the tunnelling of electronics in the floating boom, thereby can be under the situation of low erasing voltage, obtain conventional no cutting-edge structure floating boom wipe performance, so the erasing voltage of this structure can effectively reduce memory device operation the time.
Description of drawings
Fig. 1～Figure 13 shows that manufacturing method of split-gate type flash memory flow chart of the shared word line of preferred embodiment of the present invention.
Figure 14 shows that the gate-division type flash memory structural representation of the shared word line of preferred embodiment of the present invention.
Embodiment
In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
The present invention proposes a kind of manufacturing method of split-gate type flash memory of shared word line, and it can dwindle area of chip effectively under the constant situation of the electric isolation performance that keeps chip, also can reduce erasing voltage simultaneously, avoids the problem of wiping.
Please refer to Fig. 1, Figure 1 shows that the manufacturing method of split-gate type flash memory flow chart of the shared word line of preferred embodiment of the present invention.The present invention proposes a kind of manufacturing method of split-gate type flash memory of shared word line, comprises the following steps:
As shown in fig. 1, the invention provides semi-conductive substrate 100, and deposition of silica layer 110, floating gate polysilicon layer 120 and silicon nitride layer 130 successively; The thickness of described silicon dioxide layer 110 is more than or equal to 100 dusts, and the thickness of described floating gate polysilicon layer 120 is 600～800 dusts, and the thickness of described silicon nitride layer 130 is 4000～5000 dusts.
Please refer to Fig. 2 again, described silicon nitride layer 130 is carried out dry etching until exposing described floating gate polysilicon layer 120, form a plurality of grooves 200 at described silicon nitride layer 130;
As shown in Figure 3, the floating gate polysilicon layer 120 in the described groove 200 is carried out dry etching, form floating boom inclined-plane 121;
Please refer to Fig. 4 and Fig. 5 again, at the even oxide 300 of said structure surface deposition one deck, its thickness is 200～500 dusts, and then it is carried out dry etching exposes described silicon nitride layer 130 tops and the described floating gate polysilicon layer 120 of part, forms side wall oxide 310 in described recess sidewall;
Please refer to Fig. 6, in said structure surface deposition isolation oxide 400, the thickness of described isolation oxide 400 is more than or equal to 100 dusts;
Then at said structure surface deposition control gate polysilicon layer 500, its thickness is 500～1000 dusts;
As shown in Figure 7, described control gate polysilicon layer 500 and isolation oxide 400 are carried out dry etching, until the floating gate polysilicon layer 120 that exposes described silicon nitride layer 130 tops and part groove 200 bottoms;
Then the described floating gate polysilicon layer that exposes 120 is carried out dry etching, and the further silicon dioxide layer 110 of wet etching under it, until exposing described Semiconductor substrate 100;
Please refer to Fig. 8 again, the Semiconductor substrate 100 of groove 200 bottoms is carried out ion inject, form bit line;
Then with reference to figure 9 and Figure 10, at said structure surface deposition high density plasma oxide 600, its thickness is 2000～5000 dusts, then it is ground, until exposing described silicon nitride layer 130 tops;
Please refer to Figure 11 and Figure 12 again, wet etching is removed described silicon nitride layer 130, and further utilizes dry etching to remove floating gate polysilicon layer 120 and the silicon dioxide layer 110 that exposes, until exposing Semiconductor substrate 100;
Please refer to Figure 13 at last, at said structure deposition tunneling oxide layer 700 and word line polysilicon 800, described tunneling oxide layer 700 thickness are 100～200 dusts, described word line polysilicon 800 thickness are 1500～3000 dusts, and described word line polysilicon 800 are ground expose described high density plasma oxide 600.
Please refer to Figure 14, Figure 14 shows that the gate-division type flash memory structural representation of the shared word line of preferred embodiment of the present invention.The preferred embodiment according to the present invention, the floating boom 22 that described floating gate polysilicon layer obtains through this method manufacturing, 32 ends near word line 40 have cutting-edge structure 50, and itself and described word line 40 form self-alignment structure.
The gate-division type flash memory of the shared word line that the present invention proposes, two storage bit unit 20,30 are shared word line 40 of use, by to word line 40, two control gates 21,31 and source drain region 11,12 apply different operating voltages and realize storage bit unit 20,30 read, programme and wipe, the structure of share bit lines make gate-division type flash memory its can be under the constant situation of the electric isolation performance that keeps chip, dwindle area of chip effectively, also can avoid the problem of wiping simultaneously.Have most advanced and sophisticated 50 floating boom 22,32 with word line 40 formation self-alignment structures, strengthen F-N tunnelling principle according to the tip, under the situation of identical erasing voltage, have most advanced and sophisticated floating boom and can obtain stronger tunnelling electric field, thereby be more conducive to the tunnelling of electronics in the floating boom, thereby can be under the situation of low erasing voltage, obtain conventional no cutting-edge structure floating boom wipe performance, so the erasing voltage of this structure can effectively reduce memory device operation the time.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. the manufacturing method of split-gate type flash memory of a shared word line is characterized in that, comprises the following steps:
Semi-conductive substrate is provided, and deposition of silica layer, floating gate polysilicon layer and silicon nitride layer successively;
Described silicon nitride layer is carried out dry etching until exposing described floating gate polysilicon layer, form a plurality of grooves;
Floating gate polysilicon layer in the described groove is carried out dry etching, form the floating boom inclined-plane;
At the even oxide of said structure surface deposition one deck and it is carried out dry etching expose described silicon nitride layer top and the described floating gate polysilicon layer of part, form the side wall oxide in described recess sidewall;
In said structure surface deposition isolation oxide;
At said structure surface deposition control gate polysilicon layer;
Described control gate polysilicon layer and isolation oxide are carried out dry etching, until the part floating gate polysilicon layer that exposes described silicon nitride layer top and bottom portion of groove;
The described floating gate polysilicon layer that exposes is carried out dry etching, and the further silicon dioxide layer of wet etching under it, until exposing described Semiconductor substrate;
The Semiconductor substrate of bottom portion of groove is carried out ion inject, form bit line;
Grind at said structure surface deposition high density plasma oxide and to it, until exposing described silicon nitride layer top;
Wet etching is removed described silicon nitride layer, and the floating gate polysilicon layer and the wet etching removal silicon dioxide layer that further utilize the dry etching removal to expose, until exposing Semiconductor substrate;
At said structure deposition tunneling oxide layer and word line polysilicon;
Described word line polysilicon ground expose described high density plasma oxide;
Described floating gate polysilicon layer has cutting-edge structure through an end of the close word line of floating boom that this method manufacturing obtains, and itself and described word line form self-alignment structure.
2. the manufacturing method of split-gate type flash memory of shared word line according to claim 1 is characterized in that, the thickness of described silicon dioxide layer is more than or equal to 100 dusts.
3. the manufacturing method of split-gate type flash memory of shared word line according to claim 1 is characterized in that, the thickness of described floating gate polysilicon layer is 600～800 dusts.
4. the manufacturing method of split-gate type flash memory of shared word line according to claim 1 is characterized in that, the thickness of described silicon nitride layer is 4000～5000 dusts.
5. the manufacturing method of split-gate type flash memory of shared word line according to claim 1 is characterized in that, the thickness of described even oxide is 200～500 dusts.
6. the manufacturing method of split-gate type flash memory of shared word line according to claim 1 is characterized in that, the thickness of described isolation oxide is more than or equal to 100 dusts.
7. the manufacturing method of split-gate type flash memory of shared word line according to claim 1 is characterized in that, the thickness of described control gate polysilicon layer is 500～1000 dusts.
8. the manufacturing method of split-gate type flash memory of shared word line according to claim 1 is characterized in that, the thickness of described high density plasma oxide is 2000～5000 dusts.
9. the manufacturing method of split-gate type flash memory of shared word line according to claim 1 is characterized in that, the thickness of described tunneling oxide layer is 100～200 dusts.
10. the manufacturing method of split-gate type flash memory of shared word line according to claim 1 is characterized in that, the thickness of described word line polysilicon is 1500～3000 dusts.
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103050446B (en) * | 2012-12-20 | 2016-12-28 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and forming method thereof |
| CN103367262B (en) * | 2013-07-24 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | The forming method of flash memory cell |
| CN104425499A (en) * | 2013-08-29 | 2015-03-18 | 林崇荣 | Memory body element, memory body array and operation method thereof |
| CN104362151A (en) * | 2014-11-20 | 2015-02-18 | 上海华虹宏力半导体制造有限公司 | NOR-type flash memory structure and preparation method thereof |
| CN104538367B (en) * | 2014-12-30 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | Mirror image Split-gate flash memory and forming method thereof |
| CN104465524B (en) * | 2014-12-30 | 2018-04-27 | 上海华虹宏力半导体制造有限公司 | Mirror image Split-gate flash memory and forming method thereof |
| CN106206598B (en) * | 2016-07-27 | 2019-06-28 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory device making method |
| CN106206451B (en) * | 2016-07-27 | 2019-06-28 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory device making method |
| CN107946303A (en) * | 2017-11-15 | 2018-04-20 | 上海华虹宏力半导体制造有限公司 | The preparation method of flash cell |
| CN112750790B (en) * | 2021-01-22 | 2023-11-21 | 上海华虹宏力半导体制造有限公司 | Flash memory and method for manufacturing the same |
| CN112750789B (en) * | 2021-01-22 | 2024-02-06 | 上海华虹宏力半导体制造有限公司 | Split gate flash memory and preparation method thereof |
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| CN101465161A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Gate-division type flash memory sharing word line |
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| US6542412B2 (en) * | 2000-09-06 | 2003-04-01 | Halo Lsi, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic flash memory |
| CN1794458A (en) * | 2004-09-22 | 2006-06-28 | 三星电子株式会社 | Non-volatile memory and method of fabricating same |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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