CN101814510B - The contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line - Google Patents
The contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line Download PDFInfo
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Abstract
The contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of the shared word line that the present invention proposes, two storage bit unit are shared use wordline by the flush memory device obtained, reading to storage bit unit, programming and erasing is realized by applying different operating voltage to wordline, the first bit line and the second bit line, the structure of share bit lines makes gate-division type flash memory, and it can when keeping the electric isolation performance of chip constant, effectively reduce the area of chip, also can avoid the problem of wiping simultaneously.Adopt contactless design simultaneously, make flush memory device have size little, the feature of technique and CMOS traditional handicraft compatibility, is conducive to device size and reduces further.
Description
Technical field
The present invention relates to semiconductor design and manufacture field, and in particular to a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line.
Background technology
The advantages such as flash memory is convenient with it, and storage density is high, good reliability become the focus studied in non-volatility memorizer.Since coming out from first flash memory products 1980s, along with the development of technology and each electronic product are to the demand stored, flash memory is widely used in mobile phone, notebook, in the mobile and communication apparatus such as palmtop PC and USB flash disk, flash memory is a kind of nonvolatile memory, its operation principles is that the critical voltage by changing transistor or memory cell controls the switch of gate pole passage to reach the object storing data, storage data in memory can not be disappeared because of power interruptions, and flash memory is electric erasable and a kind of special construction of programmable read-only memory.Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
But existing flash memory is marching toward more when high storage density, owing to being subject to the restriction of program voltage, improve storage density by reduction of device size and will face very large challenge, the flash memory thus developing high storage density is the important impetus of flash memory technology development.Traditional flash memory is marching toward more when high storage density, and owing to being subject to the restriction of structure, the program voltage realizing device reduces to be faced with very large challenge further.
Generally speaking, flash memory is the combination of grid dividing structure or stacking gate structure or two kinds of structures.Gate-division type flash memory is due to its special structure, compare stacking gate flash memory all embodies its uniqueness performance advantage when programming and erasing, therefore sub-gate structure is owing to having high programming efficiency, and the structure of wordline can avoid advantages such as " crossing erasing ", applies particularly extensive.But make the area of chip also can increase due to gate-division type flash memory wordline many relative to stacking gate flash memory, the size therefore how reducing chip further while improving chip performance needs the problem of solution badly.
Simultaneously, along with memory device size constantly reduces the continuous rising with storage density, the size being formed at the contact hole in inner layer dielectric layer also can become less, but this inner layer dielectric layer must keep rational thickness, this contact hole is made to need to keep sizable depth-to-width ratio (depth/width), thus make the contact point in Semiconductor substrate occupy the sizable ratio of whole memory cell area, become restriction memory device size and the key factor that further develops of storage density.
Summary of the invention
The present invention proposes a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line, and its flush memory device obtained when keeping the electric isolation performance of chip constant, can reduce the area of chip effectively, also can avoid the problem of wiping simultaneously.
In order to achieve the above object, the present invention proposes a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line, comprising:
Semiconductor substrate, it has spaced source region and drain region;
Channel region, between described source region and drain region;
First bit line and the second bit line, be connected to described source region and drain region;
First floating boom, is arranged at above described channel region and source region;
Second floating boom, is arranged at above described channel region and drain region, and described first floating boom and the second floating boom form the first storage bit unit and the second storage bit unit respectively;
Wordline, comprise Part I and Part II, described Part I is above described channel region and between described first floating boom and the second floating boom, described Part II is connected to described Part I top, and be positioned at above described first floating boom and the second floating boom, described Part II top extends to above described first bit line and the second bit line, and by insulating barrier and described first bit line and the second bit line top isolated.
Wherein, described first floating boom and the second floating boom are silicon nitride floating gates.
Further, respectively the first storage bit unit is applied to described wordline, described first bit line and described second bit line and read voltage, realize the first storage bit unit and read.
Further, 2.5V, 0V and 1.5V are respectively to the first storage bit unit reading voltage that described wordline, described first bit line and described second bit line apply, realize the first storage bit unit and read.
Further, respectively the second storage bit unit is applied to described wordline, described first bit line and described second bit line and read voltage, realize the second storage bit unit and read.
Further, 2.5V, 1.5V and 0V are respectively to the second storage bit unit reading voltage that described wordline, described first bit line and described second bit line apply, realize the second storage bit unit and read.
Further, respectively the first storage bit unit program voltage is applied to described wordline, described first bit line and described second bit line, realize the first storage bit unit programming.
Further, 4V, 7.5V and 0V are respectively to the first storage bit unit program voltage that described wordline, described first bit line and described second bit line apply, realize the first storage bit unit programming.
Further, respectively the second storage bit unit program voltage is applied to described wordline, described first bit line and described second bit line, realize the second storage bit unit programming.
Further, 4V, 0V and 7.5V are respectively to the second storage bit unit program voltage that described wordline, described first bit line and described second bit line apply, realize the second storage bit unit programming.
Further, respectively storage bit unit erasing voltage is applied to described wordline, described first bit line and described second bit line, realize the first storage bit unit and the erasing of the second storage bit unit.
Further, 0V, 11V and 11V are respectively to the storage bit unit erasing voltage that described wordline, described first bit line and described second bit line apply, realize the first storage bit unit and the erasing of the second storage bit unit.
The contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of the shared word line that the present invention proposes, two storage bit unit are shared use wordline, reading to storage bit unit, programming and erasing is realized by applying different operating voltage to wordline, the first bit line and the second bit line, the structure of share bit lines makes gate-division type flash memory, and it can when keeping the electric isolation performance of chip constant, effectively reduce the area of chip, also can avoid the problem of wiping simultaneously.Adopt contactless design simultaneously, make flush memory device have size little, the feature of technique and CMOS traditional handicraft compatibility, is conducive to device size and reduces further.
Accompanying drawing explanation
Figure 1 shows that the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory structural representation of the shared word line of present pre-ferred embodiments.
Embodiment
In order to more understand technology contents of the present invention, institute's accompanying drawings is coordinated to be described as follows especially exemplified by specific embodiment.
The present invention proposes a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line, and its flush memory device obtained when keeping the electric isolation performance of chip constant, can reduce the area of chip effectively, also can avoid the problem of wiping simultaneously.
Please refer to Fig. 1, Figure 1 shows that the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory structural representation of the shared word line of present pre-ferred embodiments.The present invention proposes a kind of contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line, comprising: Semiconductor substrate 100, it has spaced source region 110 and drain region 120, channel region 130, between described source region 110 and drain region 120, first bit line 210 and the second bit line 220, is connected to described source region 110 and drain region 120, first floating boom 310, is arranged at above described channel region 130 and source region 110, second floating boom 320, is arranged at above described channel region 130 and drain region 120, and described first floating boom 310 and the second floating boom 320 form the first storage bit unit and the second storage bit unit respectively, wordline 500, comprise Part I 510 and Part II 520, described Part I 510 is above described channel region 130 and between described first floating boom 310 and the second floating boom 320, described Part II 520 is connected to described Part I 510 top, and be positioned at above described first floating boom 310 and the second floating boom 320, described Part II 520 top extends to above described first bit line 210 and the second bit line 220, and by insulating barrier 610, 620 with described first bit line 210 and the second bit line 220 top isolated, wherein, described first floating boom 310 and the second floating boom 320 are silicon nitride floating gates.
According to present pre-ferred embodiments, the first storage bit unit that described first floating boom 310 and the second floating boom 320 are formed respectively and the second storage bit unit are silicon nitride floating gates.First bit line 210 and the second bit line 220 of the present invention, be directly connected in described source region 110 and drain region 120 respectively, and do not need the mode forming contact point by making contact hole on a semiconductor substrate 100 to connect, there is the design of non-contact-point, make flush memory device have less size, be conducive to device size and reduce further.
In present pre-ferred embodiments, electric current is had to flow between source region 110 and drain region 120 in raceway groove 130, the first storage bit unit that described first floating boom 310 and the second floating boom 320 are formed respectively and the second storage bit unit can affect size of current in raceway groove 130 with or without charge storage, when the first storage bit unit that described first floating boom 310 and the second floating boom 320 are formed respectively and the second storage bit unit have electric charge, in raceway groove 130, electric current is very little, otherwise when the first storage bit unit that described first floating boom 310 and the second floating boom 320 are formed respectively and the second storage bit unit are without electric charge, in raceway groove 130, electric current is very large, to set in raceway groove 130 small area analysis state as " 0 ", to set in raceway groove 130 current state as " 1 ", the first storage bit unit that described like this first floating boom 310 and the second floating boom 320 are formed respectively and the second storage bit unit can as differentiation storage " 0 " or " 1 " information states with or without the state of charge storage, realize the function of the first storage bit unit and the second storage bit unit information storage reading.
According to present pre-ferred embodiments, respectively the first storage bit unit is applied to described wordline 500, described first bit line 210 and described second bit line 220 and read voltage, realize the first storage bit unit and read.
Further, 2.5V, 0V and 1.5V are respectively to the first storage bit unit reading voltage that described wordline 500, described first bit line 210 and described second bit line 220 apply, realize the first storage bit unit and read.
According to present pre-ferred embodiments, respectively the second storage bit unit is applied to described wordline 500, described first bit line 210 and described second bit line 220 and read voltage, realize the second storage bit unit and read.
Further, 2.5V, 1.5V and 0V are respectively to the second storage bit unit reading voltage that described wordline 500, described first bit line 210 and described second bit line 220 apply, realize the second storage bit unit and read.
Source-drain electrodes voltage between source region 110 and drain region 120 is enough high, is enough to cause some high energy electron to cross insulation dielectric layer, and enters the storage space unit on insulation dielectric layer, and this process is called that hot electron injects.And the composition of described insulation dielectric layer is the oxide of silicon or the nitride of silicon, as the material such as silicon dioxide or silicon nitride, between its first storage bit unit formed respectively at Semiconductor substrate 100 and described first floating boom 310 and the second floating boom 320 and the second storage bit unit.
According to present pre-ferred embodiments, respectively the first storage bit unit program voltage is applied to described wordline 500, described first bit line 210 and described second bit line 220, realize the first storage bit unit programming.In present pre-ferred embodiments, after applying read work voltage, electronics is had to flow to source region 110 from drain region 120 in raceway groove 130, portions of electronics is injected in the first storage bit unit of described first floating boom 310 formation by hot electron injection mode, realizes the programming operation of the first storage bit unit.
Further, 4V, 7.5V and 0V are respectively to the first storage bit unit program voltage that described wordline 500, described first bit line 210 and described second bit line 220 apply, realize the first storage bit unit programming.
According to present pre-ferred embodiments, respectively the second storage bit unit program voltage is applied to described wordline 500, described first bit line 210 and described second bit line 220, realize the second storage bit unit programming.In present pre-ferred embodiments, after applying read work voltage, electronics is had to flow to drain region 120 from source region 110 in raceway groove 130, portions of electronics is injected in the second storage bit unit of the second floating boom 320 formation by hot electron injection mode, realizes the programming operation of the second storage bit unit.
Further, 4V, 0V and 7.5V are respectively to the second storage bit unit program voltage that described wordline 500, described first bit line 210 and described second bit line 220 apply, realize the second storage bit unit programming.
According to present pre-ferred embodiments, respectively storage bit unit erasing voltage is applied to described wordline 500, described first bit line 210 and described second bit line 220, realize the first storage bit unit and the erasing of the second storage bit unit.Under this applying operating voltage condition, the electronics FN (Fowler-Nordheim) under high electric field being stored in the first storage bit unit that described first floating boom 310 and the second floating boom 320 form respectively and the second storage bit unit is tunneling to bit line 210 and 220 end, flowed away by bit line 210 and 220 end, realize the erase operation of the first storage bit unit and the second storage bit unit.
Further, 0V, 11V and 11V are respectively to the storage bit unit erasing voltage that described wordline 500, described first bit line 210 and described second bit line 220 apply, realize the first storage bit unit and the erasing of the second storage bit unit.
The contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of the shared word line that the present invention proposes, two storage bit unit are shared use wordline, reading to storage bit unit, programming and erasing is realized by applying different operating voltage to wordline, the first bit line and the second bit line, the structure of share bit lines makes gate-division type flash memory, and it can when keeping the electric isolation performance of chip constant, effectively reduce the area of chip, also can avoid the problem of wiping simultaneously.Adopt contactless design simultaneously, make flush memory device have size little, the feature of technique and CMOS traditional handicraft compatibility, is conducive to device size and reduces further.
Although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (11)
1. a contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory for shared word line, is characterized in that, comprising:
Semiconductor substrate, it has spaced source region and drain region;
Channel region, between described source region and drain region;
First bit line and the second bit line, be directly connected in described source region and drain region respectively;
First floating boom, is arranged at above described channel region and source region;
Second floating boom, is arranged at above described channel region and drain region, and described first floating boom and the second floating boom form the first storage bit unit and the second storage bit unit respectively;
Wordline, comprise Part I and Part II, described Part I is above described channel region and between described first floating boom and the second floating boom, described Part II is connected to described Part I top, and be positioned at above described first floating boom and the second floating boom, described Part II top extends to above described first bit line and the second bit line, and by insulating barrier and described first bit line and the second bit line top isolated
Wherein, described first floating boom and the second floating boom are silicon nitride floating gates.
2. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, is characterized in that, applies the first storage bit unit respectively read voltage to described wordline, described first bit line and described second bit line, realizes the first storage bit unit and reads.
3. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 2, it is characterized in that, 2.5V, 0V and 1.5V are respectively to the first storage bit unit reading voltage that described wordline, described first bit line and described second bit line apply, realize the first storage bit unit and read.
4. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, is characterized in that, applies the second storage bit unit respectively read voltage to described wordline, described first bit line and described second bit line, realizes the second storage bit unit and reads.
5. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 4, it is characterized in that, 2.5V, 1.5 V and 0V are respectively to the second storage bit unit reading voltage that described wordline, described first bit line and described second bit line apply, realize the second storage bit unit and read.
6. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, is characterized in that, applies the first storage bit unit program voltage respectively to described wordline, described first bit line and described second bit line, realizes the first storage bit unit programming.
7. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 6, it is characterized in that, 4V, 7.5V and 0V are respectively to the first storage bit unit program voltage that described wordline, described first bit line and described second bit line apply, realize the first storage bit unit programming.
8. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, is characterized in that, applies the second storage bit unit program voltage respectively to described wordline, described first bit line and described second bit line, realizes the second storage bit unit programming.
9. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 8, it is characterized in that, 4V, 0V and 7.5V are respectively to the second storage bit unit program voltage that described wordline, described first bit line and described second bit line apply, realize the second storage bit unit programming.
10. the contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of shared word line according to claim 1, it is characterized in that, respectively storage bit unit erasing voltage is applied to described wordline, described first bit line and described second bit line, realize the first storage bit unit and the erasing of the second storage bit unit.
The contactless SONOS (Silicon Oxide Nitride Oxide Semiconductor) split-grid type flash memory of 11. shared word line according to claim 10, it is characterized in that, 0V, 11V and 11V are respectively to the storage bit unit erasing voltage that described wordline, described first bit line and described second bit line apply, realize the first storage bit unit and the erasing of the second storage bit unit.
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| JP4058219B2 (en) * | 1999-09-17 | 2008-03-05 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit |
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| CN1111905C (en) * | 1998-06-12 | 2003-06-18 | 日本电气株式会社 | Method of forming semiconductor device |
| US6714454B2 (en) * | 1999-12-10 | 2004-03-30 | Yueh Yale Ma | Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell |
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