CN101789429A - Metal-insulator-metal capacitor structure and manufacturing method thereof - Google Patents
Metal-insulator-metal capacitor structure and manufacturing method thereof Download PDFInfo
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- CN101789429A CN101789429A CN200910045899A CN200910045899A CN101789429A CN 101789429 A CN101789429 A CN 101789429A CN 200910045899 A CN200910045899 A CN 200910045899A CN 200910045899 A CN200910045899 A CN 200910045899A CN 101789429 A CN101789429 A CN 101789429A
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Abstract
The invention provides a metal-insulator-metal capacitor structure and a manufacturing method thereof. The capacitor structure comprises a semiconductor substrate, metal-insulator-metal capacitors formed on the semiconductor layer by layer and metal interconnecting layers formed between adjacent two layers of metal-insulator-metal capacitors, wherein at least two layers of metal-insulator-metal capacitors are connected by a metal interconnecting layer in parallel. The metal-insulator-metal capacitor structure has the advantages that: under the condition of not increasing of floor area, the capacities of the metal-insulator-metal capacitors are increased; and the repeated metal-insulator-metal capacitor manufacturing steps in the layers reduce process cost, improve compatibility and facilitate manufacturing process integration and implementation.
Description
Technical field
The present invention relates to a kind of metal-insulator-metal type (metal-insulator-metal is designated hereinafter simply as MIM) capacitance structure, relate in particular to a kind of mim capacitor structure and manufacture method thereof of stacking-type.
Background technology
Capacity cell be usually used in as in the integrated circuits such as radio frequency IC, monolithic microwave IC as electronic passive device.Common capacitance structure such as metal-oxide semiconductor (MOS) (MOS) electric capacity, PN junction electric capacity and MIM electric capacity etc.Wherein, MIM electric capacity provides the electrology characteristic that is better than mos capacitance and PN junction electric capacity in some special applications, this is because mos capacitance and PN junction electric capacity all are subject to itself structure, and electrode is easy to generate cavitation layer when work, causes its frequency characteristic to reduce.And MIM electric capacity can provide frequency and temperature correlated characteristic preferably, and in addition, MIM electric capacity can form in the metal interconnecting stage, had also reduced degree of difficulty and the complexity integrated with the CMOS front-end process.
Fig. 1 to Fig. 3 is the main schematic flow sheet of the manufacture method of existing a kind of MIM electric capacity.
As shown in Figure 1, at first sequential aggradation the first metal layer 1, dielectric layer 3, second metal level 2 form folder one dielectric sandwich structure between the double layer of metal.
Then as shown in Figure 2, etch away second metal level 2 and the dielectric layer 3 in territory, a lateral areas, expose the first metal layer 1.
As shown in Figure 3, on sandwich structure, cover passivation layer 4, and etch two line holes 5, connect the first metal layer 1 and second metal level 2 respectively in the relevant position.Form metal level 6 at last on passivation layer 4 surface and draw lead as interconnection layer.
In this sandwich structure, the first metal layer 1 is as lower electrode plate, and second metal level 2 is as electric pole plate, midfeather the dielectric layer 3 of one deck insulation, constituted a typical MIM electric capacity.
From above-mentioned manufacturing process as can be known, MIM electric capacity is an area capacitance, and the size of its capacity depends primarily on the thickness of dielectric layer 3, and as the first metal layer 1 and second metal level, 2 both corresponding areas of battery lead plate, and the latter's influence is especially obvious.When needs were made jumbo MIM electric capacity, traditional way was the area that increases metal level, yet can make that like this MIM electric capacity takies the space in peripheral devices district, influence device size, improved the difficulty that connects up.
Summary of the invention
The problem that the present invention solves is existing metal-insulator-metal type capacitance structure, takies the space in peripheral devices district when doing big capacity easily, influences device size, improves the wiring difficulty.
For addressing the above problem, the invention provides a kind of metal-insulator-metal type capacitance structure, comprising:
Semiconductor substrate;
The metal-insulator-metal capacitor that on Semiconductor substrate, successively forms;
The metal interconnecting layer that between the adjacent two layers metal-insulator-metal capacitor, forms;
At least two-layer metal-insulator-metal capacitor is in parallel by metal interconnecting layer.
In addition, the present invention also provides a kind of manufacture method of metal-insulator-metal type capacitance structure, at the metal interconnecting layer that successively forms on the Semiconductor substrate between metal-insulator-metal capacitor and the adjacent layer metal-insulator-metal capacitor; Wherein two-layer at least metal-insulator-metal capacitor is by the metal interconnecting layer parallel connection.
Concrete steps are as follows:
On semi-conductive substrate, form the ground floor metal-insulator-metal capacitor;
Form first passivation layer on ground floor metal-insulator-metal capacitor surface, and etching forms metal
The line hole;
Form first metal interconnecting layer on the surface of first passivation layer;
Etching first metal interconnecting layer forms the first top crown interconnection layer and the first bottom crown interconnection layer;
Surface at first metal interconnecting layer forms separator;
On separator, form second layer metal-insulator-metal capacitance;
Form second passivation layer on second layer metal-insulator-metal capacitance surface, and etching formation metal connecting line hole;
Form second metal interconnecting layer in second passivation layer surface;
Etching second metal interconnecting layer forms the second top crown interconnection layer and the second bottom crown interconnection layer;
The described first top crown interconnection layer is connected with the second top crown interconnection layer by the metal connecting line hole, and the first bottom crown interconnection layer is connected with the second bottom crown interconnection layer by the metal connecting line hole.
As possibility, on said structure, repeat the making step of the second layer metal-insulator-metal capacitance and second metal interconnecting layer, can form the metal-insulator-metal type capacitance structure that comprises two above metal-insulator-metal capacitors.
Compared with prior art, the present invention forms stack architecture with the mode of a plurality of metal-insulator-metal capacitors by lamination, and by the metal interconnecting layer parallel connection, has following advantage: do not increase under the situation of area occupied, increased the capacity of metal-insulator-metal capacitor, the metal-insulator-metal capacitor making step of each layer repetition help reducing technology cost and compatibility, and be convenient to processing procedure and integrate and be easy to realize.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Parts same as the prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size in layer and zone.
Fig. 1 to Fig. 3 is the generalized section of the manufacturing process of existing MIM electric capacity;
Fig. 4 is a metal-insulator-metal type capacitance structure manufacture method flow chart of the present invention;
Fig. 5 is the flow chart of formation MIM electric capacity of the present invention;
Fig. 6 to Figure 16 is the specific embodiment generalized section of the manufacturing process of metal-insulator-metal capacitor of the present invention.
Embodiment
In manufacturing process, because MIM electric capacity formed in the metal interconnecting stage, what utilize is the metal interconnect structure manufacturing of interlayer, so can adopt the MIM electric capacity in the individual layer is together in parallel, obtain the scheme of a jumbo MIM electric capacity, to substitute the way that enlarges MIM battery lead plate area, can not increase the horizontal area of MIM electric capacity like this.
The invention provides a kind of embodiment of metal-insulator-metal capacitor manufacture method, at MIM electric capacity that successively forms on the Semiconductor substrate and the metal interconnecting layer between the adjacent layer MIM electric capacity; Wherein two-layer at least MIM electric capacity forms parallel connection by metal interconnecting layer.Basic step comprises as shown in Figure 4:
S1) form ground floor MIM electric capacity on semi-conductive substrate, described MIM electric capacity comprises top crown metal level, bottom crown metal level and dielectric layer between the two;
S2) form first passivation layer at ground floor MIM capacitive surface, and etching forms the metal connecting line hole;
S3) form first metal interconnecting layer on the surface of first passivation layer, described the first metal layer is copper, aluminium or albronze;
S4) etching first metal interconnecting layer forms the first top crown interconnection layer and the first bottom crown interconnection layer, the described first top crown interconnection layer is connected with the top crown metal level of ground floor MIM electric capacity by the metal connecting line hole, and the first bottom crown interconnection layer is connected with the bottom crown metal level of ground floor MIM electric capacity by the metal connecting line hole;
S5) form separator on the surface of described first metal interconnecting layer;
S6) form second layer MIM electric capacity on separator, described second layer MIM capacitor manufacturing method is identical with ground floor MIM electric capacity;
S7) form second passivation layer at second layer MIM capacitive surface, and etching forms the metal connecting line hole;
S8) form second metal interconnecting layer on the surface of second passivation layer; Described second metal level also is copper, aluminium or albronze;
S9) etching second metal interconnecting layer forms the second top crown interconnection layer and the second bottom crown interconnection layer.The described second top crown interconnection layer is connected with the top crown metal level of the first top crown interconnection layer and second layer MIM electric capacity by the metal connecting line hole, and the second bottom crown interconnection layer passes through that the metal connecting line hole is connected with the first bottom crown interconnection layer and the bottom crown metal level of second layer MIM electric capacity;
S10) repeat the making step of the described second layer MIM electric capacity and second metal interconnecting layer, can form the metal-insulator-metal type capacitance structure that comprises two above MIM electric capacity.
Form the step of MIM electric capacity in the said process, optionally embodiment comprises as shown in Figure 5:
S11) presumptive area on Semiconductor substrate or separator forms the bottom crown metal level;
S12) form dielectric layer at described bottom crown layer on surface of metal;
S13) form the top crown metal level in dielectric layer surface;
S14) etch away part top crown metal level and dielectric layer, expose the bottom crown metal level.
Wherein, the top crown metal level of MIM electric capacity and bottom crown metal level can be copper, aluminium or albronze, and thickness range is
Dielectric layer material can be silicon nitride or silicon oxynitride, and thickness range is
And passivation material can the wherein a kind of or combination for silica, silicon nitride, silicon oxynitride.Insolated layer materials also can the wherein a kind of or combination for silica, silicon nitride, silicon oxynitride.The thickness range of passivation layer and separator is determined according to the actual floor height of device individual layer.
According to above-mentioned embodiment, Fig. 6 to Figure 18 is the optional embodiment generalized section of of metal-insulator-metal type capacitance structure manufacturing process.
As shown in Figure 6, form bottom crown metal level 101, dielectric layer 102, top crown metal level 103 in proper order in the presumptive area on Semiconductor substrate 100 earlier.
Wherein, bottom crown metal level 101 and top crown metal level 103 can utilize sputter (sputtering) technology to form, and material can be copper, aluminium or albronze, and concrete component content can be selected with the working band of device as required, and thickness range is
Dielectric layer 102 can utilize physical vapor deposition technologies such as (PVD) to form, and material can be silicon nitride or silicon oxynitride, and thickness range is
Then as shown in Figure 7, etch away the subregion of top crown metal level 103 and dielectric layer 102, expose bottom crown metal level 101.So just, on Semiconductor substrate, formed the ground floor MIM electric capacity of sandwich structure.
As shown in Figure 8, utilize PECVD (plasma-reinforced chemical vapor deposition) technology to cover deposition on the surface of ground floor MIM electric capacity and form first passivation layer 104, its material is a kind of or its combination in silica, tetraethoxysilane, silicon nitride, the silicon oxynitride.Thickness is selected to determine according to the interfloor height of device.
As shown in Figure 9, on first passivation layer 104, the zone of corresponding ground floor MIM electric capacity utilizes mask, exposure, etching to form two perforation, until exposing top crown metal level 103 and bottom crown metal level 101 respectively.With top crown metal level 103 and bottom crown metal level 101 is metal seed layer, in two perforation, electroplate growth copper, aluminium or aluminium copper respectively, upper surface at first passivation layer 104 carries out chemistry or mechanical polishing then, forms metal connecting line hole 105 and metal connecting line hole 106.As shown in figure 10, on the surface of first passivation layer 104, deposit a layer thickness and be
First metal interconnecting layer, material is chosen as copper, aluminium or albronze; Etching first metal interconnecting layer forms the first top crown interconnection layer 107 and the first bottom crown interconnection layer 108, make the described first top crown interconnection layer 107 be connected with the top crown metal level 103 of ground floor MIM electric capacity by metal connecting line hole 105, the first bottom crown interconnection layer 108 is connected with the bottom crown metal level 101 of ground floor MIM electric capacity by metal connecting line hole 106.So just, the MIM electric capacity of ground floor and metal interconnected making thereof have been finished.
As shown in figure 11, utilize PECVD (plasma-reinforced chemical vapor deposition) technology to cover deposition on the surface of first metal interconnecting layer and form separator 109, material is a kind of or its combination in silica, tetraethoxysilane, silicon nitride, the silicon oxynitride.Thickness is selected also to determine according to the interfloor height of device.
As shown in figure 12, order forms bottom crown metal level 201, dielectric layer 202, top crown metal level 203 in the presumptive area on the surface of separator 109.
Identical with ground floor MIM electric capacity, bottom crown metal level 201 and top crown metal level 203 can utilize sputter (sputtering) technology to form, and material can be copper, aluminium or albronze, and thickness range is
Dielectric layer 202 can utilize physical vapor deposition technologies such as (PVD) to form, and material can be silicon nitride or silicon oxynitride, and thickness range is
Then as shown in figure 13, etch away the subregion of top crown metal level 203 and dielectric layer 202, expose bottom crown metal level 201.So just, on separator 109, formed second layer MIM electric capacity.
As shown in figure 14, utilize pecvd process to cover deposition on the surface of second layer MIM electric capacity and form second passivation layer 204, its material is a kind of or its combination in silica, tetraethoxysilane, silicon nitride, the silicon oxynitride.Thickness is selected to determine according to the interfloor height of device.
As shown in figure 15, on second passivation layer 204, the zone of the corresponding second layer MIM electric capacity and first metal interconnecting layer, utilize mask, exposure, etching to form four perforation, until exposing top crown interconnection layer 107, top crown metal level 203, bottom crown metal level 201 and bottom crown interconnection layer 108 respectively.With top crown interconnection layer 107, top crown metal level 203, bottom crown metal level 201 and bottom crown interconnection layer 108 is metal seed layer, electroplates growth copper, aluminium or aluminium copper respectively in four perforation, forms four metal connecting line holes.Upper surface at second passivation layer 204 carries out chemistry or mechanical polishing then, removes unnecessary metal.
As shown in figure 16, on the surface of second passivation layer 204, deposit a layer thickness and be
Second metal interconnecting layer, material is chosen as copper, aluminium or albronze; Etching second metal interconnecting layer forms the second top crown interconnection layer 207 and the second bottom crown interconnection layer 208.
The described second top crown interconnection layer 207 is connected with the top crown metal level 203 of second layer MIM electric capacity and the top crown interconnection layer 107 of first metal interconnecting layer respectively by metal connecting line hole 205, metal connecting line hole 215; The described second bottom crown interconnection layer 208 is connected with the bottom crown metal level 201 of second layer MIM electric capacity and the bottom crown interconnection layer 108 of first metal interconnecting layer respectively by metal connecting line hole 206, metal connecting line hole 216.So just, the MIM electric capacity of the second layer and metal interconnected making thereof have been finished.
In the above-described embodiments, the etching of each metal level, passivation layer and dielectric layer is preferably plasma etching, the etchant gas that feeds in reative cell comprises the mist of SF6, CHF3, CF4, chlorine CL2, oxygen O2, nitrogen N 2, helium He and other inert gases such as argon Ar, neon Ne, flow 100sccm-400sccm, underlayer temperature is controlled between 20 ℃-90 ℃, chamber pressure is 4mTorr-20mTorr, and plasma source RF power output is 1500w-2000w.
In structure as shown in figure 16, visible ground floor MIM electric capacity and second layer MIM electric capacity are in parallel by metal interconnecting layer, and lamination has formed a stack architecture.This embodiment only provides the metal-insulator-metal type capacitance structure that comprises two-layer MIM electric capacity to make flow process, make more MIM electric capacity if desired, only need on above architecture basics, to form again a separator, the making step that repeats the above-mentioned second layer MIM electric capacity and second metal interconnecting layer gets final product, this is a process that repeats and need not creative work, repeats no more.
In addition, because in actual applications, may not necessarily there be enough pantostrat spaces to offer the making of MIM electric capacity, sometimes also need to assign into other devices, so stacking-type metal-insulator-metal type capacitance structure of the present invention, its adjacent MIM electric capacity can also interlayer, stride layer realizes, only needs by metal interconnecting layer and metal connecting line hole etc. upper and lower separately pole plate is electrically connected respectively, and the parallel connection of formation MIM electric capacity gets final product.
According to above-mentioned manufacture method, resultant a kind of metal-insulator-metal type capacitance structure comprises:
Semiconductor substrate;
The MIM electric capacity that on Semiconductor substrate, successively forms;
The metal interconnecting layer that between adjacent two layers MIM electric capacity, forms;
Wherein, two-layer at least MIM electric capacity is by the metal interconnecting layer parallel connection.
Described metal interconnecting layer comprises top crown interconnection layer and bottom crown interconnection layer again, and each top crown interconnection layer connects by the metal connecting line hole, and each bottom crown interconnection layer also connects by the metal connecting line hole.
Described MIM electric capacity comprises top crown metal level, bottom crown metal level and is positioned between the two dielectric layer, wherein, the top crown metal level is connected with the top crown interconnection layer by the metal connecting line hole, and the bottom crown metal level is connected with the bottom crown interconnection layer by the metal connecting line hole.
Fill out between described MIM electric capacity and the adjacent metal interconnects layer and be covered with passivation layer.
Also be provided with separator between the adjacent two layers MIM electric capacity.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (12)
1. a metal-insulator-metal type capacitance structure is characterized in that, comprising:
Semiconductor substrate;
The metal-insulator-metal capacitor that on Semiconductor substrate, successively forms;
The metal interconnecting layer that between the adjacent two layers metal-insulator-metal capacitor, forms;
Wherein, two-layer at least metal-insulator-metal capacitor is by the metal interconnecting layer parallel connection.
2. a kind of metal-insulator-metal type capacitance structure as claimed in claim 1, it is characterized in that, described metal interconnecting layer comprises top crown interconnection layer and bottom crown interconnection layer, and each top crown interconnection layer connects by the metal connecting line hole, and each bottom crown interconnection layer connects by the metal connecting line hole.
3. a kind of metal-insulator-metal type capacitance structure as claimed in claim 2 is characterized in that, described metal interconnecting layer is copper, aluminium or albronze.
4. as a kind of metal-insulator-metal type capacitance structure under the claim 2, it is characterized in that described metal-insulator-metal capacitor comprises top crown metal level, bottom crown metal level and is positioned between the two dielectric layer; Wherein, the top crown metal level is connected with the top crown interconnection layer by the metal connecting line hole, and the bottom crown metal level is connected with the bottom crown interconnection layer by the metal connecting line hole.
5. a kind of metal-insulator-metal type capacitance structure as claimed in claim 1 is characterized in that, fills out between described metal-insulator-metal capacitor and the metal interconnecting layer and is covered with passivation layer.
6. a kind of metal-insulator-metal type capacitance structure as claimed in claim 5 is characterized in that, described passivation layer is silica, silicon nitride, silicon oxynitride is a kind of or combination.
7. a kind of metal-insulator-metal type capacitance structure as claimed in claim 1 is characterized in that, also is provided with separator between the described adjacent two layers metal-insulator-metal capacitor.
8. a metal-insulator-metal type capacitance structure manufacture method is characterized in that, at the metal interconnecting layer that successively forms on the Semiconductor substrate between metal-insulator-metal capacitor and the adjacent layer metal-insulator-metal capacitor; Wherein two-layer at least metal-insulator-metal capacitor is by the metal interconnecting layer parallel connection.
9. a metal-insulator-metal type capacitance structure manufacture method is characterized in that concrete steps comprise: form the ground floor metal-insulator-metal capacitor on semi-conductive substrate;
Form first passivation layer on ground floor metal-insulator-metal capacitor surface, and etching forms the metal connecting line hole;
Form first metal interconnecting layer on the surface of first passivation layer;
Etching first metal interconnecting layer forms the first top crown interconnection layer and the first bottom crown interconnection layer;
Surface at first metal interconnecting layer forms separator;
On separator, form second layer metal-insulator-metal capacitance;
Form second passivation layer on second layer metal-insulator-metal capacitance surface, and etching formation metal connecting line hole;
Form second metal interconnecting layer in second passivation layer surface;
Etching second metal interconnecting layer forms the second top crown interconnection layer and the second bottom crown interconnection layer;
The described first top crown interconnection layer is connected with the second top crown interconnection layer by the metal connecting line hole, and the first bottom crown interconnection layer is connected with the second bottom crown interconnection layer by the metal connecting line hole.
10. metal-insulator-metal type capacitance structure manufacture method as claimed in claim 9 is characterized in that,
Described formation metal-insulator-metal capacitor concrete steps comprise:
Order forms bottom crown metal level, dielectric layer, top crown metal level;
Etched portions top crown metal level and dielectric layer expose the bottom crown metal level.
11. a kind of metal-insulator-metal type capacitance structure manufacture method as claimed in claim 10, it is characterized in that, the top crown metal level of described ground floor metal-insulator-metal capacitor is connected with the first top crown interconnection layer by the metal connecting line hole, and the bottom crown metal level is connected with the first bottom crown interconnection layer by the metal connecting line hole; The top crown metal level of described second layer metal-insulator-metal capacitance is connected with the second top crown interconnection layer by the metal connecting line hole, and the bottom crown metal level is connected with the second bottom crown interconnection layer by the metal connecting line hole.
12. metal-insulator-metal type capacitance structure manufacture method as claimed in claim 11, it is characterized in that, repeat the making step of the described second layer metal-insulator-metal capacitance and second metal interconnecting layer, form the metal-insulator-metal type capacitance structure that comprises two above metal-insulator-metal capacitors.
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| CN103367329A (en) * | 2013-07-23 | 2013-10-23 | 上海华力微电子有限公司 | The semiconductor structure that is used for test MIM electric capacity |
| CN103378094A (en) * | 2012-04-27 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Capacitor for interposers and methods of manufacture thereof |
| CN103454018A (en) * | 2012-05-31 | 2013-12-18 | 上海丽恒光微电子科技有限公司 | Pressure sensor, oscillator, ultrasonic sensor and measuring method |
| CN104465629A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Passive device structure and forming method thereof |
| CN105719948A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Capacitor structure and forming method therefor |
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| CN109979915A (en) * | 2019-03-29 | 2019-07-05 | 上海华虹宏力半导体制造有限公司 | A kind of mim capacitor structure and preparation method thereof |
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| CN103378094A (en) * | 2012-04-27 | 2013-10-30 | 台湾积体电路制造股份有限公司 | Capacitor for interposers and methods of manufacture thereof |
| CN103454018A (en) * | 2012-05-31 | 2013-12-18 | 上海丽恒光微电子科技有限公司 | Pressure sensor, oscillator, ultrasonic sensor and measuring method |
| CN103454018B (en) * | 2012-05-31 | 2015-09-09 | 上海丽恒光微电子科技有限公司 | Pressure transducer, oscillator, ultrasonic sensor and measuring method |
| CN103367329B (en) * | 2013-07-23 | 2016-03-30 | 上海华力微电子有限公司 | For testing the semiconductor structure of MIM capacitor |
| CN103367329A (en) * | 2013-07-23 | 2013-10-23 | 上海华力微电子有限公司 | The semiconductor structure that is used for test MIM electric capacity |
| CN104465629B (en) * | 2013-09-23 | 2017-06-09 | 中芯国际集成电路制造(上海)有限公司 | Passive device structure and forming method thereof |
| CN104465629A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Passive device structure and forming method thereof |
| CN105719948A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Capacitor structure and forming method therefor |
| CN105719948B (en) * | 2014-12-04 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | Capacitance structure and forming method thereof |
| WO2020098581A1 (en) * | 2018-11-16 | 2020-05-22 | 无锡华润上华科技有限公司 | Mim capacitor and manufacturing method therefor |
| US11476324B2 (en) | 2018-11-16 | 2022-10-18 | Csmc Technologies Fab2 Co., Ltd. | MIM capacitor and manufacturing method therefor |
| CN109911840A (en) * | 2019-02-28 | 2019-06-21 | 上海集成电路研发中心有限公司 | A kind of MEMS infrared detector structure |
| CN109979915A (en) * | 2019-03-29 | 2019-07-05 | 上海华虹宏力半导体制造有限公司 | A kind of mim capacitor structure and preparation method thereof |
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| CN101789429B (en) | 2011-12-07 |
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