CN101777542A - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN101777542A CN101777542A CN 200910003190 CN200910003190A CN101777542A CN 101777542 A CN101777542 A CN 101777542A CN 200910003190 CN200910003190 CN 200910003190 CN 200910003190 A CN200910003190 A CN 200910003190A CN 101777542 A CN101777542 A CN 101777542A
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- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000004806 packaging method and process Methods 0.000 title abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 69
- 229910052751 metal Inorganic materials 0.000 claims abstract description 69
- 239000000463 material Substances 0.000 claims abstract description 48
- 239000000084 colloidal system Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 65
- 238000005538 encapsulation Methods 0.000 claims description 35
- 238000010276 construction Methods 0.000 claims description 33
- 238000012856 packing Methods 0.000 claims description 18
- 238000000059 patterning Methods 0.000 claims description 7
- 238000007641 inkjet printing Methods 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 6
- 238000004026 adhesive bonding Methods 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract 4
- 230000000694 effects Effects 0.000 description 6
- 238000003466 welding Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000026280 response to electrical stimulus Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a chip packaging structure and a packaging method, wherein the chip packaging structure comprises a flexible substrate, a chip, a second metal layer, a conducting connection member and a packaging colloid. The flexible substrate is provided with an insulated base material layer and a first metal layer, the first metal layer is formed on a first surface of the insulated base material layer and comprises a plurality of first leads and a radiating pattern. The insulated base material layer defines a chip covering area and forms openings in the chip covering area, the radiating pattern is positioned in the chip covering area and at least covers partial openings. The chip is arranged on the flexible substrate and is provided with a plurality of first projections which are electrically connected with the first leads respectively. The second metal layer is arranged on a second face of the insulated base material layer and is corresponding to a part of the first leads. The conducting connection member is connected with the radiating pattern and the second metal layer through the openings; and the packaging colloid is formed between the flexible substrate and the chip.
Description
Technical field
The invention relates to a kind of chip encapsulation construction, and especially, the invention relates to a kind of chip encapsulation construction with heat radiation and capacitor design.
Background technology
Flourish along with semiconductor technology and material science, integrated circuit becomes the arbitrarily IC module of bending with the flexible circuit board integration and making, and general LCD (Liquid Crystal Display LCD) needs several drive IC to control each pixel in the display.At present on the LCD panel according to the juncture of drive IC and different being divided into of use mantle winding: chip is attached to glass plate (Chip on Glass, COG), winding carrying encapsulation (Tape Carrier Package, TCP) and membrane of flip chip encapsulation (Chip on Film COF) waits three kinds of packaged types.Stressing compact and in order to satisfy the electrical demand that constantly promotes, in response to electricity connection end count out (pincount) constantly increase and the trend of fine pitchization (fine pitch), the membrane of flip chip encapsulation has become the generally mode of use.
See also Fig. 1, Fig. 1 is the schematic diagram that illustrates the thin-film flip-chip packaging construction 1 of prior art.As shown in Figure 1, general COF packaging structure 1, a plurality of metal pins 12 that its flexible base plate 10 comprises insulated base material layer 11 and is attached at, 18 local coverings on the metal pins 12 of welding resisting layer so that protection and insulating effect to be provided.Chip 14 electrically connects by the metal pins 12 of projection 140 with flexible base plate 10, then inserts packing colloid 16 between chip 14 and the flexible base plate 10 and pollutes to protect electrical contact and to prevent.
Yet, as mentioned above, stressing under the compact trend, the more and more little and integrated circuit of chip size is healed and is become intensive, and its task performance is multiple grows up along with the reduction of integrated circuit size, simultaneously, its heat generation density also increases thereupon, and centralized heat energy is in little space.Too high heat density will cause function, efficient and the useful life of chip significantly to be reduced.Therefore how effectively loss heat, and can make the chip normal operation, be the problem that the current chip encapsulation must be considered.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of chip encapsulation construction with heat radiation and capacitor design.The radiating effect and the energy additional capacitor that can significantly improve chip according to design of the present invention feed back, and promote the driving usefulness of this chip by this.
A kind of chip encapsulation construction is provided according to an aspect of the present invention, comprises flexible base plate, chip, second metal level, conducting connection member and packing colloid.Wherein flexible base plate has insulated base material layer and the first metal layer, and the first metal layer is to be formed on first of insulated base material layer, and the first metal layer comprises many first lead-in wires and a radiating pattern.Insulated base material layer is limited with chip covering, and forms perforate in chip covering.Radiating pattern is to be positioned at chip covering, and the perforate of cover part at least.Chip is arranged on the flexible base plate, and has a plurality of first projections.These first projections electrically connect with first lead-in wire respectively.Second metal level is arranged at insulated base material layer with respect on first second, and, but first lead-in wire of the position counterpart of second metal level.Conducting connection member sees through perforate and connects the radiating pattern and second metal level.Packing colloid is formed between flexible base plate and the chip.In this specific embodiment, the heat energy that chip the time is produced in running can see through that radiating pattern and conducting connection member conduct to second metal level and loss is gone out.
Provide a kind of method for packing with packaged chip according to a further aspect of the invention, this method for packing comprises the following step: at first, on first of insulated base material layer, the first metal layer is set, and limit chip covering thereon, and the patterning the first metal layer makes radiating pattern be positioned at chip covering to form a plurality of first lead-in wire and radiating pattern; Then, with respect on first one second second metal level is set in insulated base material layer; Then, chip is set on first of insulated base material layer, and makes a plurality of first projections of chip electrically connect first lead-in wire respectively and make at least one second projection of chip connect radiating pattern; Then, form packing colloid between insulated base material layer and the chip; Subsequently, insulated base material layer forms perforate with respect to the radiating pattern place, causes the radiating pattern perforate of cover part at least; Then, form conducting connection member, make it see through perforate and connect the radiating pattern and second metal level; At last, be provided with protective layer in perforate to cover radiating pattern and conducting connection member.
Description of drawings
Can be further understood by of the detailed description of following conjunction with figs. about the advantages and spirit of the present invention preferred embodiment of the present invention, wherein:
Fig. 1 is the schematic diagram that illustrates the thin-film flip-chip packaging construction of prior art.
Fig. 2 illustrates the generalized section according to the chip encapsulation construction of a specific embodiment of the present invention.
Fig. 3 A is the vertical view that illustrates according to the chip encapsulation construction of a specific embodiment of the present invention.
Fig. 3 B is the upward view that illustrates the chip encapsulation construction of Fig. 3 A.
Fig. 4 is the flow chart of steps that illustrates according to the chip packaging method of a specific embodiment of the present invention.
Fig. 5 A～Fig. 5 H is the generalized section of chip encapsulation construction that illustrates each step of corresponding diagram 4.
Embodiment
See also Fig. 2, Fig. 2 illustrates the generalized section according to the chip encapsulation construction 3 of a specific embodiment of the present invention.As shown in Figure 2, chip encapsulation construction 3 comprises flexible base plate 30, chip 34, second metal level 36, conducting connection member 38 and packing colloid 39.
In this specific embodiment, flexible base plate 30 has insulated base material layer 31 and the first metal layer 32, and wherein, the first metal layer 32 is formed on first 310 of insulated base material layer 31, and comprises many first lead-in wire 322 and one radiating pattern 320; Insulated base material layer 31 is limited with a chip covering and engages thereon for chip 34, and, insulated base material layer 31 can be in chip covering with, form perforate 314 but be not subject to laser processing mode, radiating pattern 320 is positioned at the also perforate 314 of cover part at least of chip covering.Chip 34 is arranged on this flexible base plate 30 and is covered in the chip covering of insulated base material layer 31.In addition, chip 34 can comprise a plurality of first projections 340 and at least one second projection 342, and wherein first projection 340 can electrically connect with first lead-in wire 322 respectively, and this second projection 342 can be connected with this radiating pattern 320.
In this specific embodiment, second metal level 36 be arranged at insulated base material layer 31 with respect on this first 310 one second 312, but and first lead-in wire 322 of the position counterpart of second metal level 36.Conducting connection member 38 can see through perforate 314 and connect the radiating pattern 320 and second metal level 36.Packing colloid 39 is formed between flexible base plate 30 and the chip 34, unit such as 322 contact and the radiating pattern 320 of going between in order to functional areas, the chip 34 and first of fixing and protection chip 34.In addition, welding resisting layer 37 is formed at the top and local first lead-in wire 322 that covers of the first metal layer 32, so that protection and insulation effect to be provided.
In practice, the material of the first metal layer 32 and second metal level 36 can comprise, but is not subject to copper.And the material of conducting connection member 38 can comprise, but be not subject to silver, material such as tin or carbon paste.In addition, in practice conducting connection member 38 can, but be not subject to printing or ink-jetting style forms.
In this specific embodiment; this chip encapsulation construction 3 can further comprise protective layer 35; the material of protective layer 35 can comprise in practice; but be not subject to epoxy resin and anti-wlding, and can gluing, printing or ink-jetting style be arranged at and cover radiating pattern 320 and conducting connection member 38 in the perforate 314 so that protective effect to be provided.
In the chip encapsulation construction 3 of above-mentioned specific embodiment, conducting connection member 38 connects the radiating pattern 320 and second metal level 36.In practice, the heat that chip 34 is produced when running can see through radiating pattern 320 and conducting connection member 38 conducts to second metal level 36, uses to help chip 34 heat radiations.
In addition, in this specific embodiment, be isolated between the first metal layer 32 and this second metal level 36, so it is equivalent to capacity plate antenna structure with insulated base material layer 31.In practice, when chip encapsulation construction 3 connects external circuits and when operating, electric current transmitted/signal and produce capacity effect and assemble electronics in second metal level, 36 inductions, first lead-in wire 322.When decommission and first lead-in wire 322 in no current/signal when passing through, the electron production feedback current of being assembled in second metal level 36 is back to circuit in the chip 34 through conducting connection member 38, radiating pattern 320 and second projection 342, quickens the liquid crystal resume speed by this to promote the driving usefulness of chip 34.
In another specific embodiment, radiating pattern 320 can comprise a plurality of blocks, and these blocks can see through second projection 342 respectively and electrically connect with chip 34.In addition, second metal level 36 also can comprise many second lead-in wires, and 38 of conducting connection member comprise a plurality of each block and these second lead-in wires that circuit electrically connects radiating pattern 320 respectively that connect.
In this specific embodiment, because above-mentioned radiating pattern 320 is distinguished a plurality of blocks and is electrically connected with different second projections 342 of chip 34, and second metal level 36 is also distinguished a plurality of second lead-in wires and is connected each block that circuit electrically connects radiating pattern 320 by difference respectively, therefore, the chip encapsulation construction 3 of this specific embodiment also can see through radiating pattern 320, second projection 342, conducting connection member 38 and second metal level 36 is linked up with external electronic, and then increases electricity connection end count out (I/O number).
See also Fig. 3 A, Fig. 3 A is the vertical view that illustrates according to the chip encapsulation construction 5 of a specific embodiment of the present invention.In this specific embodiment, chip encapsulation construction 5 comprises flexible base plate 50, and flexible base plate 50 has insulated base material layer 51 and the first metal layer.The first metal layer is formed on the insulated base material layer 51, and the first metal layer comprises many first lead-in wires 502 and radiating pattern 504.Cover welding resisting layer 52 on the flexible base plate 50, and comprise a welding resisting layer opening 520 on the welding resisting layer 52 and be arranged at wherein for chip (in Fig. 3, illustrating chip range) with dotted line.One end of radiating pattern 504 and each first lead-in wire 502 is arranged in welding resisting layer opening 520.In addition, comprise perforate 500 on the insulated base material layer 51, and radiating pattern 504 cover part perforate 500 at least.Chip encapsulation construction 5 comprises chip in addition, and it has a plurality of first projections and at least one second projection, and each first projection can electrically connect with first lead-in wire 502 respectively, and second projection can be connected with radiating pattern 504.In this specific embodiment, radiating pattern 504 is to comprise a plurality of blocks.The quantity and the shape that note that radiating pattern 504 in practice are to decide according to user or designer's demand, and radiating pattern 504 also can see through second projection and chip electrically connects.
See also Fig. 3 B, Fig. 3 B is the vertical view that illustrates the chip encapsulation construction 5 of Fig. 3 A.Shown in Fig. 3 B, second lead-in wire 53 is set on the bottom surface of insulated base material layer 51 (that is, with the above-mentioned surperficial facing surfaces that is provided with the first metal layer), and second lead-in wire 53 can conducting connection member 54 be connected with 504 of radiating pattern.In this specific embodiment, when chip encapsulation construction 5 carries chips and chip operated, the heat that chip produced can see through radiating pattern 504 conduct to second lead-in wire 53 with conducting connection member 54.Note that in practice second lead-in wire 53 also can have other shape and not be subject to this specific embodiment, for example, large-area metal level.
See also Fig. 4 and Fig. 5 A～Fig. 5 H, Fig. 4 is the flow chart of steps that illustrates according to the chip packaging method of a specific embodiment of the present invention, and Fig. 5 A～Fig. 5 H is the generalized section of chip encapsulation construction that illustrates each step of corresponding diagram 4.As shown in Figure 4, chip packaging method of the present invention comprises step S71 to S78.At first, execution in step S71 is provided with the first metal layer 32 on first 310 of insulated base material layer 31, form flexible base plate 30, and limit a chip covering 300 thereon, shown in Fig. 5 A.Then, execution in step S72, patterning the first metal layer 32 makes this radiating pattern 320 be positioned at chip covering 300, shown in Fig. 5 B to form many first lead-in wires 322 and radiating pattern 320.Afterwards, execution in step S73 is provided with second metal level 36 in insulated base material layer 31 with respect on first 310 second 312, shown in Fig. 5 C.
Then, see also Fig. 5 D, execution in step S74 is provided with chip 34 on first 310 chip covering 300, makes a plurality of first projections 340 of chip 34 electrically connect first lead-in wire 322 and at least one second projection, 342 connection radiating pattern 320 respectively.Note that because among Fig. 5 D to Fig. 5 H, chip 34 has been covered on the chip covering 300, thus for drawing neatly for the purpose of, chip covering 300 is not illustrated among Fig. 5 D to Fig. 5 H.Thereafter, execution in step S75 forms packing colloid 39, shown in Fig. 5 E between insulated base material layer 31 and chip 34.
See also Fig. 5 F, execution in step S76, this insulated base material layer 31 is sentenced laser processing mode with respect to this radiating pattern 320 and is formed a perforate 314, makes this perforate 314 of cover part at least of this radiating pattern 320.Subsequently, execution in step S77, by, but be not subject to printing or ink-jetting style forms a conducting connection member 38, make it see through this perforate 314 and connect this radiating pattern 320 and this second metal level 36, shown in Fig. 5 G.At last, execution in step S78, by, protective layer 35 is not set in perforate 314 but be not subject to gluing, printing or ink-jetting style, in order to cover and protection radiating pattern 320 and conducting connection member 38, shown in Fig. 5 H.
The formed chip encapsulation construction 3 of this specific embodiment (shown in Fig. 5 H), the heat that its chip 34 is produced when operation can see through radiating pattern 320 and conducting connection member 38 conducts to second metal level 36, uses to help chip 34 heat radiations.
In addition, in this specific embodiment, be isolated between the first metal layer 32 and this second metal level 36, so it is equivalent to capacity plate antenna structure with insulated base material layer 31.In practice, when chip encapsulation construction 3 connects external circuits and when operating, electric current transmitted/signal and produce capacity effect and assemble electronics in second metal level, 36 inductions, first lead-in wire 322.When decommission and first lead-in wire 322 in no current/signal when passing through, the electron production feedback current of being assembled in second metal level 36 is back to circuit in the chip 34 through conducting connection member 38, radiating pattern 320 and second projection 342, quickens the liquid crystal resume speed by this to promote the driving usefulness of chip 34.
In another specific embodiment, the said chip method for packing can further comprise the following step: at first, when execution in step S72, patterning radiating pattern 320 causes these blocks can see through a plurality of second projections 342 respectively and electrically connects with chip 34 to form a plurality of blocks simultaneously.Then, in execution in step S73 the time, patterning second metal level 36 is to form many second lead-in wires.At last, when execution in step S77, form a plurality of circuits that connect in conducting connection member 38 and electrically connect the block of radiating pattern 320 and second lead-in wire of second metal level 36 respectively.
Because the one patterned of radiating pattern 320, second metal level 36, and by difference connect circuit electrically connect respectively radiating pattern 320 each block and second metal level 36 each second the lead-in wire, therefore chip encapsulation construction 3 can see through radiating pattern 320, second projection 342, conducting connection member 38 and second metal level 36 and links up with external electronic, and then increase electricity connection end count out (I/O number).
In sum, the invention provides a kind of chip encapsulation construction, can significantly improve the radiating effect of chip according to this design with heat dissipation design.The metal level that adds among the present invention in addition, and former be used for and metal level that chip connects between isolated with insulated base material layer, this is equivalent to the parallel plate capacitor structure, therefore has a capacitance to exist when chip drives, additional capacitors is fed back by this, can promote the driving usefulness of chip.
By the above detailed description of preferred embodiments, be to wish to know more to describe feature of the present invention and spirit, and be not to come category of the present invention is limited with above-mentioned disclosed preferred embodiment.On the contrary, its objective is that hope can contain in the category of claim of being arranged in of various changes and tool equality institute of the present invention desire application.
Claims (10)
1. chip encapsulation construction comprises:
One flexible base plate, have an insulated base material layer and a first metal layer, this the first metal layer is formed at one first of this insulated base material layer and goes up and comprise many first lead-in wires and a radiating pattern, this insulated base material layer is limited with a chip covering and forms a perforate in this chip covering, and this radiating pattern is positioned at this chip covering and this perforate of cover part at least;
One chip is arranged on this flexible base plate and has a plurality of first projections, and described first projection electrically connects with described first lead-in wire respectively;
One second metal level is arranged at this insulated base material layer with respect on this first one second, and described first lead-in wire of counterpart;
One conducting connection member sees through this perforate and connects this radiating pattern and this second metal level; And
One packing colloid is formed between this flexible base plate and this chip.
2. chip encapsulation construction according to claim 1 is characterized in that, this chip also comprises at least one second projection, and this second projection is connected with this radiating pattern.
3. chip encapsulation construction according to claim 2, it is characterized in that, this radiating pattern comprises a plurality of blocks, described block sees through described second projection and this chip respectively and electrically connects, this second metal level comprises many second lead-in wires, and this conducting connection member comprises a plurality of circuits that connect and electrically connects described block and described second lead-in wire respectively.
4. chip encapsulation construction according to claim 1 is characterized in that, this perforate is to be formed at this insulated base material layer with laser processing mode.
5. chip encapsulation construction according to claim 1 is characterized in that, the material of this conducting connection member comprise be selected from by silver, tin and carbon paste formed in the group one of at least.
6. chip encapsulation construction according to claim 1 is characterized in that, also comprises a protective layer and is arranged in this perforate with gluing, printing or ink-jetting style, to cover this radiating pattern and this conducting connection member.
7. method for packing, in order to encapsulate a chip, this method for packing comprises the following step:
On one first an of insulated base material layer, a first metal layer is set, and limits a chip covering;
This first metal layer of patterning makes this radiating pattern be positioned at this chip covering to form many first lead-in wires and a radiating pattern;
One second metal level is set in this insulated base material layer on respect to this first one second;
This chip is set on this first of this insulated base material layer, and makes a plurality of first projections of this chip electrically connect described first lead-in wire respectively and at least one second projection connects this radiating pattern;
Between this insulated base material layer and this chip, form a packing colloid;
This insulated base material layer forms a perforate with respect to this radiating pattern place, makes this perforate of cover part at least of this radiating pattern;
Form a conducting connection member, make it see through this perforate and connect this radiating pattern and this second metal level; And
Be provided with a protective layer in this perforate to cover this radiating pattern and this conducting connection member.
8. method for packing according to claim 7 is characterized in that, this perforate is to be formed at this insulated base material layer with laser processing mode.
9. method for packing according to claim 7 is characterized in that, this conducting connection member is to form with printing or ink-jetting style.
10. method for packing according to claim 7 is characterized in that, also comprises the following step:
This radiating pattern of patterning causes described block to see through described second projection and this chip respectively and electrically connects to form a plurality of blocks;
This second metal level of patterning is to form many second lead-in wires; And
Form a plurality of circuits that connect in this conducting connection member, the described circuit that connects electrically connects described block and described second lead-in wire respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910003190 CN101777542B (en) | 2009-01-14 | 2009-01-14 | Chip packaging structure and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910003190 CN101777542B (en) | 2009-01-14 | 2009-01-14 | Chip packaging structure and packaging method |
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| Publication Number | Publication Date |
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| CN101777542A true CN101777542A (en) | 2010-07-14 |
| CN101777542B CN101777542B (en) | 2011-08-17 |
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| CN 200910003190 Expired - Fee Related CN101777542B (en) | 2009-01-14 | 2009-01-14 | Chip packaging structure and packaging method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738319A (en) * | 2011-04-08 | 2012-10-17 | 欣兴电子股份有限公司 | Manufacturing method of heat dissipation substrate |
| CN103855040A (en) * | 2012-12-04 | 2014-06-11 | 讯忆科技股份有限公司 | Method for forming guide circuit of semiconductor chip package |
| CN103904552A (en) * | 2012-12-26 | 2014-07-02 | 鸿富锦精密工业（深圳）有限公司 | Laser chip packaging structure for projection |
| CN104465604A (en) * | 2013-09-13 | 2015-03-25 | 三星显示有限公司 | Chip-on-film (COF) package, COF package array including the same, and display device including the same |
| CN106158763A (en) * | 2015-05-13 | 2016-11-23 | 南茂科技股份有限公司 | Thin film package substrate, thin film flip chip package body and thin film flip chip packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI282159B (en) * | 2005-12-20 | 2007-06-01 | Internat Semiconductor Technol | Thermally enhanced thin flip-chip package |
| TW200816422A (en) * | 2006-09-19 | 2008-04-01 | Int Semiconductor Tech Ltd | Heating dissipating chip on film package |
| CN100585890C (en) * | 2006-11-06 | 2010-01-27 | 南茂科技股份有限公司 | Luminous chip packaging body and manufacturing method therefor |
| US20080258293A1 (en) * | 2007-04-17 | 2008-10-23 | Advanced Chip Engineering Technology Inc. | Semiconductor device package to improve functions of heat sink and ground shield |
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2009
- 2009-01-14 CN CN 200910003190 patent/CN101777542B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738319A (en) * | 2011-04-08 | 2012-10-17 | 欣兴电子股份有限公司 | Manufacturing method of heat dissipation substrate |
| CN102738319B (en) * | 2011-04-08 | 2015-02-04 | 欣兴电子股份有限公司 | Manufacturing method of heat dissipation substrate |
| CN103855040A (en) * | 2012-12-04 | 2014-06-11 | 讯忆科技股份有限公司 | Method for forming guide circuit of semiconductor chip package |
| CN103855040B (en) * | 2012-12-04 | 2016-12-21 | 讯忆科技股份有限公司 | The forming method connecting circuit of semiconductor die package |
| CN103904552A (en) * | 2012-12-26 | 2014-07-02 | 鸿富锦精密工业（深圳）有限公司 | Laser chip packaging structure for projection |
| CN104465604A (en) * | 2013-09-13 | 2015-03-25 | 三星显示有限公司 | Chip-on-film (COF) package, COF package array including the same, and display device including the same |
| CN104465604B (en) * | 2013-09-13 | 2018-11-13 | 三星显示有限公司 | Chip on film encapsulates and includes its chip on film array of packages and display device |
| CN106158763A (en) * | 2015-05-13 | 2016-11-23 | 南茂科技股份有限公司 | Thin film package substrate, thin film flip chip package body and thin film flip chip packaging method |
| CN106158763B (en) * | 2015-05-13 | 2018-09-07 | 南茂科技股份有限公司 | Thin film package substrate, thin film flip chip package body and thin film flip chip packaging method |
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| Publication number | Publication date |
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| CN101777542B (en) | 2011-08-17 |
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