CN101777320A - Ghost eliminating circuit, display and electronic device - Google Patents
Ghost eliminating circuit, display and electronic device Download PDFInfo
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Abstract
The invention discloses a ghost eliminating circuit, a display and an electronic device. The ghost eliminating circuit comprises a first switch transistor and a diode, wherein the first end of the first switch transistor is electrically coupled to the second driving voltage output end of a power supply unit through a voltage divider, the second end is electrically coupled to reference voltage, the third end is electrically coupled to the logic voltage input end of a grid driving circuit and the first driving voltage output end of the power supply unit, wherein the grid driving circuit comprises an XON function; and the anode of the diode is electrically coupled to the second driving voltage output end, and the cathode of the diode is electrically coupled to the logic voltage input end. When the display is shut down, the ghost eliminating circuit is switched to the mode that the first driving voltage is used for providing the logic voltage for the grid driving circuit so as to prolong the acting time of the XON function, fully release the charge in a film electric crystal and effectively eliminate residual images generated when the display is shut down.
Description
Technical field
The present invention relates in particular to a kind of afterimage eliminate circuit, display and electronic installation of display shutdown mode about a kind of afterimage eliminate circuit.
Background technology
The display panel of traditional LCD comprises gate driver circuit, data drive circuit and pel array.Pel array is arranged by a plurality of dot structures and is formed, and in general, dot structure mainly is made up of membrane transistor, sweep trace, data line, storage capacitors and liquid crystal cells, each membrane transistor comprises grid, drain electrode and source electrode, and the grid of each membrane transistor is connected to sweep trace, drain electrode is connected to data line, and source electrode is connected to an end of storage capacitors.The output terminal of gate driver circuit is coupled to pel array, in order to drive these dot structures, to open or to close a plurality of membrane transistors that are connected with sweep trace.Many data lines of source electrode drive circuit and this are connected, when a plurality of membrane transistors are opened, for it provides the GTG display voltage, so that equal stored video signal in each dot structure.Because LCD when display image, is understood stored charge in the storage capacitors between two relative electrodes (as public electrode and pixel electrode).When the display panel power cutoff of LCD, these stored charges will make corresponding pixel be in different GTGs, thus on display screen more residual images.
In order to address the above problem, be in the prior art using XON function on the drive integrated circult (IC) to open the membrane transistor of all dot structures behind the LCD power-off, so that dot structure carries out rapid discharge.The XON function here is meant, after the XON pin of grid-driving integrated circuit is received the off signal of display panel, grid-driving integrated circuit all is pulled up to high-potential voltage VGH (when the general normal demonstration with the output voltage of all output terminals, usually has only an output terminal output high-potential voltage VGH at a certain time slot, all the other output terminal output LOW voltage VGL, VGL is generally between-10V to 0V, VGH is generally more than 10V), open the grid of membrane transistors all in the display panels, with mandatory electric charge in the dot structure is neutralized apace, discharge, reach the purpose of eliminating ghost.Wherein voltage VGH, VGL are the driving voltages of the power module supply membrane transistor in LCD or the display panels.
See also Fig. 1, Figure 1 shows that the circuit diagram of LCD of the prior art.The driving voltage V3 output terminal of LCD power-supply unit is coupled to the logic voltage Vcc input end of gate driver circuit by first resistance 45, and the input voltage Vxon input end of XON pin is by voltage comparable chip 46 and electric capacity 47 and driving voltage V3 output terminal electric property coupling.Driving voltage V3 output voltage values when the display operate as normal is Vdd.
See also Fig. 2, Figure 2 shows that the driving sequential chart of LCD of the prior art.Before sequential t2, LCD is opened operate as normal, and the general supply of LCD is closed during sequential t2, and driving voltage V3 begins to descend, and the logic voltage Vcc of gate driver circuit also decreases, and high-potential voltage VGH also begins to descend.At this moment, under 46 effects of voltage comparable chip, the input voltage Vxon of XON pin descends rapidly.It is low-voltage that the realization of the XON function of driving I C need be satisfied Vxon, and logic voltage Vcc is high-tension condition.Concrete, as shown in Figure 1, promptly satisfy a certain low voltage threshold for example for being lower than 0.3Vdd (after being sequential t3) as Vxon, and satisfy a certain high voltage threshold for example when being higher than 0.7Vdd (before the sequential t4) at logic voltage Vcc, the XON function of drive IC works, open the grid of membrane transistors all in the display panels, the electric charge in the dot structure is neutralized apace, discharges with mandatory.
Yet, in the prior art, when LCD is shut down, the logic voltage Vcc of gate driver circuit often descends also very fast (in Fig. 1, reduce to 0.7Vdd during sequential t4), thereby the time Δ t that opens of XON function (as the sequential t3 among Fig. 1 to sequential t4) is very short, it is too short that the membrane transistor grid is opened the time, electric charge is not able to do in time fully to neutralize, and just still has ghost and rests on the display panels.
Summary of the invention
Therefore, one of purpose of the present invention is to provide a kind of afterimage eliminate circuit, display and electronic installation, the logic voltage of gate driver circuit can be provided by first driving voltage in display shutdown back, form effective discharge path, elimination remains in the electric charge in the dot structure, effectively eliminates the problem of display afterimage when shutdown.
For reaching above-mentioned purpose, the invention provides a kind of afterimage eliminate circuit, this afterimage eliminate circuit comprises first switching transistor and diode.First switching transistor has first end, second end and the 3rd end, this first end is electrically coupled to the second driving voltage output terminal of power-supply unit by voltage divider, this second end is electrically coupled to reference voltage, the 3rd end is by the logic voltage input end electric property coupling of first resistance and gate driver circuit, and the 3rd end also is electrically coupled to the first driving voltage output terminal of this power-supply unit by second resistance, wherein this gate driver circuit comprises the XON function.The positive pole of this diode is electrically coupled to this second driving voltage output terminal of this power-supply unit, and the negative pole of this diode is electrically coupled to this logic voltage input end of this gate driver circuit.
Further, this afterimage eliminate circuit also comprises mu balanced circuit, and an end of this mu balanced circuit is electrically coupled to this reference voltage, and the other end is electrically coupled to this logic voltage input end of this gate driver circuit.
Further, this mu balanced circuit is a voltage stabilizing diode.
Further, this first switching transistor is a bipolar transistor, and this first end, second end and the 3rd end are respectively base stage, the collector and emitter of this bipolar transistor.
Further, this first switching transistor is a mos field effect transistor, and this first end, second end and the 3rd end are respectively grid, source electrode and the drain electrode of this mos field effect transistor.
Further, this voltage divider comprises the 3rd resistance and the 4th resistance, the two ends of the 3rd resistance are electrically coupled to the second driving voltage output terminal and this first end of this power-supply unit respectively, and the two ends of the 4th resistance are electrically coupled to this reference voltage and this first end respectively.
Further, this reference voltage is a ground voltage.
The present invention also provides a kind of display, and this display comprises pel array and aforesaid afterimage eliminate circuit.Pel array comprises a plurality of dot structures, and each those dot structure comprises at least one active member.Wherein the output terminal of this gate driver circuit is electrically coupled to this pel array.
Further, this display is a LCD.
The present invention also provides a kind of electronic installation, and this electronic installation comprises aforesaid display and user's interface, and user's interface and this display electric property coupling are to control this display.
Compared with prior art, display of the present invention utilizes second driving voltage to provide logic voltage by diode to gate driver circuit before shutdown, then switches to after the shutdown and utilizes first driving voltage to provide logic voltage for gate driver circuit.The time that the logic voltage that promptly utilizes first driving voltage to prolong gate driver circuit works when shutdown, reach and prolong the time that the XON function works, and then prolong discharge time, reach the purpose that discharges electric charge in the membrane transistor fully, effectively eliminate the problem of display afterimage when shutdown.
Can be about the advantages and spirit of the present invention by following detailed Description Of The Invention and appended graphic being further understood.
Description of drawings
Figure 1 shows that the circuit diagram of LCD of the prior art;
Figure 2 shows that the driving sequential chart of LCD of the prior art;
Figure 3 shows that synoptic diagram according to LCD of the present invention;
Figure 4 shows that synoptic diagram according to first embodiment of afterimage eliminate circuit of the present invention;
Figure 5 shows that driving sequential chart according to LCD of the present invention;
Figure 6 shows that synoptic diagram according to second embodiment of afterimage eliminate circuit of the present invention.
Embodiment
The invention provides a kind of electronic installation, electronic installation comprises display 1 and user's interface, and user's interface and display 1 electric property coupling are with control display 1, and wherein display 1 for example is a LCD.See also Fig. 3, Figure 3 shows that synoptic diagram according to LCD of the present invention.LCD 1 comprises pel array, gate driver circuit 2, source electrode drive circuit 3, power-supply unit 4 and afterimage eliminate circuit 10.Power-supply unit 4 provides the logic voltage Vcc of gate driver circuit 2 by afterimage eliminate circuit 10, with 2 runnings of driving grid driving circuit, gate driver circuit 2 is used to scan the display panel of LCD 1, and source electrode drive circuit 3 is used for providing gray scale voltage for display panels when display panels is scanned.
Wherein, pel array is arranged by a plurality of dot structures 5 and is formed, and in general, dot structure 5 is mainly by active member 8, sweep trace 7, data line 6, storage capacitors 9 and liquid crystal cells 19, and active member 8 for example is the membrane transistor that is coupled to sweep trace 7 and data line 6.Each membrane transistor 8 comprises grid, drain electrode and source electrode, and the grid of each membrane transistor 8 is connected to sweep trace 7, drain electrode is connected to data line 6, source electrode is connected to an end of storage capacitors 9, the other end of storage capacitors 9 is coupled to common electric voltage Vcom, and an end of liquid crystal cells 19 is electrically coupled to first end of storage capacitors 9, and the other end is electrically coupled to common electric voltage Vcom.The output terminal of gate driver circuit 2 is coupled to pel array, and in order to drive these dot structures 5, concrete for example gate driver circuit 2 is connected with this multi-strip scanning line 7, to open or to close a plurality of membrane transistors 8 that are connected with sweep trace 7.Source electrode drive circuit 3 is connected with these many data lines 6, when a plurality of membrane transistors 8 are opened, for it provides the GTG display voltage, so that equal stored video signal in each dot structure 5.
On the other hand, because LCD 1 when display image, is understood stored charge in the storage capacitors 9 between two relative electrodes (as public electrode and pixel electrode).When the display panel power cutoff of LCD 1, these stored charges will make corresponding pixel be in different GTGs, thus on display screen more residual images.Gate driver circuit 2 has the XON function among the present invention, the XON function here is meant, after the XON pin of grid-driving integrated circuit 2 is received the off signal of display panel, gate driver circuit 10 all is pulled up to high-potential voltage VGH (when the general normal demonstration with the output voltage of all output terminals, usually has only an output terminal output high-potential voltage VGL at a certain time slot, all the other output terminal output LOW voltage VGL, VGL is generally between-10V to 0V, VGH is generally more than 10V), open the grid of membrane transistors 8 all in the display panel, the electric charge in the dot structure 5 is discharged apace with mandatory.Voltage VGH, VGL are the driving voltages that the power-supply unit 4 in LCD 1 or the display panels is supplied with membrane transistor 8.It is evident that the velocity of discharge is fast more, the ghost on the display panel will be eliminated fast more thoroughly more.Therefore, in the implementation procedure of eliminating ghost, the XON function is very important.Yet when LCD 1 enters shutdown mode, if logic voltage Vcc descends too soon when shutdown, make the XON function time too short, it is too short that the grid of membrane transistor 8 is opened the time, electric charge does not have enough time to neutralize, data-signal is still kept or part maintains in the dot structure 5, thereby produces the ghost problem.
See also Fig. 4, Figure 4 shows that synoptic diagram according to first embodiment of afterimage eliminate circuit of the present invention.The input end electric property coupling power-supply unit 4 of afterimage eliminate circuit 10 of the present invention, the output terminal of afterimage eliminate circuit 10 is electrically coupled to the input end of gate driver circuit 2, and the logic voltage Vcc of gate driver circuit 2 is provided.And afterimage eliminate circuit 10 comprises first switching transistor 15 and diode 16.First switching transistor 15 has first end, second end and the 3rd end, and first end is electrically coupled to the second driving voltage V2 output terminal of power-supply unit 4 by voltage divider 18; Second end is coupled to reference voltage V0, and wherein reference voltage V0 for example is a ground voltage, that is the second end ground connection; The 3rd end is by the logic voltage Vcc input end electric property coupling of first resistance 11 with gate driver circuit 2, and the 3rd end also is electrically coupled to the first driving voltage VGH output terminal of power-supply unit 4 by second resistance 12.The positive pole of diode 16 is electrically coupled to the second driving voltage V2 output terminal of power-supply unit 4, and the negative pole of diode 16 is electrically coupled to the logic voltage Vcc input end of gate driver circuit 2.Wherein, in the present embodiment, first switching transistor 15 for example is bipolar npn type (BJT) transistor, and first end, second end and the 3rd end are respectively base stage, the collector and emitter of bipolar transistor 15.That is base stage is coupled to the second driving voltage V2 output terminal of power-supply unit 4 by voltage divider 18; Collector is coupled to reference voltage V0, and wherein reference voltage V0 for example is a ground voltage, that is grounded collector; Emitter is by the logic voltage Vcc input end electric property coupling of first resistance 11 with gate driver circuit 2, and emitter also is electrically coupled to the first driving voltage VGH output terminal of power-supply unit 4 simultaneously by second resistance 12.
And in the present embodiment, voltage divider 18 comprises the 3rd resistance 13 and the 4th resistance 14, the second driving voltage V2 output terminal of the two ends difference electric property coupling power-supply unit 4 of the 3rd resistance 13 and the base stage of BJT transistor 15, the two ends of the 4th resistance 14 are electrically coupled to the base stage of reference voltage V0 and BJT transistor 15 respectively, same reference voltage V0 for example is a ground voltage, that is an end ground connection of the 4th resistance 14.Wherein, the resistance of first resistance 11 and second resistance 12 approximately is positioned at the scope of 100-500K ohm, the resistance of the 3rd resistance 13 and the 4th resistance 14 approximately is positioned at the scope less than 100K ohm, and the ratio of the 3rd resistance 13 and the 4th resistance 14 is about 2: 1, for example concrete, first resistance 11 and second resistance 12 are 100K ohm, and the 3rd resistance 13 is 2K ohm, and the 4th resistance 14 is 1K ohm.But, decide according to actual conditions not as limit.
In addition, afterimage eliminate circuit 10 also comprises mu balanced circuit 17, and an end of mu balanced circuit 17 is electrically coupled to reference voltage V0 such as ground voltage, and the other end of mu balanced circuit 17 is electrically coupled to the logic voltage Vcc input end of gate driver circuit 2.Mu balanced circuit 17 for example maintains in the preset range in order to the logic voltage Vcc that will import gate driver circuit 2.Wherein in the present embodiment, mu balanced circuit 17 for example is a voltage stabilizing diode.
When LCD 1 operate as normal, the value of the second driving voltage V2 of power-supply unit 4 is the Vdd of noble potential, diode 16 conductings this moment, 15 conductings of BJT transistor, voltage divider 18 is coupled to reference voltage V0, also successively by the emitter and the grounded collector of second resistance 12 and BJT transistor 15, this moment, the second driving voltage V2 provided logic voltage Vcc for gate driver circuit 2 by diode 16 for voltage divider 18 ground connection for example, the first driving voltage VGH output terminal.The shift register of respectively organizing of gate driver circuit 2 is exported the grid impulse signal successively afterwards, to open the membrane transistor 8 that connects on every sweep trace 7 one by one, at this moment, the corresponding data-signal of source electrode drive circuit 3 outputs charges to required pixel current potential with memory capacitance 9 and liquid crystal cells 19 to the membrane transistor 8 of connection on these data lines 6, to show different GTGs.
When LCD 1 shutdown, be that power-supply unit 4 is closed, this moment, the second driving voltage V2 dropped to the critical conduction voltage that is lower than diode 16 fast, and diode 16 opens circuit by forming at this moment, BJT transistor 15 also ends, and forms between its emitter and the collector and opens circuit.And compared to the quick decline of the second driving voltage V2, still can there be a period of time in the first driving voltage VGH in LCD 1 inside.At this moment, switch to and utilize the first driving voltage VGH to provide logic voltage Vcc to gate driver circuit 2 through second resistance 12 and first resistance 11, and then prolong the time of logic voltage Vcc role when shutdown of gate driver circuit 2, reach the purpose that prolongs the time that the XON function works, and then prolong the time that discharges electric charge.
The concrete Fig. 5 that sees also Figure 5 shows that the driving sequential chart according to LCD of the present invention.Before sequential t6, LCD is opened and operate as normal, and the general supply of LCD 1 is closed during sequential t6, and driving voltage V2 begins to descend, and the logic voltage Vcc of gate driver circuit also decreases, and high-potential voltage VGH also begins to descend.At this moment, the input voltage Vxon of XON begins rapid decline.Along with the decline of driving voltage V2, BJT transistor 15 ends, and the first driving voltage VGH provides logic voltage Vcc to gate driver circuit 2, so logic voltage Vcc is through raising once more after the of short duration decline.Because the current potential height of high-potential voltage VGH own, drop to a certain threshold value for example during 0.7Vdd required time longer, thereby make logic voltage Vcc still can remain on above a period of time of 0.7Vdd.Be equal to or less than a certain threshold value for example during 0.3Vdd when Vxon reduces to, promptly during sequential t7, the XON function on the drive IC begins effect, opens the membrane transistor 8 of all dot structures 5, so that dot structure 5 carries out rapid discharge.When sequential t8, logic voltage Vcc also drops to below the 0.7Vdd, and the XON function no longer works, and discharge finishes.Than Δ t discharge time of the prior art, the Δ t ' discharge time of LCD of the present invention (Δ t ' is that sequential t7 is to sequential t8) obviously increases, and helps the release fully of residual charge in the dot structure 5.
See also Fig. 6, Figure 6 shows that synoptic diagram according to second embodiment of afterimage eliminate circuit of the present invention.Afterimage eliminate circuit 10 in afterimage eliminate circuit 30 in the present embodiment and first embodiment similar, difference is, first switching transistor 25 is a n channel metal oxide semiconductor field effect transistor in the present embodiment, and first end, second end and the 3rd end are respectively grid, source electrode and the drain electrode of n channel metal oxide semiconductor field effect transistor 25.Because the mode of action of afterimage eliminate circuit 30 in LCD be consistent with the afterimage eliminate circuit 10 in first embodiment, thus at this at detailed description.
Compared with prior art, display of the present invention utilizes the second driving voltage V2 to provide logic voltage by diode to grid-driving integrated circuit before shutdown, then switch to after the shutdown and utilize the first driving voltage VGH to provide logic voltage, and utilize the stable of mu balanced circuit sustaining voltage simultaneously for grid-driving integrated circuit.The time that the logic voltage that promptly utilizes the first driving voltage VGH voltage to prolong grid-driving integrated circuit works when shutdown, reach and prolong the time that the XON function works, and then prolong discharge time, reach the purpose that discharges electric charge in the membrane transistor fully, effectively eliminate the problem of display afterimage when shutdown.
Those of ordinary skill in the art is to be understood that, though specific embodiments of the invention are illustrated as example with the membrane transistor LCD, be confined to this but have more than, for example, display device can also be applicable to flat panel TV, vehicle-mounted flat-panel monitor, desktop computer display screen, Tablet PC etc.
By the above detailed description of preferred embodiments, be to wish to know more to describe feature of the present invention and spirit, and be not to come protection scope of the present invention is limited with above-mentioned disclosed preferred embodiment.On the contrary, its objective is that hope can contain in the protection domain of claim of being arranged in of various changes and tool equality institute of the present invention desire application.Therefore, the protection domain of the claim that the present invention applied for should be done the broadest explanation according to above-mentioned explanation, contains the arrangement of all possible change and tool equality to cause it.
Claims (10)
1. an afterimage eliminate circuit is characterized in that this afterimage eliminate circuit comprises
First switching transistor, have first end, second end and the 3rd end, this first end is electrically coupled to the second driving voltage output terminal of power-supply unit by voltage divider, this second end is electrically coupled to reference voltage, the 3rd end is by the logic voltage input end electric property coupling of first resistance and gate driver circuit, and the 3rd end also is electrically coupled to the first driving voltage output terminal of this power-supply unit by second resistance, wherein this gate driver circuit comprises the XON function; And
Diode, the positive pole of this diode are electrically coupled to the second driving voltage output terminal of this power-supply unit, and the negative pole of this diode is electrically coupled to the logic voltage input end of this gate driver circuit.
2. afterimage eliminate circuit as claimed in claim 1 is characterized in that this afterimage eliminate circuit also comprises mu balanced circuit, and an end of this mu balanced circuit is electrically coupled to this reference voltage, and the other end is electrically coupled to the logic voltage input end of this gate driver circuit.
3. afterimage eliminate circuit as claimed in claim 2 is characterized in that this mu balanced circuit is a voltage stabilizing diode.
4. afterimage eliminate circuit as claimed in claim 1 is characterized in that this first switching transistor is a bipolar transistor, and this first end, second end and the 3rd end are respectively base stage, the collector and emitter of this bipolar transistor.
5. afterimage eliminate circuit as claimed in claim 1, it is characterized in that this first switching transistor is a mos field effect transistor, this first end, second end and the 3rd end are respectively grid, source electrode and the drain electrode of this mos field effect transistor.
6. afterimage eliminate circuit as claimed in claim 1, it is characterized in that this voltage divider comprises the 3rd resistance and the 4th resistance, the two ends of the 3rd resistance are electrically coupled to the second driving voltage output terminal and this first end of this power-supply unit respectively, and the two ends of the 4th resistance are electrically coupled to this reference voltage and this first end respectively.
7. afterimage eliminate circuit as claimed in claim 1 is characterized in that this reference voltage is a ground voltage.
8. a display is characterized in that this display comprises
Pel array comprises a plurality of dot structures, and each those dot structure comprises at least one active member; And
As any described afterimage eliminate circuit of claim 1-7, wherein the output terminal of this gate driver circuit is electrically coupled to this pel array.
9. display as claimed in claim 8 is characterized in that this display is a LCD.
10. an electronic installation is characterized in that this electronic installation comprises
Display as claimed in claim 8; And
User's interface, with this display electric property coupling to control this display.
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| CN2010101201758A CN101777320B (en) | 2010-01-27 | 2010-01-27 | ghost eliminating circuit, display and electronic device |
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| CN2010101201758A CN101777320B (en) | 2010-01-27 | 2010-01-27 | ghost eliminating circuit, display and electronic device |
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