TWI324761B - A gate driver for eliminating deficient in a display apparatus, and a display apparatus using the same - Google Patents

Description

I8572 twf.doc/y IX. Description of the Invention: [Technical Field] The present invention relates to a type of inter-pole drive circuit, and more particularly to a gate drive device for eliminating the residual image of a display device. [Prior Art] The rapid progress of the Yuxi Refining Society has mostly benefited from the dramatic advancement of semiconductor components and display devices. As for the display device, a thin film transistor liquid crystal display having high space utilization efficiency, low power consumption, and no light-lighting characteristics (Thin Film τ coffee ist〇r Uquid c

Display, TF_T-LCD) has gradually become the mainstream of the market.

Nightingale: -::^ Driving timing diagram of TFT LCD. Traditional TFT optical module. At power-on, the voltage is applied first, including the total power applied to the TFT fluid/display (as shown by curve A). Then, at the timing t, the common TFT and the electric TFT liquid crystal display on the halogen electrode: an image signal (as shown by curve B) to the optical module (such as a curve Γ followed by a timing such as turning on the back TFT liquid crystal display) The screaming display panel light source, so that you can continue to participate,

It is first at the timing t M 'd_ to be opposite to its (d) timing. The signal is in the time series / 乂 backlight module' and the input image to the pixel structure liquid crystal display ^ total end, after the county in the timing U closed TFT is the timing iFl ^ off _ back wire group and before the end of the image signal, F2 During this time (usually 16.7 milliseconds), it is called 4761 18572twf.d〇〇/y. • Since the image signal is still present in the halogen structure, and the charge remains on the halogen electrode, these residual charges are not valid. The discharge path, so it takes a while to fully discharge. Therefore, after the TFT liquid crystal display is turned off, image sticking often occurs after the timing tF3. In order to solve the above problem, it is conventional to use an external low voltage detection 1C after the timing tF3, or to build a band gap between the gate driver 1C and The comparator detects the level of the logic power supply. When the level of the logic power supply is detected to decrease to a certain value, the 'low voltage detection integrated circuit (or a combination of the bandgap circuit and the comparator) outputs a low potential signal to the gate drive IC of the TFT liquid crystal display ( Gate driver IQ's afterimage removal control signal pin (χΑ〇Pin) enables the gate driver IC to output a high-potential signal to neutralize the charge in the thin-film transistor stored in the τρτ liquid crystal display to eliminate the shutdown image. However, since the conventional method must detect the logic power supply VDD level of the TFT liquid crystal display, when the logic power supply VDD level is detected, the logic power supply VDD voltage is too low or falls too fast. Difficulty. • In this way, the state of the output of the gate driver IC cannot be ensured. [Invention] In view of the above, it is an object of the present invention to provide an open-circuit driving circuit for a display device. Eliminating the residual image generated when the display device is turned off. • Another object of the present invention is to provide a gate driving circuit for a display device, which is not subject to the standard driving power supply VDD when the shutdown image is removed. The invention is to provide a gate driving circuit which can be applied to a display 8 18572 twf.doc/y. The gate driving circuit of the invention is characterized by a pull-up resistor and an inverting logic. And a number of 曰脰 '考电卿', source extreme coffee == .=(:::__ measured transistor - extreme and high; output - and drive (four) Jin: ft will rotate a number of outputs The signal is not activated. The inverting logic includes three series connections to make the afterimage cancellation control signal have sufficient driving force to drive each;, = mm - the buffer circuit in each channel circuit, and the opening and buffering It is included in the reverse = = level conversion circuit 'reverse = after: number ' electric | level conversion circuit is to convert the source of the logic through the inverse number - 'reverse and then the residual image removal control signal And the logic state outputted by the ^ level conversion circuit enters (4) the output signal to the display skirt. In the present invention, the health wire _ high __ source Γ low = the power supply falls down to the off display attack = two = from The drive power will climb up to the gate power level of the display device. When the power is turned on, until the voltage difference of the power supply is large enough to make the detection transistor turn on, the 1324761 18572twf.doc/y afterimage removal control signal remains high and follows the high voltage drive power supply.

The source is off. At this time, the output of each channel circuit drives the display device according to the shift temporary storage control signal provided by the preset shift register. When the power is turned off, until the voltage difference between the reference voltage and the low-voltage driving power supply is small enough to make the detecting transistor turn off, the after-image removal control signal is low and follows the low-voltage driving power supply, and the output signal of each channel circuit will output high. The potential, in turn, neutralizes the charge of the thin film transistor stored in the display device to eliminate the shutdown of the display device. a is that the gate driving circuit of the present invention has a circuit for detecting a low-street driving power supply (VGL) of the display device, and can be used to control the (four) state of the gate driving f when the display device is turned off, so The low voltage detection integrated circuit is also unaffected by the standard drive power (VDD). In this way, the cost can be reduced and the (four) pole crane circuit can solve the shutdown image of the display device in the display device. In order to make the above and other features and advantages of the present invention more obvious and easy to understand, the special feature is better, and the ship's closed type is described in detail below. L. The method of driving is shown in accordance with a preferred embodiment of the present invention. Referring to Fig. 2, the gate driving circuit 200 of the present invention includes a pull-up resistor 2〇j gate 205 and a plurality of donations, #φ/贞电电日日2G3, and inverted logic pass circuits 213a-213n. Pull-up resistor 2〇1 door, ρ, ι^曰: θ 曰 body 203 is not extreme and high-voltage drive power VGH ', L ° in the present example, detection transistor 1324761 18572twf.doc / y 203 It can be an NMOS FET. The high voltage driving power supply VGH can be 2〇v, the low voltage driving power supply VGL can be -6V, and the reference voltage vb can be between 0~-IV. The input terminal of the inverting logic gate 205 is coupled to the Zener voltage of the detecting transistor 2〇3. The output terminal is coupled to an input terminal of each of the channel circuits 213a to 213n opposite to the gates 216a to 216n. A plurality of inverters 207, an inverter 209, and an inverter 211 connected in series are included in the inverting logic gate 2〇5. The input of the inverter 207 is switched to the & and the output of the inverter 209 is coupled to the inverter 211. The input terminal of the inverter 211 outputs an afterimage removal control signal XAO. In the present embodiment, the three series inverters 207, 209, and 211 of the inverting logic gate 205 are used to boost the driving ability of the output afterimage removal control signal XAO of the inverting logic gate 205 to eliminate the residual image. The control signal χΑΟ has sufficient driving force to drive the respective channel circuits 213a to 213n. The driving power of the inverting logic gate 205 is a low voltage driving power source VGL and a high voltage driving power source VGH. As is well known, the inverting logic gate 205 is used as an inverting output buffer circuit for detecting the drain voltage of the transistor 203. However, when the detection of the gate voltage of the transistor 203 has sufficient driving force, the inverted logic gate 205 can be omitted. • Each of the channel circuits 213a to 213n includes inverters 214a to 214n, voltage level conversion circuits 215a to 215n, inverse gates 216a to 216n, and buffers 217a to 217n. The inverters 214a-214n are configured to receive the output signals SR1 SRSRn of the shift temporary 18572 twf, d〇c/y register (not shown in FIG. 2), and output to the voltage level conversion circuit 215a~ At the input of 215n, the voltage level conversion circuits 215a to 215n convert the potentials of the output signals of the inverters 214a to 214n. For example, when the outputs of the inverters 214a to 214n are in a high logic state (the potential of which is the standard driving power supply VDD), the electric waste level conversion circuit 2. 15 215 η η converts the potential into a potential High-voltage drive power ν G Η logic, high signal. On the other hand, when the outputs of the inverters 214a to 214n are in a low logic state (the low potential is the standard ground power source vss), the voltage level conversion circuits 215a to 215n convert them into potentials for the low voltage driving power source VGL. Logical low signal. That is to say, the input and output signals of the voltage level conversion circuits 215a to 215n have the same logic (same logic high or the same logic low), but the voltage levels are different. In this embodiment, inside the channel circuits 213a to 213n, the logic gates located in front of the voltage level conversion circuits 215a to 215n are driven by the standard driving power source VDD and the standard ground power source vss, and the ink level conversion circuit is used. The logic gates behind 215a~215η are driven by the high voltage driving power supply VGH and the low voltage driving power supply VGL. In this embodiment, the standard driving power supply VDD can be 3.3V, and the standard grounding power supply vss can be 〇v. Thereby, the logic states converted by the voltage level conversion circuits 215a to 215n are sent to the other input terminals of the opposite gates 216a to 216n, and the gates 216a to 216n are reversed according to the afterimage removal control signal χ Α 〇 The logic signals of the voltage level conversion circuits 215a to 215n are logically operated, and the output signals 〇UT1 to 〇UTn are sent to the display device via the buffers 217a to 217n. . 1324761 18572twf.doc/y Figure 3 illustrates a preferred embodiment of the present invention. Please refer to FIG. 2 and FIG. 3 together. When the power supply is turned on: the current sequence is the standard driving power supply VDD - the low voltage driving power supply voltage driving power supply VGH, at this time, the power supply circuit generates the power supply sequence in order to avoid the secret driving. The circuit itself is locked (10) she

=), causing damage to the display device. Since the logic state of the power supply is not stable, the state of the afterimage removal control signal 为 is low (0V) before the timing tQ, and the low voltage driving power supply VGL and the high voltage driving power supply VGH are also low, so the detection is performed. Since the transistor 2〇3 cannot be turned on at this time, the outputs OUT1 to OUTn of the respective channel circuits 213a to 213n are all in a low potential state. In the present embodiment, the on-off condition of the detecting transistor 203 is based on the voltage difference between the reference voltage VB and the low-voltage driving power source VGL to determine whether the detecting transistor 203 is turned on or off. When the voltage difference between the reference voltage VB and the low-voltage driving power source VGL is greater than a threshold voltage, for example, 3V, the detecting transistor 2〇3 is turned on; when the voltage difference between the reference voltage VB and the low-voltage driving power source VGL is less than the critical value When the voltage is, for example, 3 V, the detecting transistor 203 is turned off. After the timing to, the low voltage driving power source VGL starts to fall, and when the voltage difference between the reference voltage VB of the timing ti and the low voltage driving power source VGL is greater than the threshold voltage, the detecting transistor 203 starts to conduct (ie, A of FIG. 3). point). At timings ti~t2, the detection transistor 203:; and the extreme voltage will follow the level of the low voltage driving power supply VGL. Therefore, at the timing t3~u, the input terminal of the inverting logic gate 205 receives a low-level logic 13 1324761 18572twf.doc/y state, so that the after-image cancellation control signal XA is chased by the level of p VGH and outputs A high-potential logic = a high-voltage driving power supply 213a to 213n reverses a turn of the gates 216a to 216n: to each channel circuit when the power supply can be regarded as stable, the signal XAO is regarded as a high-potential logic state at timings t4 to t5 , 残~' 肖除控

Preface (4) All electrical pastes are stable. And when =: Continue: The power supply has stabilized', so that the gate drive circuit 2〇〇 enters positive aj & (Nonnal 0peration), with the preset shift register hang = 乍 = SR BU SRn in turn to high potential The signal is then converted by the voltage level ^ = 215a~215η, so that the gate drive circuit 2 〇〇 all the outputs oim~0UTn sequentially drive the display device for the high voltage drive power = = bit '. In addition, when timing t6, the power supply will start to gradually turn off. When the power supply age is after the timing t7, the potential of the fresh power supply VDD and the high voltage drive power supply VGH starts to drop, and the low voltage drive power supply VGL potential is 2 liters. Waiting until the timing Μ, the voltage difference between the low voltage driving power supply VGL and the reference voltage is less than the threshold voltage, which will cause the detecting transistor 2〇3 to be turned off (ie, point B in Fig. 3). Therefore, at timings t7 to t8, the detection transistor 203 and the extreme voltage follow the high voltage driving power source VGH. Therefore, when the timing is turned off, the input terminal of the inverting logic gate 205 receives a high-potential logic state, so that the after-image cancellation control signal XAO follows the low-voltage driving power source VGL, and outputs a low-potential logic state to each channel circuit. 213a~213η are an input end of the 216a~216n. In the timing deduction ~ t] 0 ' will make each channel circuit 2] 3a ~ 213n turn 14 18572twf. doc / y OUT 1 ~ OUTn follow the high house drive to reach the shoulder, but still see the power supply, the potential (although the potential The device will "output the state of the electricity" and then pass the charge of the buffer film transistor to the middle and lower devices, so that it can be stored in the display device, for example, as shown in Fig. 2: to achieve the elimination of the shutdown image. Detecting the transistor 203 Start the lead; no timing U and t8, the timing U is the time of the off. According to the above, when the sequence / is the detection of the crystal (four) 3

The voltage difference is large (four) boundary voltage (3^[up and down_power VGL pass; when the reference voltage VB and the low voltage make the detection transistor 203 lead the power supply VGL voltage difference is less than the gap 3V Α 电 point ^ low / Drive power VGL (can be, time point. *.., electricity is the test transistor 203 # conduction close t8, wall: ^^ sequence & ^ 贞 test transistor 2G3 off time point. Timing When the power is turned off, the gate driving circuit is still kinetic energy ΐ 'to neutralize all the films stored in the display device 、, 、, what is the effect of eliminating the afterimage of the shutdown is also better. The display stem is provided by the present invention. An inter-pole driving circuit is used for detecting a logic state in which the output is kept at a high potential when the device is turned off, and neutralizing the charge of the thin film transistor stored in the display device to solve the problem that the display device is turned off. It is not affected by the standard drive power vDD, and can correctly detect the time when the power is turned off, so it can ensure the accuracy of the output of the gate drive circuit. In addition, the circuit structure is simple, which can reduce the cost of production. 15 1324761 !8572twf.doc/y though However, the present invention has been disclosed in the preferred embodiments as a limitation of the present invention, and anyone skilled in the art, in the course of the invention, may make some modifications and retouchings. The scope is defined as a brief description of the drawing. Fig. 1 is a driving timing diagram of a TFT liquid crystal display. The electric gate = the gate driving circuit not according to a preferred embodiment of the present invention.

3 is a timing diagram of a gate driving circuit according to the present embodiment. [Main component symbol description] 200: gate driving circuit 201: pull-up resistor 203: detecting transistor 205: inverting logic 207, 209, 211 214a to 214c: inverters 213a to 213c: channel circuits

215a to 215c: voltage level conversion circuits 216a to 216c: opposite gates 217a to 217c: buffer A: detecting transistor conduction time point B: detecting transistor off time point VB: reference voltage VGL: low voltage driving power supply VGH: High-voltage driving power supply 1324761 18572twf.doc/y VDD: Standard driving power supply VSS: Standard grounding power supply ΧΑΟ : After-image removal control signals SR1 to SRn: Shift register output signals OUT1 to OUTn: Output of gate drive circuit tNl , tN2, tN3, tFl, tF2, tF3, t〇~tlO: Japanese temple order

17

Claims (1)

18572twf.doc/y X. Patent application scope·· 1 々-species-pole drive circuit, suitable for---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- a gate of the electric dust and a source coupled to a low voltage driving power supply (VGL); a pull-up resistor coupled to the drain of the detecting transistor and a high voltage f power source ( Between VGH), the shaft power supply (VGL) is paired with the high voltage driving power supply (VGH); an inverting logic gate receives the drain voltage of the test transistor and outputs an afterimage removal a control signal (ΧΑ〇); and a channel circuit, receiving the afterimage removal control signal (χΑ〇), and rotating a plurality of output signals to drive the display device; when the power is off, making the reference voltage (VB) and When the voltage difference between the low-voltage driving voltage (VGL) is small enough to turn off the detecting transistor, the = elimination control signal (XAq) is low, and the signal of the channel circuits is synchronized. High potential, so that the charge stored in the display device; 0, to eliminate the display device Blur. 2. The gate driving circuit according to claim 1, wherein the closing comprises a plurality of inverters connected in series to enable the residual image iJL(XAO) to have sufficient driving force to drive The channel power 3. According to the gate crane circuit described in the scope of the patent application, each channel circuit includes: "zhong reverse phase benefit, receiving a shift register output signal; 1324761 !8572twf.doc/y An electric dust level conversion circuit that converts the shift register input bit into the low voltage drive power source. One of the powers of the ;; the original (VGL) or remote voltage drive power supply (ν〇Η) and the gate 'to eliminate the control of the charge (the inverse conversion circuit performs the inverse logic operation; and the voltage quasi-buffer' buffer The output signal of the output of the reverse gate. (4) The 4-channel circuit 4 is closed as described in the scope of the patent application, when the power source is initially, until the widower is strict, the dynamic circuit, its, e MWT , A nj 4 翏 test voltage (VB) and the low-voltage drive Ray II) difference is large enough to touch the _ transistor control key (x butterfly is high potential and follow the high feed = device 5 package: species The display device has the capability of eliminating the residual image of the shutdown, and the display has a gate driving circuit, including: The reference voltage (VB) and the low-low detection transistor are coupled to a voltage driving power supply (VGL); a pull-up resistor is secret between the detecting transistor and the --hybrid driving power supply (VGH), which is low a dynamic power supply (VGL) is paired with the high voltage driving power supply (VGH); an inverted access gate receives a drain voltage of the detecting transistor and outputs an afterimage removal control signal (XAO); a plurality of channel circuits, receiving the afterimage removal control signal (χΑ〇), and outputting a complex output signal to drive the display to be set; 19 丄:)ΖΗ·/ϋ 丄18572twf.doc/y source off, 'until the reference voltage (VB) and the low-voltage driving electrical difference is small enough for the detecting transistor to strike, the residual output signal is synchronized to the high-power i of the channel circuits to eliminate the charge in the display The display device of the above-mentioned test, wherein the detection is coupled to the pull-up resistor and the inverting logic gate; -A m 'connected to the reference voltage (νΒ); and the source Extremely, ♦ the horse is connected to the low voltage drive power supply (VGL). 7. The logic gate of item 5 of the scope of patent application includes a plurality of tandem inverse two g: the counter signal (ΧΑΟ) has enough $ bottle ":. Xiao to make a ha, in addition to controlling the driving force To drive the channel power and 8 · as mentioned in the scope of claim 5, the circuit includes: · "Stomach Qiao" in which each pass. 'Receive a shift temporary output signal; - Dust level a conversion circuit that converts the shift bit into one of the low-side motion, one of the (four) μ-breaking powers, the power supply (vgl) or the high-dynamic power supply (VGH) gate' to eliminate the control signal for the afterimage (ΧΑ 〇) 盥哕 盥哕 转换 转换 电路 进行 ; 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕 盥哕The display device according to item 5, wherein, when the 20 1324761 I8572 twf.doc/y driving power supply () is a kind of gate driving circuit, the adaptive circuit is characterized in that: the phase is in a display, the room is Extremely driven to f ^ electric day 0 body 'coupling - health drive power (VGL), and according to a reference (VB) and the low-voltage drive \ _ The transistor is turned on; the power supply (VGL) is determined whether the _ ΐ ^ 二 二 二 二 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻 轻And the multi-channel circuit responds to the shutdown image of the display device. The I 仏 is used to perform the gate drive circuit described in claim 10, and the detection circuit in JL. The crystal has: an eighth pole connected to the first end of the pull-up resistor; a gate coupled to the reference voltage (VB); and a source coupled to the low voltage driving power source ( VGL). Each box (4) describes the crane circuit, one of which is inverted to receive a shift register output signal; an electric fresh bit conversion secret, the shift temporary storage ί output (4) is converted into the The low-voltage driving power supply (VGL) or the high-voltage driving power supply &-reversing gate is opposite to the voltage level of the voltage measuring circuit and the voltage conversion circuit 21 1324761 18572 twf.doc/y and the bit conversion circuit - The buffer 'buffers the output of the inverse gate, the output signal. '』The salt channel circuit idle drive The circuit further comprises an inverting logic comprising: a hard-working circuit - a - inverting H, the input end of which is connected to the (four) first end; and a second inverter 'the input end of which is switched to the first - Inverter ^ output, and output: afterimage removal of the second inverter wheel out 14. If the application paste range is 13th: the inverting logic gate is the inverting output - buffering the electric charge t to eliminate the control money ( XA__(four) circuit. In the residual shirt, the gate drive circuit described in item 1G of the entangled body, the source female until the reference voltage (VB) and the low m drive electric mu follow the high-voltage output power supply (wide 4 S 2 I to the test voltage (VB) and the low-voltage drive power (V〇L) bit, the output signals of some of the channel circuits are synchronized to a high potential, so that the display is stored in the display *%, set the shutdown afterimage . , the inner electric and the neutral, to eliminate the display skirt 22