TWI417852B - Liquid crystal display and driving circuit thereof - Google Patents

Description

Liquid crystal display and its driving circuit

The present invention relates to a liquid crystal display and a driving circuit thereof, and more particularly to a liquid crystal display and a driving circuit thereof that can quickly and completely eliminate image sticking after the liquid crystal display is turned off.

Flat panel displays, such as liquid crystal displays (LCDs), are widely used in personal digital assistants due to their high image quality, small size, light weight, low driving voltage, and low power consumption. Consumer communication or electronic products such as Assistant, PDA), mobile phones, camcorders, notebook computers, desktop monitors, car monitors and projection TVs, and gradually replaced cathode ray tubes (CRT) And become the mainstream of the display.

In a typical liquid crystal display architecture, after the liquid crystal display is turned off, the residual image is often seen on the liquid crystal display panel, and sometimes it disappears after a few seconds. This phenomenon not only does not meet the user's visual expectation, but also reduces the liquid crystal display for a long time. The display quality of the panel. Taking a Thin Film Transistor (TFT) liquid crystal display as an example, one of the main causes of the residual image phenomenon is that the discharge speed of the pixel electrode of the thin film transistor liquid crystal display is too slow, so that the charge cannot be turned off after the shutdown. It is quickly released and remains in the capacitance of the pixel electrode, so that it must wait for a while before it is completely discharged.

Therefore, in a liquid crystal display, a reset circuit is usually included. It is used for detecting the power supply voltage in the liquid crystal display, and determining whether the liquid crystal display is about to be turned off according to the level of the power supply voltage, thereby controlling the voltage of a reset signal XAO. In detail, in the case of normal power supply of the liquid crystal display, the above reset signal XAO will be high; and when the liquid crystal display is turned off, the above reset signal XAO will be low. When the reset signal XAO is low, if its first operating voltage VDD has not dropped to a low potential, each scan line on the liquid crystal panel of the liquid crystal display is turned on, so that the charges on the pixel electrodes thereof are in the middle of each other. And, and speed up the elimination of afterimages.

1 is a functional block diagram of a conventional liquid crystal display. Referring to FIG. 1 , the liquid crystal display 100 has a reset circuit 10 , a gate driver 20 , and a liquid crystal panel 30 . It should be noted that only the portion of the liquid crystal display 100 that is more relevant to the present invention is shown in FIG. 1. The liquid crystal display 100 actually has other components, such as a source driver and a timing control circuit, which are the components of the present invention. It is well known to those of ordinary skill in the art, and the emphasis is placed on the point of emphasis of the present invention.

The output terminal 12 of the reset circuit 10 outputs the above-described reset signal XAO to the gate driver 20. The gate driver 20 has a resistor R and a logic circuit 40. Both ends of the resistor R are coupled to the first operating voltage VDD and the output terminal 12 of the reset circuit 10, respectively. The input of logic circuit 40 is also coupled to output 12 of reset circuit 10. The logic circuit 40 has components such as a shift register and an output buffer for making the output scan line voltage V _G high when the reset signal XAO is low. When the scan line voltage V _G is at a high potential, each scan line of the liquid crystal panel 30 will be at a high potential, so that the thin film transistor coupled to each pixel electrode of the liquid crystal panel 30 is turned on, and the liquid crystal panel 30 is caused to be driven. The charges of the respective pixel electrodes are neutralized with each other.

The reset circuit 10 has a switching element 14 for coupling the output terminal 12 of the reset circuit 10 to the second operating voltage VSS when the first operating voltage VDD drops to a predetermined value. The second operating voltage VSS is typically a ground voltage and will be lower than the first operating voltage VDD. When the liquid crystal display 100 is turned off, the first operating voltage VDD gradually drops to near the second operating voltage VSS. However, when the liquid crystal display 100 is closed and the first operating voltage VDD falls to the second operating voltage VSS, the internal equivalent of the switching element 14 of the reset circuit 10 is made constant because the first operating voltage VDD is continuously reduced. The resistance R _S gradually becomes larger. While the internal equivalent resistance R _S gradually becomes larger, the voltage of the reset signal XAO is boosted. When the voltage of the reset signal XAO is raised to a certain potential, the scan line voltage V _G outputted by the logic circuit 40 is turned to a low potential, thereby causing the thin film transistor to be coupled to each pixel electrode of the liquid crystal panel 30. It will be turned off, and the afterimage of the liquid crystal panel 30 will not be completely eliminated.

The invention provides a driving circuit for a liquid crystal display, which is used to avoid the problem that the residual resistance of the reset circuit is not completely eliminated after the liquid crystal display is turned off.

The present invention provides a liquid crystal display having a driving circuit for extending the voltage of a scanning line of the liquid crystal panel after the liquid crystal display is turned off. The high potential time allows the residual image of the liquid crystal display to be completely and quickly eliminated.

The invention provides a driving circuit for a liquid crystal display. The above driving circuit includes a reset circuit, a pull-up circuit, a buffer, and a pull-down circuit. The reset circuit has an output and is adapted to output a reset signal. The voltage of the reset signal is high when the liquid crystal display is turned on, and is low after the liquid crystal display is turned off. The first end of the pull-up circuit is coupled to the first operating voltage, and the second end of the pull-up circuit is coupled to the output of the reset circuit. The input end of the buffer is coupled to the output of the reset circuit and the second end of the pull-up circuit. The first end of the pull-down circuit is coupled to the output end of the buffer, and the second end of the pull-down circuit is coupled to the second operating voltage.

The invention proposes a liquid crystal display. The above liquid crystal display includes a liquid crystal panel and a driving circuit. The above driving circuit includes a reset circuit, a pull-up circuit, a buffer, and a pull-down circuit. The reset circuit has an output and is adapted to output a reset signal. The voltage of the reset signal is high when the liquid crystal display is turned on, and is low after the liquid crystal display is turned off. The first end of the pull-up circuit is coupled to the first operating voltage, and the second end of the pull-up circuit is coupled to the output of the reset circuit. The input end of the buffer is coupled to the output of the reset circuit and the second end of the pull-up circuit. The first end of the pull-down circuit is coupled to the output end of the buffer, and the second end of the pull-down circuit is coupled to the second operating voltage.

In an embodiment of the invention, the driving circuit further includes a logic circuit. The input end of the logic circuit is coupled to the output end of the buffer and the first end of the pull-down circuit. The output of the logic circuit is coupled to a liquid crystal display Crystal panel. The logic circuit is configured to make a scan line voltage outputted from the output end of the logic circuit high when the first end of the pull-down circuit is low, to eliminate the residual image of the liquid crystal panel.

In an embodiment of the invention, the first operating voltage is higher than the second operating voltage.

In an embodiment of the invention, the pull-down circuit has a pull-down resistor.

In an embodiment of the invention, the pull-up circuit includes a P-type MOSFET and a pull-up resistor. The gate of the P-type MOS field-effect transistor is coupled to the second operating voltage, the source of the P-type MOS field-effect transistor is coupled to the first operating voltage, and the drain of the P-type MOS field-effect transistor is The first end of the pull-up resistor is coupled. The second end of the pull-up resistor is coupled to the output of the reset circuit and the input of the buffer.

In an embodiment of the invention, the resistance value of an internal equivalent resistance of the reset circuit is increased as the first operating voltage decreases.

In one embodiment of the invention, the buffer described above includes two inverters connected in series.

Based on the above, the driving circuit of the liquid crystal display in the embodiment of the present invention can maintain the voltage input to the logic circuit at a low voltage while the internal equivalent resistance becomes large, so that all the thin film transistors on the liquid crystal panel are provided. The longer turn-on time can be maintained after the liquid crystal display is turned off, and the time for neutralizing the charge of the pixel electrode can be extended, and the afterimage of the liquid crystal display can be quickly and completely eliminated.

In order to make the above features and advantages of the present invention more obvious, the following The embodiments are described in detail with reference to the accompanying drawings.

2 is a functional block diagram of a liquid crystal display according to an embodiment of the present invention. Referring to FIG. 2, the liquid crystal display 200 in this embodiment has a liquid crystal panel 30 and a driving circuit 110. The driving circuit 110 is configured to control the opening and closing of a thin film transistor (not shown) on a plurality of scanning lines (not shown) of the liquid crystal panel 30. The drive circuit 110 has a reset circuit 10, a pull-up circuit 120, a buffer 130, a pull-down circuit 140, and a logic circuit 150. It should be noted that only the portion of the liquid crystal display 200 that is more relevant to the present invention is shown in FIG. 2. The liquid crystal display 200 actually has other components, such as a source driver, a timing control circuit, etc., for convenience of explanation. For the sake of this, it will be omitted here.

The reset circuit 10 has an output 12 and is adapted to output the reset signal XAO described above. The voltage of the reset signal XAO is high when the liquid crystal display 200 is turned on, and is low after the liquid crystal display 200 is turned off. The first end 122 of the pull-up circuit 120 is coupled to the first operating voltage VDD, and the second end 124 of the pull-up circuit 120 is coupled to the output 12 of the reset circuit 10. The input 132 of the buffer 130 is coupled to the output 12 of the reset circuit 10 and the second end 124 of the pull-up circuit 122. The first end 142 of the pull-down circuit 140 is coupled to the output 134 of the buffer 130, and the second end 144 of the pull-down circuit 140 is coupled to the second operating voltage VSS. The first operating voltage VDD is generally a positive voltage, and the second operating voltage VSS is generally a ground voltage.

The logic circuit 150 has components such as a shift register, an output buffer, and the like. The input 152 of the logic circuit 150 is coupled to the output 134 of the buffer 130 and the first end 142 of the pull-down circuit 140. The output end 154 of the logic circuit 150 is coupled to the liquid crystal panel 30 of the liquid crystal display 200. The logic circuit 150 is configured to make the scan line voltage V _G outputted by the voltage XAO2 high when the voltage XAO2 is low. When the scan line voltage V _G is at a high potential, each scan line of the liquid crystal panel 30 will be at a high potential, so that the thin film transistor coupled to each pixel electrode of the liquid crystal panel 30 is turned on, and the liquid crystal panel 30 is caused to be driven. The charges of the respective pixel electrodes are neutralized with each other, whereby the afterimage of the liquid crystal panel 30 is quickly and completely eliminated after the liquid crystal display 200 is turned off.

The reset signal XAO output by the output 12 of the reset circuit 10 is transferred to the second terminal 124 of the pull-up circuit 122 and the input terminal 132 of the buffer 130. The pull-up circuit 122 includes a P-type MOS field-effect transistor (PMOSFET) P1 and a pull-up resistor R _H . The gate of the P-type MOS field-effect transistor P1 is coupled to the second operating voltage VSS, the source of the P-type MOS field-effect transistor is coupled to the first operating voltage VDD, and the P of the P-type MOS field-effect transistor The pole is coupled to one end of the pull-up resistor R _H . The other end of the pull-up resistor R _H is coupled to the output terminal 12 of the reset circuit 10 and the input terminal 132 of the buffer 130. Further, in the present embodiment, the pull-down circuit 140 has a pull-down resistor R _L .

Since the second operating voltage VSS is applied to the gate of the P-type MOS field-effect transistor P1, the P-type MOS field-effect transistor P1 is turned on. Further, when the liquid crystal display 200 is turned on, the switching element 14 of the reset circuit 10 is turned off, so that the voltage of the reset signal XAO is maintained at a high potential at this time. In contrast, the switching element 14 of the reset circuit 10 is turned on for a short period of time after the liquid crystal display 200 is turned off, and the resistance value of the internal equivalent resistance R _S is small when the liquid crystal display 200 is just turned off. It can be ignored, so the voltage of the reset signal XAO at this time is almost equal to the second operating voltage VSS and is at a low potential. However, when the liquid crystal display 200 is turned off, the first operating voltage VDD gradually decreases to approach the second operating voltage VSS as time elapses, and when the first operating voltage VDD becomes smaller, the switching element 14 is affected. The degree of conduction is such that the resistance value of the internal equivalent resistance R _S becomes larger as the first operating voltage VDD decreases. When the resistance value of the internal equivalent resistance R _S becomes larger, the voltage of the reset signal XAO also rises.

In the present embodiment, the voltage XAO2 output by the buffer 130 may be different because the voltage of the reset signal XAO is closer to the first operating voltage VDD or closer to the second operating voltage VSS. In detail, when the voltage of the reset signal XAO is closer to the first operating voltage VDD, the voltage XAO2 is equal to the first operating voltage VDD; and when the voltage of the reset signal XAO is closer to the second operating voltage VSS, the voltage XAO2 will It is equal to the second operating voltage VSS. Further, after the liquid crystal display 200 is turned off, even if the resistance value of the internal equivalent resistance R _S becomes large, the voltage of the reset signal XAO is equal to (by the voltage drop of the pull-up resistor R _H and the internal equivalent resistance R _S ) ( VDD × R _S / (R _H + R _S )). In addition, since the pull-down resistor R _{L of the} pull-down circuit 140 is coupled to the second operating voltage VSS, when the liquid crystal display 200 is turned off, the voltage XAO2 outputted by the buffer 130 is maintained at the second operating voltage VSS, thereby making The scan line voltage V _G outputted by the logic circuit 150 is maintained at a high potential for a long period of time. Therefore, compared with the circuit of FIG. 1, with the driving circuit 110 of the embodiment, all the thin film transistors on the liquid crystal panel 30 can be maintained for a long time after the liquid crystal display 200 is turned off, and then used to neutralize the pixels. The time of the charge of the electrodes can be extended, and the afterimage of the liquid crystal display can be quickly and completely eliminated.

Further, in another embodiment of the present invention, when the liquid crystal display 200 is turned off, the P-type metal oxide half field effect transistor P1 is also immediately turned off, so that the voltage of the reset signal XAO is equal to the second operating voltage VSS. When the voltage of the reset signal XAO is equal to the second operating voltage VSS, the voltage XAO2 of the first terminal 142 of the pull-down circuit 140 is also equal to the second operating voltage VSS, and the scan line voltage V _G is maintained for a long time. High potential.

In an embodiment of the invention, the buffer 130 includes two serially connected inverters (not shown) for performing the inversion processing on the reset signal XAO twice, and then outputting the voltage XAO2.

In the embodiment of FIG. 2, the pull-up circuit 120, the buffer 130, the pull-down circuit 140, and the logic circuit 150 of the drive circuit 110 are disposed within the gate driver 160. However, the invention is not limited thereto. In other embodiments of the present invention, the components of the driving circuit 110 may be disposed in whole or in part outside the gate driver 160, or may be disposed in whole or in part within the gate driver 160.

In summary, the driving circuit of the liquid crystal display device in the above embodiment of the present invention can maintain the scan line voltage outputted by the logic circuit at a high voltage for a long time when the internal equivalent resistance becomes large, so that LCD panel All of the thin film transistors can maintain a longer turn-on time after the liquid crystal display is turned off, and the time for neutralizing the charge of the pixel electrode can be extended, and the residual image of the liquid crystal display can be quickly and completely eliminated.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Reset circuit

12‧‧‧ Output

14‧‧‧Switching elements

20‧‧‧gate driver

30‧‧‧LCD panel

40‧‧‧Logical Circuit

110‧‧‧Drive circuit

120‧‧‧ Pulling circuit

122‧‧‧ first end

124‧‧‧ second end

130‧‧‧buffer

132‧‧‧ input

134‧‧‧output

140‧‧‧ pull down circuit

142‧‧‧ first end

144‧‧‧ second end

150‧‧‧Logical Circuit

152‧‧‧ input

154‧‧‧ Output

200‧‧‧LCD display

XAO‧‧‧Reset signal

XAO2‧‧‧ voltage

VDD‧‧‧First operating voltage

VSS‧‧‧second operating voltage

R‧‧‧resistance

R _H ‧‧‧ Pull-up resistor

R _L ‧‧‧ pull-down resistor

R _S ‧‧‧ internal equivalent resistance

P1‧‧‧P type gold oxide half field effect transistor

Scan line voltage V _G ‧‧‧

1 is a functional block diagram of a conventional liquid crystal display.

2 is a functional block diagram of a liquid crystal display according to an embodiment of the present invention.

10‧‧‧Reset circuit

12‧‧‧ Output

14‧‧‧Switching elements

30‧‧‧LCD panel

110‧‧‧Drive circuit

120‧‧‧ Pulling circuit

122‧‧‧ first end

124‧‧‧ second end

130‧‧‧buffer

132‧‧‧ input

134‧‧‧output

140‧‧‧ pull down circuit

142‧‧‧ first end

144‧‧‧ second end

150‧‧‧Logical Circuit

152‧‧‧ input

154‧‧‧ Output

200‧‧‧LCD display

XAO‧‧‧Reset signal

XAO2‧‧‧ voltage

VDD‧‧‧First operating voltage

VSS‧‧‧second operating voltage

R _H ‧‧‧ Pull-up resistor

R _L ‧‧‧ pull-down resistor

R _S ‧‧‧ internal equivalent resistance

P1‧‧‧P type gold oxide half field effect transistor

Scan line voltage V _G ‧‧‧

Claims (12)

A driving circuit for a liquid crystal display, comprising: a reset circuit having an output terminal, wherein the reset circuit is adapted to output a reset signal, wherein a voltage of the reset signal is high when the liquid crystal display is turned on, and The first display of the pull-up circuit is coupled to a first operating voltage, and the second end of the pull-up circuit is coupled to the reset circuit. An output terminal, wherein the pull-up circuit comprises: a P-type MOS field-effect transistor (PMOSFET), a source of which is coupled to the first operating voltage, wherein the P-type MOSFET has a half field effect when the liquid crystal display is turned off The transistor is immediately turned off; and a pull-up resistor having a first end coupled to a drain of the P-type MOS field-effect transistor, a second end coupled to the output of the reset circuit and the buffer The input end of the buffer; one input end of the buffer is coupled to the output end of the reset circuit and the second end of the pull-up circuit; and a pull-down circuit, the pull-down circuit a first end coupled to an output of the buffer, the pull One of the second circuit terminal coupled to a second operating voltage. The driving circuit of claim 1, further comprising a logic circuit, wherein an input end of the logic circuit is coupled to the output end of the buffer and the first end of the pull-down circuit, the logic circuit The output end is coupled to a liquid crystal panel of the liquid crystal display, and the logic circuit is used for the pull-down power When the first end of the circuit is low, the voltage of a scan line outputted by the output end of the logic circuit is high to eliminate the residual image of the liquid crystal panel. The driving circuit of claim 1, wherein the first operating voltage is higher than the second operating voltage. The driving circuit of claim 1, wherein the pull-down circuit has a pull-down resistor. The driving circuit of claim 1, wherein the resistance value of an internal equivalent resistance of the reset circuit becomes larger as the first operating voltage decreases. The driving circuit of claim 1, wherein the buffer comprises two inverters connected in series. A liquid crystal display comprising: a liquid crystal panel; and a driving circuit coupled to the liquid crystal panel, the driving circuit comprising: a reset circuit having an output, the reset circuit is adapted to output a reset signal, wherein The voltage of the reset signal is high when the liquid crystal display is turned on, and is low after the liquid crystal display is turned off; and a pull-up circuit, the first end of the pull-up circuit is coupled to a first operating voltage, The second end of the pull-up circuit is coupled to the output end of the reset circuit, wherein the pull-up circuit comprises: a P-type MOS field-effect transistor (PMOSFET), a source coupled to the first Operating voltage, wherein the P-type metal oxide half field effect transistor is immediately turned off when the liquid crystal display is turned off; a pull-up resistor, the first end of which is coupled to a drain of the P-type MOS field-effect transistor, the second end of which is coupled to the output end of the reset circuit and the input end of the buffer; An input end of the buffer is coupled to the output end of the reset circuit and the second end of the pull-up circuit; and a pull-down circuit, the first end of the pull-down circuit is coupled to the first end One output end of the buffer, the second end of the pull-down circuit is coupled to a second operating voltage. The liquid crystal display of claim 7, wherein the driving circuit further comprises a logic circuit, the input end of the logic circuit is coupled to the output end of the buffer and the first end of the pull-down circuit, An output end of the logic circuit is coupled to the liquid crystal panel, wherein the logic circuit is configured to make a scan line voltage outputted by the output end of the logic circuit high when the first end of the pull-down circuit is low Potential to eliminate image sticking of the liquid crystal panel. The liquid crystal display of claim 7, wherein the first operating voltage is higher than the second operating voltage. The liquid crystal display of claim 7, wherein the pull-down circuit is formed by a pull-down resistor. The liquid crystal display of claim 7, wherein the resistance value of an internal equivalent resistance of the reset circuit becomes larger as the first operating voltage decreases. The liquid crystal display of claim 7, wherein the buffer comprises two inverters connected in series.