TW201616472A - Driver circuit with device variation compensation and operation method thereof - Google Patents
Driver circuit with device variation compensation and operation method thereof Download PDFInfo
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- TW201616472A TW201616472A TW103136281A TW103136281A TW201616472A TW 201616472 A TW201616472 A TW 201616472A TW 103136281 A TW103136281 A TW 103136281A TW 103136281 A TW103136281 A TW 103136281A TW 201616472 A TW201616472 A TW 201616472A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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Abstract
Description
本揭露是有關於一種驅動電路,且特別是有關於一種具元件變異補償之驅動電路及其操作方法。 The disclosure relates to a driving circuit, and in particular to a driving circuit with component variation compensation and an operating method thereof.
顯示面板的習知閘極驅動電路使用N型薄膜電晶體(thin film transistor,TFT)。為了持續關閉在掃描線(閘極線)上像素的薄膜電晶體,閘極驅動電路需要把掃描線的電壓(薄膜電晶體的閘極電壓)保持在低電位。在習知閘極驅動電路中,提供低電位的下拉(pull-down)電路需持續開啟,造成薄膜電晶體的持續偏壓。因在持續高電壓偏壓的操作條件下,薄膜電晶體可能產生特性漂移的現象(例如特性衰退及/或臨界電壓的漂移)。薄膜電晶體的特性衰退會使其工作壽命縮短,而電晶體臨界電壓(threshold voltage,Vth)的漂移將影響閘極驅動電路的可靠度。 A conventional gate driving circuit of a display panel uses an N-type thin film transistor (TFT). In order to continuously turn off the thin film transistor of the pixel on the scanning line (gate line), the gate driving circuit needs to keep the voltage of the scanning line (the gate voltage of the thin film transistor) at a low potential. In the conventional gate drive circuit, a pull-down circuit that provides a low potential needs to be continuously turned on, resulting in a continuous bias of the thin film transistor. Thin film transistors may exhibit characteristic drift phenomena (eg, characteristic degradation and/or drift of threshold voltage) under operating conditions that continue to be subjected to high voltage bias. The degradation of the characteristics of the thin film transistor will shorten its working life, and the drift of the threshold voltage (Vth) of the transistor will affect the reliability of the gate driving circuit.
本揭露實施例提供一種驅動電路及其操作方法,其可以補償元件的臨界電壓變異。 The disclosed embodiments provide a driving circuit and an operating method thereof that can compensate for a threshold voltage variation of an element.
本揭露的一實施例提供一種驅動電路,包括上拉開關單元、隔離開關與下拉開關單元。上拉開關單元的第一端耦接至第一電壓。上拉開關單元的第二端耦接至驅動電路的輸出端。隔離開關的第一端耦接至上拉開關單元的第二端。下拉開關單元的第一端耦接至隔離開關的第二端。下拉開關單元的第二端耦接至第二電壓。當驅動電路操作於初始化模式時,該隔離開關為截止,上述下拉開關單元可以取樣下拉開關單元的臨界電壓而獲得下拉臨界電壓值。當驅動電路操作於正常模式時,上述的隔離開關為導通,下拉開關單元使用該截止電壓值補償該下拉開關單元的輸入電壓。 An embodiment of the present disclosure provides a driving circuit including a pull-up switch unit, an isolating switch, and a pull-down switch unit. The first end of the pull-up switch unit is coupled to the first voltage. The second end of the pull-up switch unit is coupled to the output end of the driving circuit. The first end of the isolating switch is coupled to the second end of the pull-up switch unit. The first end of the pull-down switch unit is coupled to the second end of the isolating switch. The second end of the pull-down switch unit is coupled to the second voltage. When the driving circuit operates in the initialization mode, the isolating switch is turned off, and the pull-down switching unit can sample the threshold voltage of the pull-down switching unit to obtain a pull-down threshold voltage value. When the driving circuit operates in the normal mode, the above-mentioned isolating switch is turned on, and the pull-down switching unit uses the cutoff voltage value to compensate the input voltage of the pull-down switch unit.
在本揭露的一實施例中,上述下拉開關單元包括下拉開關以及下拉開關補償電路。下拉開關的第一端耦接至隔離開關的第二端。下拉開關的第二端耦接至第二電壓。下拉開關補償電路耦接於該下拉開關單元的控制端與該下拉開關的控制端之間。當驅動電路操作於初始化模式時,該下拉開關補償電路取樣該下拉開關的臨界電壓而獲得下拉臨界電壓值。當驅動電路操作於正常模式時,該下拉開關補償電路使用該下拉臨界電壓值補償該下拉開關的輸入電壓。 In an embodiment of the disclosure, the pull-down switch unit includes a pull-down switch and a pull-down switch compensation circuit. The first end of the pull-down switch is coupled to the second end of the isolating switch. The second end of the pull-down switch is coupled to the second voltage. The pull-down switch compensation circuit is coupled between the control end of the pull-down switch unit and the control end of the pull-down switch. When the driving circuit operates in the initialization mode, the pull-down switch compensation circuit samples the threshold voltage of the pull-down switch to obtain a pull-down threshold voltage value. When the driving circuit operates in the normal mode, the pull-down switch compensation circuit uses the pull-down threshold voltage value to compensate the input voltage of the pull-down switch.
在本揭露的一實施例中,上述的下拉開關補償電路包括電容、第一開關、第二開關以及第三開關。電容的第一端與第二 端分別耦接於該下拉開關單元的控制端與該下拉開關的控制端。第一開關的第一端與第二端分別耦接於第三電壓與該電容的第二端。第二開關的第一端與第二端分別耦接於該電容的第二端與該下拉開關的第一端。第三開關的第一端與第二端分別耦接於該電容的第一端與該下拉開關的第二端。 In an embodiment of the disclosure, the pull-down switch compensation circuit includes a capacitor, a first switch, a second switch, and a third switch. First and second ends of the capacitor The terminals are respectively coupled to the control end of the pull-down switch unit and the control end of the pull-down switch. The first end and the second end of the first switch are respectively coupled to the third voltage and the second end of the capacitor. The first end and the second end of the second switch are respectively coupled to the second end of the capacitor and the first end of the pull-down switch. The first end and the second end of the third switch are respectively coupled to the first end of the capacitor and the second end of the pull-down switch.
在本揭露的一實施例中,上述的下拉開關補償電路包括電容、第一開關、第二開關以及第三開關。電容的第一端與第二端分別耦接於該下拉開關單元的控制端與該下拉開關的控制端。第一開關的第一端與第二端分別耦接於第三電壓與該電容的第二端。第二開關的第一端與第二端分別耦接於該電容的第二端與該下拉開關的第一端。第三開關的第一端與第二端分別耦接於該電容的第一端與第四電壓。在本揭露的一實施例中,上述的第三電壓為第一系統電壓,而第四電壓為第二系統電壓。 In an embodiment of the disclosure, the pull-down switch compensation circuit includes a capacitor, a first switch, a second switch, and a third switch. The first end and the second end of the capacitor are respectively coupled to the control end of the pull-down switch unit and the control end of the pull-down switch. The first end and the second end of the first switch are respectively coupled to the third voltage and the second end of the capacitor. The first end and the second end of the second switch are respectively coupled to the second end of the capacitor and the first end of the pull-down switch. The first end and the second end of the third switch are respectively coupled to the first end and the fourth voltage of the capacitor. In an embodiment of the disclosure, the third voltage is a first system voltage and the fourth voltage is a second system voltage.
在本揭露的一實施例中,上述的驅動電路更包括隔離開關補償電路。隔離開關補償電路耦接於該隔離開關的控制端。當驅動電路操作於初始化模式時,隔離開關補償電路取樣該隔離開關的臨界電壓而獲得隔離臨界電壓值。當驅動電路操作於正常模式時,隔離開關補償電路使用該隔離臨界電壓值補償該隔離開關的輸入電壓。 In an embodiment of the disclosure, the driving circuit further includes an isolation switch compensation circuit. The isolation switch compensation circuit is coupled to the control end of the isolation switch. When the driving circuit operates in the initialization mode, the isolation switch compensation circuit samples the threshold voltage of the isolation switch to obtain an isolation threshold voltage value. When the driving circuit operates in the normal mode, the isolation switch compensation circuit uses the isolation threshold voltage value to compensate the input voltage of the isolation switch.
在本揭露的一實施例中,上述的隔離開關補償電路包括電容、第一開關、第二開關以及第三開關。電容的第一端與第二端分別耦接於控制電壓與該隔離開關的控制端。第一開關的第一 端與第二端分別耦接於參考電壓與該電容的第二端。第二開關的第一端與第二端分別耦接於該電容的第二端與該隔離開關的第一端。第三開關的第一端與第二端分別耦接於該電容的第一端與該隔離開關的第二端。 In an embodiment of the disclosure, the above-described isolation switch compensation circuit includes a capacitor, a first switch, a second switch, and a third switch. The first end and the second end of the capacitor are respectively coupled to the control voltage and the control end of the isolating switch. First of the first switch The terminal and the second end are respectively coupled to the reference voltage and the second end of the capacitor. The first end and the second end of the second switch are respectively coupled to the second end of the capacitor and the first end of the isolating switch. The first end and the second end of the third switch are respectively coupled to the first end of the capacitor and the second end of the isolating switch.
在本揭露的一實施例中,上述的隔離開關補償電路包括第一電容、第二電容、第一開關、第二開關、第三開關以及第四開關。第一電容的第一端耦接於控制電壓。第二電容的第一端與第二端分別耦接於該第一電容的第二端與該隔離開關的控制端。第一開關的第一端與第二端分別耦接於參考電壓與該第二電容的第二端。第二開關的第一端與第二端分別耦接於該第二電容的第二端與該隔離開關的第一端。第三開關的第一端與第二端分別耦接於該第二電容的第一端與該隔離開關的第二端。第四開關的第一端與第二端分別耦接於該第一電容的第一端與第二端。 In an embodiment of the disclosure, the isolation switch compensation circuit includes a first capacitor, a second capacitor, a first switch, a second switch, a third switch, and a fourth switch. The first end of the first capacitor is coupled to the control voltage. The first end and the second end of the second capacitor are respectively coupled to the second end of the first capacitor and the control end of the isolating switch. The first end and the second end of the first switch are respectively coupled to the reference voltage and the second end of the second capacitor. The first end and the second end of the second switch are respectively coupled to the second end of the second capacitor and the first end of the isolating switch. The first end and the second end of the third switch are respectively coupled to the first end of the second capacitor and the second end of the isolating switch. The first end and the second end of the fourth switch are respectively coupled to the first end and the second end of the first capacitor.
在本揭露的一實施例中,上述的隔離開關補償電路包括第一電容、第二電容、第一開關、第二開關以及第三開關。第一電容的第一端耦接於控制電壓。第二電容的第一端與第二端分別耦接於該第一電容的第二端與該隔離開關的控制端。第一開關的第一端與第二端分別耦接於參考電壓與該第二電容的第二端。第二開關的第一端與第二端分別耦接於該第二電容的第一端與該隔離開關的第二端。第三開關的第一端與第二端分別耦接於該第一電容的第一端與第二端。 In an embodiment of the disclosure, the isolation switch compensation circuit includes a first capacitor, a second capacitor, a first switch, a second switch, and a third switch. The first end of the first capacitor is coupled to the control voltage. The first end and the second end of the second capacitor are respectively coupled to the second end of the first capacitor and the control end of the isolating switch. The first end and the second end of the first switch are respectively coupled to the reference voltage and the second end of the second capacitor. The first end and the second end of the second switch are respectively coupled to the first end of the second capacitor and the second end of the isolating switch. The first end and the second end of the third switch are respectively coupled to the first end and the second end of the first capacitor.
在本揭露的一實施例中,上述的驅動電路更包括輸出下 拉開關。輸出下拉開關的第一端耦接至該驅動電路的輸出端。輸出下拉開關的第二端耦接至該第二電壓。 In an embodiment of the disclosure, the above driving circuit further includes an output Pull the switch. The first end of the output pull-down switch is coupled to the output of the drive circuit. The second end of the output pull-down switch is coupled to the second voltage.
在本揭露的一實施例中,上述的驅動電路更包括控制單元。控制單元的輸入端耦接至該驅動電路的輸入端。控制單元的第一輸出端與第二輸出端分別耦接至該上拉開關單元的控制端與該下拉開關單元的控制端。 In an embodiment of the disclosure, the driving circuit further includes a control unit. The input end of the control unit is coupled to the input of the drive circuit. The first output end and the second output end of the control unit are respectively coupled to the control end of the pull-up switch unit and the control end of the pull-down switch unit.
在本揭露的一實施例中,上述的控制單元包括第一電晶體、第二電晶體、第三電晶體以及第四電晶體。第一電晶體的第一端耦接至第一電壓。第一電晶體的第二端耦接至該上拉開關單元的控制端。第一電晶體的控制端耦接至該驅動電路的輸入端。第二電晶體的第一端耦接至該第一電晶體的第二端。第二電晶體的第二端耦接至該第二電壓。第二電晶體的控制端耦接至該下拉開關單元的控制端。第三電晶體的第一端耦接至該第一電壓。第三電晶體的第二端耦接至該第二電晶體的控制端。第四電晶體的第一端耦接至該第三電晶體的第二端。第四電晶體的第二端耦接至該第二電壓。第四電晶體的控制端耦接至該驅動電路的輸入端。 In an embodiment of the disclosure, the control unit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first end of the first transistor is coupled to the first voltage. The second end of the first transistor is coupled to the control end of the pull-up switch unit. A control end of the first transistor is coupled to an input end of the driving circuit. The first end of the second transistor is coupled to the second end of the first transistor. The second end of the second transistor is coupled to the second voltage. The control end of the second transistor is coupled to the control end of the pull-down switch unit. The first end of the third transistor is coupled to the first voltage. The second end of the third transistor is coupled to the control end of the second transistor. The first end of the fourth transistor is coupled to the second end of the third transistor. The second end of the fourth transistor is coupled to the second voltage. A control end of the fourth transistor is coupled to an input end of the driving circuit.
本揭露的一實施例提供一種驅動電路的操作方法。其中,該驅動電路包括上拉開關單元、隔離開關與下拉開關單元。上拉開關單元的第一端與第二端分別耦接至第一電壓與該驅動電路的輸出端,其中該第一電壓為第一系統電壓。隔離開關的第一端耦接至該上拉開關單元的第二端。下拉開關單元的第一端與第二端分別耦接至該隔離開關的第二端與第二電壓,其中該第二電 壓為第二系統電壓。所述操作方法包括:當該驅動電路操作於初始化模式時,截止該隔離開關;當該驅動電路操作於該初始化模式時,取樣該下拉開關單元的臨界電壓而獲得下拉臨界電壓值;當該驅動電路操作於一正常模式時,導通該隔離開關;以及當該驅動電路操作於該正常模式時,使用該下拉臨界電壓值補償該下拉開關單元的輸入電壓。 An embodiment of the present disclosure provides a method of operating a drive circuit. The driving circuit includes a pull-up switch unit, an isolating switch and a pull-down switch unit. The first end and the second end of the pull-up switch unit are respectively coupled to the first voltage and the output end of the driving circuit, wherein the first voltage is the first system voltage. The first end of the isolating switch is coupled to the second end of the pull-up switch unit. The first end and the second end of the pull-down switch unit are respectively coupled to the second end of the isolating switch and the second voltage, wherein the second electric The voltage is the second system voltage. The operating method includes: turning off the isolation switch when the driving circuit operates in an initialization mode; sampling a threshold voltage of the pull-down switching unit to obtain a pull-down threshold voltage value when the driving circuit operates in the initialization mode; When the circuit operates in a normal mode, the isolation switch is turned on; and when the driving circuit operates in the normal mode, the pull-down threshold voltage value is used to compensate an input voltage of the pull-down switch unit.
在本揭露的一實施例中,上述下拉開關單元包括一下拉開關。下拉開關的第一端耦接至該隔離開關的第二端。下拉開關的第二端耦接至該第二電壓。所述操作方法包括:當該驅動電路操作於該初始化模式時,取樣該下拉開關的臨界電壓而獲得該下拉臨界電壓值;以及當該驅動電路操作於該正常模式時,使用該下拉臨界電壓值補償該下拉開關的輸入電壓。 In an embodiment of the disclosure, the pull-down switch unit includes a pull-down switch. The first end of the pull-down switch is coupled to the second end of the isolating switch. The second end of the pull-down switch is coupled to the second voltage. The operating method includes: sampling a threshold voltage of the pull-down switch to obtain the pull-down threshold voltage value when the driving circuit operates in the initialization mode; and using the pull-down threshold voltage value when the driving circuit operates in the normal mode Compensate for the input voltage of the pull-down switch.
在本揭露的一實施例中,上述下拉開關單元更包括電容。電容的第一端與第二端分別耦接於該下拉開關單元的控制端與該下拉開關的控制端。所述取樣該下拉開關的該臨界電壓之步驟包括:於該初始化模式的充電期間,使該電容的第一端與第二端分別耦接該下拉開關的第二端與第三電壓;以及於該初始化模式的放電期間,使該電容的第一端耦接該下拉開關的第二端,以及使該電容的第二端耦接該下拉開關的第一端與控制端。 In an embodiment of the disclosure, the pull-down switch unit further includes a capacitor. The first end and the second end of the capacitor are respectively coupled to the control end of the pull-down switch unit and the control end of the pull-down switch. The step of sampling the threshold voltage of the pull-down switch includes: coupling the first end and the second end of the capacitor to the second end and the third voltage of the pull-down switch respectively during charging of the initialization mode; During the discharge of the initialization mode, the first end of the capacitor is coupled to the second end of the pull-down switch, and the second end of the capacitor is coupled to the first end and the control end of the pull-down switch.
在本揭露的一實施例中,上述下拉開關單元更包括電容。電容的第一端與第二端分別耦接於該下拉開關單元的控制端與該下拉開關的控制端。所述取樣該下拉開關的該臨界電壓之步 驟包括:於該初始化模式的充電期間,使該電容的第二端與第一端分別耦接第三電壓與第四電壓;以及於該初始化模式的放電期間,使該電容的第一端耦接該第四電壓,以及使該電容的第二端耦接該下拉開關的第一端與控制端。 In an embodiment of the disclosure, the pull-down switch unit further includes a capacitor. The first end and the second end of the capacitor are respectively coupled to the control end of the pull-down switch unit and the control end of the pull-down switch. The step of sampling the threshold voltage of the pull-down switch The method includes: during the charging of the initialization mode, coupling the second end and the first end of the capacitor to the third voltage and the fourth voltage respectively; and during the discharging of the initialization mode, coupling the first end of the capacitor The fourth voltage is connected, and the second end of the capacitor is coupled to the first end of the pull-down switch and the control end.
在本揭露的一實施例中,上述的操作方法更包括:當該驅動電路操作於該初始化模式時,取樣該隔離開關的臨界電壓而獲得隔離臨界電壓值;以及當該驅動電路操作於該正常模式時,使用該隔離臨界電壓值補償該隔離開關的輸入電壓。 In an embodiment of the present disclosure, the operating method further includes: sampling the threshold voltage of the isolation switch to obtain an isolation threshold voltage when the driving circuit operates in the initialization mode; and when the driving circuit operates in the normal state In the mode, the isolation threshold voltage is used to compensate the input voltage of the isolation switch.
在本揭露的一實施例中,上述的驅動電路更包括電容。電容的第一端與第二端分別耦接於控制電壓與該隔離開關的控制端。所述取樣該隔離開關的該臨界電壓之步驟包括:於該初始化模式的充電期間,使該電容的第二端與第一端分別耦接第一參考電壓與第二參考電壓;以及於該初始化模式的放電期間,使該電容的第一端耦接該隔離開關的第二端,以及使該電容的第二端耦接該隔離開關的第一端與控制端。 In an embodiment of the disclosure, the driving circuit further includes a capacitor. The first end and the second end of the capacitor are respectively coupled to the control voltage and the control end of the isolating switch. The step of sampling the threshold voltage of the isolation switch includes: coupling the second end and the first end of the capacitor to the first reference voltage and the second reference voltage respectively during the charging of the initialization mode; and During the discharge of the mode, the first end of the capacitor is coupled to the second end of the isolating switch, and the second end of the capacitor is coupled to the first end and the control end of the isolating switch.
在本揭露的一實施例中,上述的驅動電路更包括電容。電容的第一端與第二端分別耦接於控制電壓與該隔離開關的控制端。所述取樣該隔離開關的該臨界電壓之步驟包括:於該初始化模式的充電期間,使該電容的第二端與第一端分別耦接第一參考電壓與第二參考電壓;以及於該初始化模式的放電期間,使該電容的第一端耦接該隔離開關的第二端,以及使該電容的第二端耦接該第一參考電壓與該隔離開關的控制端。 In an embodiment of the disclosure, the driving circuit further includes a capacitor. The first end and the second end of the capacitor are respectively coupled to the control voltage and the control end of the isolating switch. The step of sampling the threshold voltage of the isolation switch includes: coupling the second end and the first end of the capacitor to the first reference voltage and the second reference voltage respectively during the charging of the initialization mode; and During the discharge of the mode, the first end of the capacitor is coupled to the second end of the isolating switch, and the second end of the capacitor is coupled to the first reference voltage and the control end of the isolating switch.
在本揭露的一實施例中,上述的操作方法更包括:當該驅動電路操作於該初始化模式時,下拉該驅動電路的輸出端的電壓至該第二電壓。 In an embodiment of the disclosure, the operating method further includes: when the driving circuit operates in the initialization mode, pulling down a voltage of an output end of the driving circuit to the second voltage.
基於上述,本揭露實施例所述驅動電路及其操作方法可以利用下拉開關單元取樣其內部的下拉開關的臨界電壓。當驅動電路操作於正常模式時,下拉開關單元可以依據經取樣的臨界電壓去補償下拉開關單元的輸入電壓。因此,本揭露實施例所述驅動電路及其操作方法可以補償元件的臨界電壓變異。 Based on the above, the driving circuit and the operating method thereof according to the embodiments of the present disclosure can sample the threshold voltage of the internal pull-down switch by using the pull-down switching unit. When the driving circuit operates in the normal mode, the pull-down switching unit can compensate the input voltage of the pull-down switching unit according to the sampled threshold voltage. Therefore, the driving circuit and the operating method thereof according to the embodiments of the present disclosure can compensate for the threshold voltage variation of the component.
為讓本揭露能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 In order to make the disclosure more apparent, the following embodiments are described in detail with reference to the accompanying drawings.
100‧‧‧驅動電路 100‧‧‧ drive circuit
110‧‧‧上拉開關單元 110‧‧‧Pull switch unit
120‧‧‧隔離開關 120‧‧‧Isolation switch
130‧‧‧下拉開關單元 130‧‧‧ Pull-down switch unit
131‧‧‧下拉開關 131‧‧‧ pull-down switch
132、133‧‧‧下拉開關補償電路 132, 133‧‧‧ pull-down switch compensation circuit
139‧‧‧控制端 139‧‧‧Control end
140‧‧‧控制單元 140‧‧‧Control unit
141‧‧‧第一電晶體 141‧‧‧First transistor
142‧‧‧第二電晶體 142‧‧‧second transistor
143‧‧‧第三電晶體 143‧‧‧ Third transistor
144‧‧‧第四電晶體 144‧‧‧4th transistor
211‧‧‧電容 211‧‧‧ Capacitance
221‧‧‧第一開關 221‧‧‧First switch
222‧‧‧第二開關 222‧‧‧second switch
223、224‧‧‧第三開關 223, 224‧‧‧ third switch
450‧‧‧輸出下拉開關 450‧‧‧Output pull-down switch
500‧‧‧驅動電路 500‧‧‧ drive circuit
560‧‧‧隔離開關補償電路 560‧‧‧Isolation switch compensation circuit
561‧‧‧電容、第二電容 561‧‧‧Capacitor, second capacitor
562‧‧‧第一開關 562‧‧‧First switch
563‧‧‧第二開關 563‧‧‧second switch
564‧‧‧第三開關 564‧‧‧ third switch
565‧‧‧電容、第一電容 565‧‧‧Capacitor, first capacitor
566‧‧‧第四開關 566‧‧‧fourth switch
P1‧‧‧充電期間 P1‧‧‧Charging period
P2‧‧‧放電期間 P2‧‧‧discharge period
P3‧‧‧充電期間 P3‧‧‧Charging period
P4‧‧‧放電期間 P4‧‧‧Discharge period
PI‧‧‧初始化模式 PI‧‧‧Initial mode
PI1‧‧‧第一期間 PI1‧‧‧ first period
PI2‧‧‧第二期間 PI2‧‧‧ second period
S110~S150‧‧‧步驟 S110~S150‧‧‧Steps
V0‧‧‧控制電壓 V0‧‧‧ control voltage
V1‧‧‧第一電壓 V1‧‧‧ first voltage
V2‧‧‧第二電壓 V2‧‧‧second voltage
V3‧‧‧控制電壓 V3‧‧‧ control voltage
V4‧‧‧電壓 V4‧‧‧ voltage
V5~V11‧‧‧控制信號 V5~V11‧‧‧ control signal
Vc1、Vc2‧‧‧電壓 V c1 , V c2 ‧‧‧ voltage
Vdd‧‧‧系統電壓 Vdd‧‧‧ system voltage
-Vdd‧‧‧負系統電壓 -Vdd‧‧‧negative system voltage
Vin‧‧‧輸入端 Vin‧‧‧ input
Vout‧‧‧輸出端 Vout‧‧‧ output
Vp2‧‧‧電壓 V p2 ‧‧‧ voltage
Vss‧‧‧接地電壓 Vss‧‧‧ Grounding voltage
圖1A是依照本揭露一實施例說明一種驅動電路的電路方塊示意圖。 FIG. 1A is a block diagram showing a circuit of a driving circuit according to an embodiment of the invention.
圖1B是依照本揭露一實施例說明一種驅動電路的操作方法流程示意圖。 FIG. 1B is a schematic flow chart showing an operation method of a driving circuit according to an embodiment of the present disclosure.
圖2是依照本揭露一實施例說明圖1A所示驅動電路的電路示意圖。 FIG. 2 is a circuit diagram showing the driving circuit of FIG. 1A according to an embodiment of the present disclosure.
圖3是依照本揭露一實施例說明圖2所示控制信號之時序示意圖。 FIG. 3 is a timing diagram illustrating the control signal shown in FIG. 2 according to an embodiment of the present disclosure.
圖4是依照本揭露另一實施例說明圖1A所示驅動電路的電 路示意圖。 4 is a diagram illustrating the power of the driving circuit of FIG. 1A according to another embodiment of the present disclosure. Road map.
圖5是依照本揭露另一實施例說明一種驅動電路的電路方塊示意圖。 FIG. 5 is a block diagram showing a circuit of a driving circuit according to another embodiment of the disclosure.
圖6是依照本揭露一實施例說明圖5所示驅動電路的電路示意圖。 FIG. 6 is a circuit diagram illustrating the driving circuit of FIG. 5 according to an embodiment of the present disclosure.
圖7是依照本揭露一實施例說明圖6所示控制信號之時序示意圖。 FIG. 7 is a timing diagram illustrating the control signal shown in FIG. 6 according to an embodiment of the present disclosure.
圖8是依照本揭露另一實施例說明圖5所示驅動電路的電路示意圖。 FIG. 8 is a circuit diagram illustrating the driving circuit of FIG. 5 according to another embodiment of the present disclosure.
圖9是依照本揭露一實施例說明圖8所示控制信號之時序示意圖。 FIG. 9 is a timing diagram illustrating the control signal shown in FIG. 8 according to an embodiment of the present disclosure.
圖10是依照本揭露又一實施例說明圖5所示驅動電路的電路示意圖。 FIG. 10 is a circuit diagram illustrating the driving circuit of FIG. 5 according to still another embodiment of the present disclosure.
在本案說明書全文(包括申請專利範圍)中所使用的「耦接」一詞可指任何直接或間接的連接手段。舉例而言,若文中描述第一裝置耦接於第二裝置,則應該被解釋成該第一裝置可以直接連接於該第二裝置,或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。另外,凡可能之處,在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似部分。不同實施例中使用相同標號或使用相同用語的元件/構件/ 步驟可以相互參照相關說明。 The term "coupled" as used throughout the specification (including the scope of the patent application) may be used in any direct or indirect connection. For example, if the first device is described as being coupled to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be connected through other devices or some kind of connection means. Connected to the second device indirectly. In addition, wherever possible, the elements and/ Components/components that use the same reference numbers or use the same terminology in different embodiments The steps can refer to the relevant instructions.
驅動電路可以依據輸入信號的準位而產生對應的輸出信號來驅動負載電路。在驅動電路的輸出長時間維持在相同準位的情況下,其內部電晶體需要持續被偏壓。以推挽輸出電路為例,在驅動電路的推挽輸出信號維持在低邏輯準位的情況下,驅動電路內推挽輸出電路的下拉(pull-down)電晶體(例如N型電晶體)的偏壓電壓需要持續在高邏輯電位。提供低輸出電位的下拉電晶體因為持續被施加高電壓,造成其電晶體特性可能產生漂移的現象(例如特性衰退及/或臨界電壓的漂移)。 The driving circuit can generate a corresponding output signal according to the level of the input signal to drive the load circuit. In the case where the output of the drive circuit is maintained at the same level for a long time, its internal transistor needs to be constantly biased. Taking a push-pull output circuit as an example, in a case where the push-pull output signal of the driving circuit is maintained at a low logic level, a pull-down transistor (for example, an N-type transistor) of the push-pull output circuit in the driving circuit is used. The bias voltage needs to continue at a high logic potential. A pull-down transistor that provides a low output potential causes a phenomenon in which its transistor characteristics may drift due to continuous application of a high voltage (for example, characteristic degradation and/or drift of a threshold voltage).
再舉例來說,顯示面板的閘極驅動電路可以使用N型薄膜電晶體(thin film transistor,TFT)。為了持續關閉在掃描線(閘極線)上像素的薄膜電晶體,閘極驅動電路需要把掃描線的電壓(薄膜電晶體的閘極電壓)保持在低電位。在習知閘極驅動電路中,提供低電位的下拉(pull-down)電路需持續開啟,造成薄膜電晶體的持續偏壓。在持續高電壓偏壓的操作條件下,薄膜電晶體可能產生特性漂移的現象(例如特性衰退及/或臨界電壓的漂移)。薄膜電晶體的特性衰退會使其工作壽命縮短,而電晶體臨界電壓(threshold voltage,Vth)的漂移將影響閘極驅動電路的可靠度。 For another example, the gate driving circuit of the display panel may use an N-type thin film transistor (TFT). In order to continuously turn off the thin film transistor of the pixel on the scanning line (gate line), the gate driving circuit needs to keep the voltage of the scanning line (the gate voltage of the thin film transistor) at a low potential. In the conventional gate drive circuit, a pull-down circuit that provides a low potential needs to be continuously turned on, resulting in a continuous bias of the thin film transistor. Under continuous high voltage bias operating conditions, thin film transistors may exhibit characteristic drift phenomena (eg, characteristic degradation and/or drift of threshold voltage). The degradation of the characteristics of the thin film transistor will shorten its working life, and the drift of the threshold voltage (Vth) of the transistor will affect the reliability of the gate driving circuit.
要解決這個問題,一些實施例將利用多組下拉電路/元件分擔下拉功能,以降低下拉電路/元件的占空比(duty cycle)。然而,隨著操作時間拉長,這些下拉電路/元件仍會產生臨界電壓漂移的現象。再者,在驅動電路的製作過程中可能會發生製程漂移現象。 製程漂移會改變電晶體的特性,例如使電晶體的臨界電壓發生變異。如何提高驅動電路的可靠度,並有效弭平元件間臨界電壓變異造成的影響,是個必須解決的問題。 To solve this problem, some embodiments will utilize multiple sets of pull-down circuits/components to share the pull-down function to reduce the duty cycle of the pull-down circuit/component. However, as the operating time is lengthened, these pull-down circuits/components still produce a phenomenon of threshold voltage drift. Furthermore, process drift may occur during the fabrication of the driver circuit. Process drift can alter the characteristics of the transistor, such as mutating the threshold voltage of the transistor. How to improve the reliability of the drive circuit and effectively smooth the effects caused by the variation of the threshold voltage between components is a problem that must be solved.
下述諸實施例將說明具元件變異補償之驅動電路及其操作方法。驅動電路可以直接補償元件特性,達到補償下拉開關(例如薄膜電晶體或是其他開關元件)的臨界電壓變異。此驅動電路可以具有臨界電壓補償功能,以提高可靠度與精確性。 The following embodiments will describe a driving circuit with component variation compensation and a method of operating the same. The driver circuit can directly compensate component characteristics to compensate for the threshold voltage variation of the pull-down switch (such as a thin film transistor or other switching element). This driver circuit can have a threshold voltage compensation function to improve reliability and accuracy.
圖1A是依照本揭露一實施例說明一種驅動電路100的電路方塊示意圖。驅動電路100包括上拉(pull-up)開關單元110、隔離開關120、下拉開關單元130以及控制單元140。上拉開關單元110的第一端耦接至第一電壓V1。上拉開關單元110的第二端耦接至驅動電路100的輸出端Vout。隔離開關120的第一端耦接至上拉開關單元110的第二端。下拉開關單元130的第一端耦接至隔離開關120的第二端。下拉開關單元130的第二端耦接至第二電壓V2。上述第一電壓V1與第二電壓V2可以是任何準位的電壓,其中第一電壓V1大於第二電壓V2。舉例來說(但不受限於此),第一電壓V1可以是第一系統電壓(例如系統電壓Vdd或是其他電壓),該第二電壓V2可以是第二系統電壓(例接地電壓Vss或是其他電壓)。在另一實施例中,第一電壓V1可以是時脈信號(clock signal),而第二電壓V2可以是第二系統電壓(例接地電壓Vss或是其他電壓)。在其他實施例中,此第二系統電壓(第二電壓V2)可能是任何大於0V的固定電壓、接地電壓或負電壓。 FIG. 1A is a block diagram showing a circuit of a driving circuit 100 according to an embodiment of the present disclosure. The drive circuit 100 includes a pull-up switch unit 110, an isolation switch 120, a pull-down switch unit 130, and a control unit 140. The first end of the pull-up switch unit 110 is coupled to the first voltage V1. The second end of the pull-up switch unit 110 is coupled to the output terminal Vout of the driving circuit 100. The first end of the isolating switch 120 is coupled to the second end of the pull-up switch unit 110. The first end of the pull-down switch unit 130 is coupled to the second end of the isolating switch 120. The second end of the pull-down switch unit 130 is coupled to the second voltage V2. The first voltage V1 and the second voltage V2 may be voltages of any level, wherein the first voltage V1 is greater than the second voltage V2. For example, but not limited to, the first voltage V1 may be a first system voltage (eg, system voltage Vdd or other voltage), and the second voltage V2 may be a second system voltage (eg, a ground voltage Vss or Is other voltage). In another embodiment, the first voltage V1 may be a clock signal, and the second voltage V2 may be a second system voltage (eg, a ground voltage Vss or other voltage). In other embodiments, this second system voltage (second voltage V2) may be any fixed voltage, ground voltage, or negative voltage greater than 0V.
隔離開關120受控於控制電壓V3。當驅動電路100操作於正常模式時,隔離開關120為導通。當驅動電路100操作於初始化模式時,隔離開關120為截止。 The isolating switch 120 is controlled by a control voltage V3. When the drive circuit 100 operates in the normal mode, the isolation switch 120 is turned on. When the drive circuit 100 is operated in the initialization mode, the isolation switch 120 is turned off.
控制單元140是任何輸入級電路,例如差動輸入對(differential input pair)電路、移位暫存器(shift register)、多工器(multiplexor)或是其他輸入級。控制單元140的輸入端耦接至驅動電路100的輸入端Vin。控制單元140的第一輸出端與第二輸出端分別耦接至上拉開關單元110的控制端與下拉開關單元130的控制端139。於正常模式中,隔離開關120為導通。依據輸入端Vin的準位,控制單元140可以對應控制上拉開關單元110與下拉開關單元130,使其以推挽(Push-pull)方式共同產生輸出端Vout的信號。 Control unit 140 is any input stage circuit, such as a differential input pair circuit, a shift register, a multiplexor, or other input stage. The input end of the control unit 140 is coupled to the input terminal Vin of the driving circuit 100. The first output end and the second output end of the control unit 140 are respectively coupled to the control end of the pull-up switch unit 110 and the control end 139 of the pull-down switch unit 130. In the normal mode, the isolation switch 120 is conductive. According to the level of the input terminal Vin, the control unit 140 can correspondingly control the pull-up switch unit 110 and the pull-down switch unit 130 to jointly generate a signal of the output terminal Vout in a push-pull manner.
當驅動電路100操作於初始化模式時,而下拉開關單元130取樣下拉開關單元130的臨界電壓(threshold voltage,Vth)而獲得下拉臨界電壓值。驅動電路100可以利用下拉開關單元130取樣其內部的下拉開關的臨界電壓。因此,當驅動電路100操作於正常模式時,而下拉開關單元130可以使用該下拉臨界電壓值去補償下拉開關單元130的輸入電壓。 When the driving circuit 100 operates in the initialization mode, the pull-down switching unit 130 samples the threshold voltage (Vth) of the pull-down switching unit 130 to obtain a pull-down threshold voltage value. The drive circuit 100 can sample the threshold voltage of its internal pull-down switch using the pull-down switch unit 130. Therefore, when the driving circuit 100 operates in the normal mode, the pull-down switching unit 130 can use the pull-down threshold voltage value to compensate the input voltage of the pull-down switching unit 130.
在此說明驅動電路100的操作方法。圖1B是依照本揭露一實施例說明一種驅動電路的操作方法流程示意圖。步驟S110可以判斷驅動電路100的操作模式。圖1A與圖1B可以相互參照。當步驟S110判斷驅動電路100操作於初始化模式時,截止隔離開 關120(步驟S120),並且取樣該具補償功能的下拉開關單元130的臨界電壓而獲得第一臨界電壓值(步驟S130)。當步驟S110判斷驅動電路100操作於正常模式時,導通隔離開關120(步驟S140),以及使用該第一臨界電壓值補償該具補償功能的下拉開關單元130的輸入電壓(步驟S150)。 The method of operation of the drive circuit 100 is described herein. FIG. 1B is a schematic flow chart showing an operation method of a driving circuit according to an embodiment of the present disclosure. Step S110 can determine the operation mode of the drive circuit 100. 1A and 1B can be cross-referenced. When it is determined in step S110 that the driving circuit 100 is operated in the initialization mode, the off-isolation is turned on. Off 120 (step S120), and sampling the threshold voltage of the pull-down switch unit 130 with the compensation function to obtain a first threshold voltage value (step S130). When it is determined in step S110 that the driving circuit 100 is operating in the normal mode, the isolation switch 120 is turned on (step S140), and the input voltage of the pull-down switching unit 130 having the compensation function is compensated using the first threshold voltage value (step S150).
圖2是依照本揭露一實施例說明圖1A所示驅動電路100的電路示意圖。於圖2所示實施例中,控制單元140包括第一電晶體141、第二電晶體142、第三電晶體143以及第四電晶體144。第一電晶體141的第一端耦接至第三電壓(第一系統電壓,例如系統電壓Vdd或其他固定電壓)。第一電晶體141的第二端耦接至上拉開關單元110的控制端。第一電晶體141的控制端耦接至驅動電路100的輸入端Vin。第二電晶體142的第一端耦接至第一電晶體141的第二端。第二電晶體142的第二端耦接至第二電壓(第二系統電壓,例如接地電壓Vss或其他固定電壓)。第二電晶體142的控制端耦接至下拉開關單元130的控制端139。第三電晶體143的第一端耦接至第三電壓(例如系統電壓Vdd)。第三電晶體143的第二端耦接至第二電晶體142的控制端與下拉開關單元130的控制端139。第三電晶體143的控制端受控於電壓V4。電壓V4可以是時脈信號(clock signal)或固定準位的偏壓電壓。第四電晶體144的第一端耦接至第三電晶體143的第二端。第四電晶體144的第二端耦接至第二電壓(例如接地電壓Vss)。第四電晶體144的控制端耦接至驅動電路100的輸入端Vin。 FIG. 2 is a schematic circuit diagram of the driving circuit 100 of FIG. 1A according to an embodiment of the present disclosure. In the embodiment shown in FIG. 2, the control unit 140 includes a first transistor 141, a second transistor 142, a third transistor 143, and a fourth transistor 144. The first end of the first transistor 141 is coupled to a third voltage (a first system voltage, such as a system voltage Vdd or other fixed voltage). The second end of the first transistor 141 is coupled to the control end of the pull-up switch unit 110. The control end of the first transistor 141 is coupled to the input terminal Vin of the driving circuit 100. The first end of the second transistor 142 is coupled to the second end of the first transistor 141. The second end of the second transistor 142 is coupled to a second voltage (a second system voltage, such as a ground voltage Vss or other fixed voltage). The control end of the second transistor 142 is coupled to the control terminal 139 of the pull-down switch unit 130. The first end of the third transistor 143 is coupled to a third voltage (eg, system voltage Vdd). The second end of the third transistor 143 is coupled to the control end of the second transistor 142 and the control end 139 of the pull-down switch unit 130. The control terminal of the third transistor 143 is controlled by the voltage V4. The voltage V4 can be a clock signal or a bias voltage of a fixed level. The first end of the fourth transistor 144 is coupled to the second end of the third transistor 143. The second end of the fourth transistor 144 is coupled to a second voltage (eg, a ground voltage Vss). The control terminal of the fourth transistor 144 is coupled to the input terminal Vin of the driving circuit 100.
於圖2所示實施例中,下拉開關單元130包括下拉開關131以及下拉開關補償電路132。下拉開關131的第一端耦接至隔離開關120的第二端。下拉開關131的第二端耦接至第二電壓(第二系統電壓,例如接地電壓Vss或其他固定電壓)。下拉開關補償電路132耦接於下拉開關單元130的控制端139與下拉開關131的控制端之間。當驅動電路100操作於初始化模式(例如圖3所示初始化模式PI)時,下拉開關補償電路132可以取樣下拉開關131的臨界電壓(threshold voltage,Vth)而獲得下拉臨界電壓值。當驅動電路100操作於正常模式(例如圖3所示正常模式PN)時,下拉開關補償電路132使用該下拉臨界電壓值補償下拉開關131的輸入電壓。 In the embodiment shown in FIG. 2, the pull-down switch unit 130 includes a pull-down switch 131 and a pull-down switch compensation circuit 132. The first end of the pull-down switch 131 is coupled to the second end of the isolating switch 120. The second end of the pull-down switch 131 is coupled to a second voltage (a second system voltage, such as a ground voltage Vss or other fixed voltage). The pull-down switch compensation circuit 132 is coupled between the control terminal 139 of the pull-down switch unit 130 and the control terminal of the pull-down switch 131. When the driving circuit 100 operates in an initialization mode (for example, the initialization mode PI shown in FIG. 3), the pull-down switch compensation circuit 132 can sample the threshold voltage (Vth) of the pull-down switch 131 to obtain a pull-down threshold voltage value. When the drive circuit 100 operates in a normal mode (such as the normal mode PN shown in FIG. 3), the pull-down switch compensation circuit 132 compensates the input voltage of the pull-down switch 131 using the pull-down threshold voltage value.
於圖2所示實施例中,下拉開關補償電路132包括電容211、第一開關221、第二開關222以及第三開關223。電容211的第一端與第二端分別耦接於下拉開關單元130的控制端139與下拉開關131的控制端。第一開關221的第一端與第二端分別耦接於第三電壓(例如系統電壓Vdd)與電容211的第二端。第二開關222的第一端與第二端分別耦接於電容211的第二端與下拉開關131的第一端。第三開關223的第一端與第二端分別耦接於電容211的第一端與下拉開關131的第二端。 In the embodiment shown in FIG. 2, the pull-down switch compensation circuit 132 includes a capacitor 211, a first switch 221, a second switch 222, and a third switch 223. The first end and the second end of the capacitor 211 are respectively coupled to the control end 139 of the pull-down switch unit 130 and the control end of the pull-down switch 131. The first end and the second end of the first switch 221 are respectively coupled to a third voltage (eg, system voltage Vdd) and a second end of the capacitor 211. The first end and the second end of the second switch 222 are respectively coupled to the second end of the capacitor 211 and the first end of the pull-down switch 131. The first end and the second end of the third switch 223 are respectively coupled to the first end of the capacitor 211 and the second end of the pull-down switch 131.
圖3是依照本揭露一實施例說明圖2所示控制信號之時序示意圖。圖3所示初始化模式PI可以在正常模式PN之前進行。在其他實施例中,初始化模式PI可在每個訊框(Frame)的Vin 啟動之前進行。請參照圖2與圖3,當驅動電路100操作於初始化模式PI時,控制電壓V3使隔離開關120截止。於初始化模式PI的充電期間P1,控制信號V5與V7分別使第一開關221與第三開關223導通,以及控制信號V6使第二開關222截止。因此於充電期間P1,導通的第一開關221與第三開關223可以使電容211的第一端與第二端分別耦接下拉開關131的第二端與第三電壓(例如系統電壓Vdd)。此時,系統電壓Vdd與下拉開關131的第二端的電位差被儲存於電容211。 FIG. 3 is a timing diagram illustrating the control signal shown in FIG. 2 according to an embodiment of the present disclosure. The initialization mode PI shown in Fig. 3 can be performed before the normal mode PN. In other embodiments, the initialization mode PI can be in each frame (Frame) of Vin Do it before starting. Referring to FIG. 2 and FIG. 3, when the driving circuit 100 operates in the initialization mode PI, the control voltage V3 turns off the isolation switch 120. In the charging period P1 of the initialization mode PI, the control signals V5 and V7 respectively turn on the first switch 221 and the third switch 223, and the control signal V6 turns off the second switch 222. Therefore, during the charging period P1, the first switch 221 and the third switch 223 that are turned on can respectively couple the first end and the second end of the capacitor 211 to the second end of the pull-down switch 131 and the third voltage (for example, the system voltage Vdd). At this time, the potential difference between the system voltage Vdd and the second end of the pull-down switch 131 is stored in the capacitor 211.
於初始化模式PI的放電期間P2,控制信號V6與V7分別使第二開關222與第三開關223導通,以及控制信號V5使第一開關221截止。因此於放電期間P2,導通的第三開關223可以使電容211的第一端耦接下拉開關131的第二端,以及導通的第二開關222可以使該電容211的第二端耦接下拉開關131的第一端。此時,下拉開關131被接成二極體形式的電晶體(diode-connected transistor),使得電容211放電。電容211的電荷經由第二開關222與下拉開關131放電至接地電壓Vss,直到下拉開關131的閘極-源極電壓約略等於下拉開關131的臨界電壓(threshold voltage,Vth)。因此,下拉開關131的臨界電壓可以被儲存於電容211。也就是說,若下拉開關單元130的控制端139的電壓為Vp2,下拉開關131的控制端的電壓為Vc1,下拉開關131的臨界電壓為Vth1,則電容211的兩端壓差為Vc1-Vp2=Vth1。 During the discharge period P2 of the initialization mode PI, the control signals V6 and V7 respectively turn on the second switch 222 and the third switch 223, and the control signal V5 turns off the first switch 221. Therefore, during the discharge period P2, the third switch 223 that is turned on can couple the first end of the capacitor 211 to the second end of the pull-down switch 131, and the second switch 222 that is turned on can couple the second end of the capacitor 211 to the pull-down switch. The first end of 131. At this time, the pull-down switch 131 is connected to a diode-connected transistor, so that the capacitor 211 is discharged. The charge of the capacitor 211 is discharged to the ground voltage Vss via the second switch 222 and the pull-down switch 131 until the gate-source voltage of the pull-down switch 131 is approximately equal to the threshold voltage (Vth) of the pull-down switch 131. Therefore, the threshold voltage of the pull-down switch 131 can be stored in the capacitor 211. That is, if the voltage of the control terminal 139 of the pull-down switch unit 130 is V p2 , the voltage of the control terminal of the pull-down switch 131 is V c1 , and the threshold voltage of the pull-down switch 131 is V th1 , the voltage difference between the two ends of the capacitor 211 is V C1 -V p2 =V th1 .
當驅動電路100操作於正常模式PN時,控制電壓V3使 隔離開關120為導通。此時,下拉開關131的汲極電流Id=K(Vc1-Vth1)2=K[(Vp2+Vth1)-Vth1]2=K(Vp2)2,其中K為常數。因此,圖2所示驅動電路100可以改善/消除下拉開關131的下拉臨界電壓值Vth1的變異影響。也就是說,圖2所示下拉開關補償電路132可以於初始化模式PI取樣下拉開關131的下拉臨界電壓值Vth1,然後在正常模式PN時使用下拉臨界電壓值Vth1去補償下拉開關單元130的輸入電壓(下拉開關131的控制端電壓Vc1)。 When the drive circuit 100 operates in the normal mode PN, the control voltage V3 causes the isolation switch 120 to be turned on. At this time, the drain current I d of the pull-down switch 131 = K (V c1 - V th1 ) 2 = K [(V p2 + V th1 ) - V th1 ] 2 = K (V p2 ) 2 , where K is a constant. Therefore, the driving circuit 100 shown in FIG. 2 can improve/eliminate the variation effect of the pull-down threshold voltage value V th1 of the pull-down switch 131. That is, the pull-down switch compensation circuit 132 shown in FIG. 2 can sample the pull-down threshold voltage value V th1 of the pull-down switch 131 in the initialization mode PI, and then use the pull-down threshold voltage value V th1 to compensate the pull-down switch unit 130 in the normal mode PN. The input voltage (the control terminal voltage V c1 of the pull-down switch 131).
圖1A所示驅動電路100的實施方式不應受限於圖2所示方式。例如,圖4是依照本揭露另一實施例說明圖1A所示驅動電路100的電路示意圖。圖4所示實施例可以參照圖2與圖3的相關說明而類推之。於圖4所示實施例中,驅動電路100還包括輸出下拉開關450。輸出下拉開關450的第一端耦接至驅動電路100的輸出端Vout。輸出下拉開關450的第二端耦接至第二電壓(第二系統電壓,例如接地電壓Vss或是其他固定電壓)。輸出下拉開關450受控於控制電壓V0。當驅動電路100操作於初始化模式PI時,輸出下拉開關450為導通,以將驅動電路100的輸出端Vout的電壓下拉至第二電壓(例如接地電壓Vss)。因此,於初始化模式PI中輸出下拉開關450可以確保驅動電路100的輸出端Vout的電壓保持於低邏輯準位。當驅動電路100操作於正常模式PN時,輸出下拉開關450為截止,以避免影響驅動電路100的正常操作。 The embodiment of the drive circuit 100 shown in FIG. 1A should not be limited to the manner shown in FIG. 2. For example, FIG. 4 is a circuit diagram illustrating the driving circuit 100 of FIG. 1A according to another embodiment of the present disclosure. The embodiment shown in FIG. 4 can be analogized with reference to the related description of FIG. 2 and FIG. 3. In the embodiment shown in FIG. 4, the drive circuit 100 further includes an output pull-down switch 450. The first end of the output pull-down switch 450 is coupled to the output terminal Vout of the driving circuit 100. The second end of the output pull-down switch 450 is coupled to a second voltage (a second system voltage, such as a ground voltage Vss or other fixed voltage). The output pull-down switch 450 is controlled by the control voltage V0. When the driving circuit 100 operates in the initialization mode PI, the output pull-down switch 450 is turned on to pull the voltage of the output terminal Vout of the driving circuit 100 to a second voltage (for example, the ground voltage Vss). Therefore, outputting the pull-down switch 450 in the initialization mode PI can ensure that the voltage of the output terminal Vout of the driving circuit 100 is maintained at a low logic level. When the drive circuit 100 operates in the normal mode PN, the output pull-down switch 450 is turned off to avoid affecting the normal operation of the drive circuit 100.
於圖4所示實施例中,下拉開關單元130包括下拉開關 131以及下拉開關補償電路133。下拉開關補償電路133包括電容211、第一開關221、第二開關222以及第三開關224。電容211的第一端與第二端分別耦接於下拉開關單元130的控制端139與下拉開關131的控制端。第一開關221的第一端與第二端分別耦接於第三電壓(第一系統電壓,例如系統電壓Vdd或是其他固定電壓)與電容211的第二端。第二開關222的第一端與第二端分別耦接於電容211的第二端與下拉開關131的第一端。第三開關224的第一端與第二端分別耦接於電容211的第一端與第四電壓(第二系統電壓,例如接地電壓Vss或是其他固定電壓)。 In the embodiment shown in FIG. 4, the pull-down switch unit 130 includes a pull-down switch. 131 and pull-down switch compensation circuit 133. The pull-down switch compensation circuit 133 includes a capacitor 211, a first switch 221, a second switch 222, and a third switch 224. The first end and the second end of the capacitor 211 are respectively coupled to the control end 139 of the pull-down switch unit 130 and the control end of the pull-down switch 131. The first end and the second end of the first switch 221 are respectively coupled to a third voltage (a first system voltage, such as a system voltage Vdd or other fixed voltage) and a second end of the capacitor 211. The first end and the second end of the second switch 222 are respectively coupled to the second end of the capacitor 211 and the first end of the pull-down switch 131. The first end and the second end of the third switch 224 are respectively coupled to the first end of the capacitor 211 and the fourth voltage (the second system voltage, such as the ground voltage Vss or other fixed voltage).
當驅動電路100操作於初始化模式PI時,控制電壓V3使隔離開關120截止。於初始化模式PI的充電期間P1,控制信號V5與V7分別使第一開關221與第三開關224導通,以及控制信號V6使第二開關222截止。因此於充電期間P1,導通的第一開關221與第三開關224可以使電容211的第二端與第一端分別耦接第三電壓(例如系統電壓Vdd)與第四電壓(例如接地電壓Vss)。此時,系統電壓Vdd與接地電壓Vss的電位差被儲存於電容211。 When the drive circuit 100 operates in the initialization mode PI, the control voltage V3 turns off the isolation switch 120. In the charging period P1 of the initialization mode PI, the control signals V5 and V7 respectively turn on the first switch 221 and the third switch 224, and the control signal V6 turns off the second switch 222. Therefore, during the charging period P1, the first switch 221 and the third switch 224 that are turned on can couple the second end of the capacitor 211 and the first end to a third voltage (eg, system voltage Vdd) and a fourth voltage (eg, ground voltage Vss). ). At this time, the potential difference between the system voltage Vdd and the ground voltage Vss is stored in the capacitor 211.
於初始化模式PI的放電期間P2,控制信號V6與V7分別使第二開關222與第三開關224導通,以及控制信號V5使第一開關221截止。因此於放電期間P2,導通的第三開關224可以使電容211的第一端耦接第四電壓(例如接地電壓Vss),以及導通的第二開關222可以使電容211的第二端耦接下拉開關131的第 一端。此時,下拉開關131被接成二極體形式的電晶體,使得電容211放電。因此,下拉開關131的臨界電壓可以被儲存於電容211。也就是說,電容211的兩端壓差為Vc1-Vp2=Vth1。 During the discharge period P2 of the initialization mode PI, the control signals V6 and V7 respectively turn on the second switch 222 and the third switch 224, and the control signal V5 turns off the first switch 221. Therefore, during the discharge period P2, the turned-on third switch 224 can couple the first end of the capacitor 211 to the fourth voltage (eg, the ground voltage Vss), and the turned-on second switch 222 can couple the second end of the capacitor 211 to the pull-down. The first end of the switch 131. At this time, the pull-down switch 131 is connected to a transistor in the form of a diode, so that the capacitor 211 is discharged. Therefore, the threshold voltage of the pull-down switch 131 can be stored in the capacitor 211. That is, the voltage difference across the capacitor 211 is V c1 - V p2 = V th1 .
當驅動電路100操作於正常模式PN時,控制電壓V3使隔離開關120為導通。此時,下拉開關131的汲極電流Id=K(Vc1-Vth1)2=K[(Vp2+Vth1)-Vth1]2=K(Vp2)2,其中K為常數。因此,圖4所示驅動電路100可以改善/消除下拉開關131的下拉臨界電壓值Vth1的變異影響。 When the drive circuit 100 operates in the normal mode PN, the control voltage V3 causes the isolation switch 120 to be turned on. At this time, the drain current I d of the pull-down switch 131 = K (V c1 - V th1 ) 2 = K [(V p2 + V th1 ) - V th1 ] 2 = K (V p2 ) 2 , where K is a constant. Therefore, the driving circuit 100 shown in FIG. 4 can improve/eliminate the variation effect of the pull-down threshold voltage value V th1 of the pull-down switch 131.
圖5是依照本揭露另一實施例說明一種驅動電路500的電路方塊示意圖。驅動電路500包括上拉開關單元110、隔離開關120、下拉開關單元130、控制單元140以及隔離開關補償電路560。圖5所示上拉開關單元110、隔離開關120、下拉開關單元130與控制單元140可以參照圖1A至圖4的相關說明而類推之,故不再贅述。 FIG. 5 is a block diagram showing a circuit of a driving circuit 500 according to another embodiment of the disclosure. The driving circuit 500 includes a pull-up switch unit 110, an isolation switch 120, a pull-down switch unit 130, a control unit 140, and an isolation switch compensation circuit 560. The pull-up switch unit 110, the isolating switch 120, the pull-down switch unit 130 and the control unit 140 shown in FIG. 5 can be analogized with reference to the related description of FIG. 1A to FIG. 4, and therefore will not be described again.
於圖5所示實施例中,隔離開關補償電路560耦接於隔離開關120的控制端。當驅動電路500操作於初始化模式時,隔離開關補償電路560可以取樣隔離開關120的臨界電壓而獲得隔離臨界電壓值Vth2。當驅動電路500操作於正常模式時,隔離開關補償電路560可以使用該隔離臨界電壓值Vth2補償隔離開關120的輸入電壓。因此,當驅動電路500操作於正常模式時,除了下拉開關單元130可以使用下拉臨界電壓值Vth1去補償下拉開關單元130的輸入電壓之外,隔離開關補償電路560亦可以使用隔離 臨界電壓值Vth2去補償隔離開關120的輸入電壓。 In the embodiment shown in FIG. 5, the isolating switch compensation circuit 560 is coupled to the control terminal of the isolating switch 120. When the driving circuit 500 operates in the initialization mode, the isolation switch compensation circuit 560 can sample the threshold voltage of the isolation switch 120 to obtain the isolation threshold voltage value V th2 . When the drive circuit 500 operates in the normal mode, the isolation switch compensation circuit 560 can compensate the input voltage of the isolation switch 120 using the isolation threshold voltage value Vth2 . Therefore, when the driving circuit 500 operates in the normal mode, the isolation switch compensation circuit 560 can also use the isolation threshold voltage value V except that the pull-down switching unit 130 can use the pull-down threshold voltage value V th1 to compensate the input voltage of the pull-down switching unit 130. Th2 goes to compensate for the input voltage of the isolating switch 120.
圖6是依照本揭露一實施例說明圖5所示驅動電路500的電路示意圖。圖6所示驅動電路500包括上拉開關單元110、隔離開關120、下拉開關單元130、控制單元140、輸出下拉開關450以及隔離開關補償電路560。下拉開關單元130與控制單元140可以參照圖2至圖3的相關說明而類推之,而圖6所示輸出下拉開關450可以參照圖4的相關說明而類推之,故不再贅述。於圖6所示實施例中,下拉開關單元130包括下拉開關131以及下拉開關補償電路132。在另一實施例中,圖6所示下拉開關補償電路132可能被置換為圖4所示下拉開關補償電路133。 FIG. 6 is a circuit diagram illustrating the driving circuit 500 of FIG. 5 according to an embodiment of the present disclosure. The driving circuit 500 shown in FIG. 6 includes a pull-up switch unit 110, an isolation switch 120, a pull-down switch unit 130, a control unit 140, an output pull-down switch 450, and an isolation switch compensation circuit 560. The pull-down switch unit 130 and the control unit 140 can be analogized with reference to the related description of FIG. 2 to FIG. 3, and the output pull-down switch 450 shown in FIG. 6 can be analogized with reference to the related description of FIG. 4, and therefore will not be described again. In the embodiment shown in FIG. 6, the pull-down switch unit 130 includes a pull-down switch 131 and a pull-down switch compensation circuit 132. In another embodiment, the pull-down switch compensation circuit 132 shown in FIG. 6 may be replaced with the pull-down switch compensation circuit 133 shown in FIG.
於圖6所示實施例中,隔離開關補償電路560包括電容561、第一開關562、第二開關563以及第三開關564。電容561的第一端與第二端分別耦接於控制電壓V3與隔離開關120的控制端。第一開關562的第一端與第二端分別耦接於第一參考電壓(第二系統電壓,例如接地電壓Vss或其他固定電壓)與電容561的第二端。第二開關563的第一端與第二端分別耦接於電容561的第二端與隔離開關120的第一端。第三開關564的第一端與第二端分別耦接於電容561的第一端與隔離開關120的第二端。 In the embodiment shown in FIG. 6, the isolation switch compensation circuit 560 includes a capacitor 561, a first switch 562, a second switch 563, and a third switch 564. The first end and the second end of the capacitor 561 are respectively coupled to the control voltage V3 and the control end of the isolating switch 120. The first end and the second end of the first switch 562 are respectively coupled to a first reference voltage (a second system voltage, such as a ground voltage Vss or other fixed voltage) and a second end of the capacitor 561. The first end and the second end of the second switch 563 are respectively coupled to the second end of the capacitor 561 and the first end of the isolating switch 120. The first end and the second end of the third switch 564 are respectively coupled to the first end of the capacitor 561 and the second end of the isolating switch 120.
圖7是依照本揭露一實施例說明圖6所示控制信號之時序示意圖。圖7所示初始化模式PI可以在正常模式PN之前進行。在其他實施例中,初始化模式PI可在每個訊框(Frame)的Vin啟動之前進行。圖7所示實施例可以參照圖3的相關說明而類推 之。請參照圖6與圖7,當驅動電路500操作於初始化模式PI的第一期間PI1時,隔離開關補償電路560可以取樣隔離開關120的臨界電壓而獲得隔離臨界電壓值Vth2。當驅動電路500操作於初始化模式PI的第二期間PI2時,下拉開關補償電路132可以取樣下拉開關131的臨界電壓而獲得下拉臨界電壓值Vth1。當驅動電路500操作於正常模式PN時,下拉開關補償電路132可以使用下拉臨界電壓值Vth1補償下拉開關131的輸入電壓,而隔離開關補償電路560可以使用隔離臨界電壓值Vth2補償隔離開關120的輸入電壓。關於初始化模式PI的第二期間PI2的操作細節與正常模式PN的操作細節,請參照圖2至圖4所述初始化模式PI與正常模式PN的相關說明而類推之,故不再贅述。 FIG. 7 is a timing diagram illustrating the control signal shown in FIG. 6 according to an embodiment of the present disclosure. The initialization mode PI shown in Fig. 7 can be performed before the normal mode PN. In other embodiments, the initialization mode PI can be performed before the Vin of each frame (Frame) is started. The embodiment shown in FIG. 7 can be analogized with reference to the related description of FIG. Referring to FIG. 6 and FIG. 7, when the driving circuit 500 operates in the first period PI1 of the initialization mode PI, the isolation switch compensation circuit 560 can sample the threshold voltage of the isolation switch 120 to obtain the isolation threshold voltage value V th2 . When the driving circuit 500 operates in the second period PI2 of the initialization mode PI, the pull-down switch compensation circuit 132 can sample the threshold voltage of the pull-down switch 131 to obtain the pull-down threshold voltage value V th1 . When the driving circuit 500 operates in the normal mode PN, the pull-down switch compensation circuit 132 can compensate the input voltage of the pull-down switch 131 using the pull-down threshold voltage value V th1 , and the isolation switch compensation circuit 560 can compensate the isolation switch 120 using the isolation threshold voltage value V th2 . Input voltage. Regarding the operation details of the second period PI2 of the initialization mode PI and the operation details of the normal mode PN, please refer to the descriptions of the initialization mode PI and the normal mode PN described with reference to FIGS. 2 to 4, and thus will not be described again.
請參照圖6與圖7,於初始化模式PI的第一期間PI1的充電期間P3,控制信號V8與V10分別使第一開關562與第三開關564導通,以及控制信號V9使第二開關563截止。因此於充電期間P3,導通的第一開關562與第三開關564可以使電容561的第二端與第一端分別耦接第一參考電壓(第二系統電壓,例如接地電壓Vss或是其他固定電壓)與第二參考電壓(例如由控制電壓V3所提供的負系統電壓,-Vdd)。此時,接地電壓Vss與負系統電壓-Vdd的電位差被儲存於電容561。 Referring to FIG. 6 and FIG. 7, in the charging period P3 of the first period PI1 of the initialization mode PI, the control signals V8 and V10 respectively turn on the first switch 562 and the third switch 564, and the control signal V9 turns off the second switch 563. . Therefore, during the charging period P3, the first switch 562 and the third switch 564 that are turned on can respectively couple the second end of the capacitor 561 and the first end to the first reference voltage (the second system voltage, such as the ground voltage Vss or other fixed Voltage) and a second reference voltage (eg, a negative system voltage provided by control voltage V3, -Vdd). At this time, the potential difference between the ground voltage Vss and the negative system voltage -Vdd is stored in the capacitor 561.
於初始化模式PI的第一期間PI1的放電期間P4,控制信號V9與V10分別使第二開關563與第三開關564導通,以及控制信號V8使第一開關562截止。因此於放電期間P4,導通的第 三開關564可以使電容561的第一端耦接隔離開關120的第二端,以及導通的第二開關563可以使電容561的第二端耦接隔離開關120的第一端。此時,隔離開關120被接成二極體形式的電晶體(diode-connected transistor),使得電容561放電。電容561的電荷經由第二開關563與隔離開關120放電至負系統電壓-Vdd,直到隔離開關120的閘極-源極電壓約略等於隔離開關120的臨界電壓Vth2。因此,隔離開關120的隔離臨界電壓值Vth2可以被儲存於電容561。也就是說,若下拉開關131的控制端的電壓為Vc2,則電容561的兩端壓差為Vc2-V3=Vth2。 During the discharge period P4 of the first period PI1 of the initialization mode PI, the control signals V9 and V10 respectively turn on the second switch 563 and the third switch 564, and the control signal V8 turns off the first switch 562. Therefore, during the discharge period P4, the third switch 564 that is turned on can couple the first end of the capacitor 561 to the second end of the isolating switch 120, and the second switch 563 that is turned on can couple the second end of the capacitor 561 to the isolating switch 120. The first end. At this time, the isolation switch 120 is connected to a diode-connected transistor, so that the capacitor 561 is discharged. The charge of the capacitor 561 is discharged to the negative system voltage -Vdd via the second switch 563 and the isolation switch 120 until the gate-source voltage of the isolation switch 120 is approximately equal to the threshold voltage Vth2 of the isolation switch 120. Therefore, the isolation threshold voltage value V th2 of the isolation switch 120 can be stored in the capacitor 561. That is, if the voltage at the control terminal of the pull-down switch 131 is V c2 , the voltage difference across the capacitor 561 is V c2 - V3 = V th2 .
當驅動電路500操作於正常模式PN時,控制電壓V3使隔離開關120為導通。隔離開關120的汲極電流Id=K(Vc2-Vth2)2=K[(V3+Vth2)-Vth2]2=K(V3)2,其中K為常數。因此,圖6所示驅動電路500可以改善/消除隔離開關120的隔離臨界電壓值Vth2的變異影響。此外,下拉開關131的汲極電流Id=K(Vc1-Vth1)2=K[(Vp2+Vth1)-Vth1]2=K(Vp2)2,其中K為常數。因此,圖6所示驅動電路100可以改善/消除下拉開關131的下拉臨界電壓值Vth1的變異影響。也就是說,圖2所示隔離開關補償電路560與下拉開關補償電路132可以於初始化模式PI分別取樣隔離開關120的隔離臨界電壓值Vth2與下拉開關131的下拉臨界電壓值Vth1,然後在正常模式PN時使用隔離臨界電壓值Vth2與下拉臨界電壓值Vth1去分別補償隔離開關120的輸入電壓與下拉開關單元130的輸入電壓。 When the drive circuit 500 operates in the normal mode PN, the control voltage V3 causes the isolation switch 120 to be turned on. Drain current isolation switch 120 I d = K (V c2 -V th2) 2 = K [(V3 + V th2) -V th2] 2 = K (V3) 2, where K is a constant. Therefore, the driving circuit 500 shown in FIG. 6 can improve/eliminate the variation effect of the isolation threshold voltage value V th2 of the isolation switch 120. Further, the drain current I d of the pull-down switch 131 = K (V c1 - V th1 ) 2 = K [(V p2 + V th1 ) - V th1 ] 2 = K(V p2 ) 2 , where K is a constant. Therefore, the driving circuit 100 shown in FIG. 6 can improve/eliminate the variation effect of the pull-down threshold voltage value V th1 of the pull-down switch 131. That is, the isolation switch compensation circuit 560 and the pull-down switch compensation circuit 132 shown in FIG. 2 can respectively sample the isolation threshold voltage value V th2 of the isolation switch 120 and the pull-down threshold voltage value V th1 of the pull-down switch 131 in the initialization mode PI, and then In the normal mode PN, the isolation threshold voltage value V th2 and the pull-down threshold voltage value V th1 are used to compensate the input voltage of the isolation switch 120 and the input voltage of the pull-down switch unit 130, respectively.
圖5所示驅動電路500的實施方式不應受限於圖6所示方式。例如,圖8是依照本揭露另一實施例說明圖5所示驅動電路500的電路示意圖。圖8所示實施例可以參照圖6與圖7的相關說明而類推之。於圖8所示實施例中,隔離開關補償電路560包括第一電容565、第二電容561、第一開關562、第二開關563、第三開關564以及第四開關566。第一電容565的第一端耦接於控制電壓V3。第二電容561的第一端與第二端分別耦接於第一電容565的第二端與隔離開關120的控制端。第一開關562的第一端與第二端分別耦接於參考電壓(第二系統電壓,例如接地電壓Vss或是其他固定電壓)與第二電容561的第二端。第二開關563的第一端與第二端分別耦接於第二電容561的第二端與隔離開關120的第一端。第三開關564的第一端與第二端分別耦接於第二電容561的第一端與隔離開關120的第二端。第四開關566的第一端與第二端分別耦接於第一電容565的第一端與第二端。 The embodiment of the drive circuit 500 shown in FIG. 5 should not be limited to the manner shown in FIG. For example, FIG. 8 is a circuit diagram illustrating the driving circuit 500 of FIG. 5 according to another embodiment of the present disclosure. The embodiment shown in FIG. 8 can be analogized with reference to the related description of FIG. 6 and FIG. In the embodiment shown in FIG. 8 , the isolation switch compensation circuit 560 includes a first capacitor 565 , a second capacitor 561 , a first switch 562 , a second switch 563 , a third switch 564 , and a fourth switch 566 . The first end of the first capacitor 565 is coupled to the control voltage V3. The first end and the second end of the second capacitor 561 are respectively coupled to the second end of the first capacitor 565 and the control end of the isolating switch 120. The first end and the second end of the first switch 562 are respectively coupled to a reference voltage (a second system voltage, such as a ground voltage Vss or other fixed voltage) and a second end of the second capacitor 561. The first end and the second end of the second switch 563 are respectively coupled to the second end of the second capacitor 561 and the first end of the isolating switch 120. The first end and the second end of the third switch 564 are respectively coupled to the first end of the second capacitor 561 and the second end of the isolating switch 120. The first end and the second end of the fourth switch 566 are respectively coupled to the first end and the second end of the first capacitor 565.
圖9是依照本揭露一實施例說明圖8所示控制信號之時序示意圖。圖9所示實施例可以參照圖7的相關說明而類推之,故不再贅述。請參照圖8與圖9,於初始化模式PI的第一期間PI1的充電期間P3,控制信號V11使第四開關566截止。於初始化模式PI的第一期間PI1的放電期間P4,控制信號V11使第四開關566導通。因此由控制電壓V3所提供的負系統電壓-Vdd可以被傳送至第二電容561的第一端。於充電期間P3,第二電容561的第二端與第一端分別耦接第一參考電壓(第二系統電壓,例如接地 電壓Vss或是其他固定電壓)與第二參考電壓(例如負系統電壓-Vdd)。於放電期間P4,第二電容561的第一端耦接隔離開關120的第二端,以及第二電容561的第二端耦接隔離開關120的第一端(此時為第二系統電壓,例如大於0V的固定電壓、接地電壓Vss或負的固定電壓)與隔離開關120的控制端。放電期間P4結束後,第二電容561的兩端壓差為Vc2-V3=Vth2。當驅動電路500操作於正常模式PN時,隔離開關120的汲極電流Id=K(Vc2-Vth2)2=K[(V3+Vth2)-Vth2]2=K(V3)2,其中K為常數。因此,圖8所示驅動電路500可以改善/消除隔離開關120的隔離臨界電壓值Vth2的變異影響。 FIG. 9 is a timing diagram illustrating the control signal shown in FIG. 8 according to an embodiment of the present disclosure. The embodiment shown in FIG. 9 can be analogized with reference to the related description of FIG. 7, and therefore will not be described again. Referring to FIGS. 8 and 9, the control signal V11 turns off the fourth switch 566 during the charging period P3 of the first period PI1 of the initialization mode PI. The control signal V11 turns on the fourth switch 566 during the discharge period P4 of the first period PI1 of the initialization mode PI. Therefore, the negative system voltage -Vdd provided by the control voltage V3 can be transmitted to the first terminal of the second capacitor 561. During the charging period P3, the second end and the first end of the second capacitor 561 are respectively coupled to the first reference voltage (the second system voltage, such as the ground voltage Vss or other fixed voltage) and the second reference voltage (eg, the negative system voltage). -Vdd). During the discharge period P4, the first end of the second capacitor 561 is coupled to the second end of the isolating switch 120, and the second end of the second capacitor 561 is coupled to the first end of the isolating switch 120 (at this time, the second system voltage, For example, a fixed voltage greater than 0V, a ground voltage Vss or a negative fixed voltage) and a control terminal of the isolating switch 120. After the end of the discharge period P4, the voltage difference across the second capacitor 561 is V c2 - V3 = V th2 . When the driving circuit 500 PN normal mode of operation, the drain current of the isolation switch 120 I d = K (V c2 -V th2) 2 = K [(V3 + V th2) -V th2] 2 = K (V3) 2 , where K is a constant. Therefore, the driving circuit 500 shown in FIG. 8 can improve/eliminate the variation effect of the isolation threshold voltage value V th2 of the isolation switch 120.
圖10是依照本揭露又一實施例說明圖5所示驅動電路500的電路示意圖。於圖10所示實施例中,隔離開關補償電路560包括第一電容565、第二電容561、第一開關562、第三開關564以及第四開關566。圖10所示實施例可以參照圖8與圖9的相關說明而類推之,故不再贅述。不同於圖8所示實施例之處,在於圖10所示實施例省略了圖8所示第二開關563。 FIG. 10 is a circuit diagram illustrating the driving circuit 500 of FIG. 5 according to still another embodiment of the present disclosure. In the embodiment shown in FIG. 10, the isolation switch compensation circuit 560 includes a first capacitor 565, a second capacitor 561, a first switch 562, a third switch 564, and a fourth switch 566. The embodiment shown in FIG. 10 can be analogized with reference to the related descriptions of FIG. 8 and FIG. 9, and therefore will not be described again. Different from the embodiment shown in FIG. 8, the second switch 563 shown in FIG. 8 is omitted in the embodiment shown in FIG.
請參照圖9與圖10,於先前操作中,第四開關566曾經將第一電容565的兩端短路,使得第一電容565的兩端電壓差為0。於初始化模式PI的第一期間PI1的充電期間P3,控制信號V11使第四開關566截止,控制信號V8與V10使第一開關562與第三開關564導通,而控制電壓V3被下拉至負系統電壓-Vdd。負系統電壓-Vdd會經由第一電容565而施加於第二電容561的第一 端。接地電壓Vss會經由第一開關562而施加於第二電容561的第二端。因此,第二電容561會被充電,使得第一電容565的兩端電壓差約略為Vdd。此時,因為隔離開關120的閘源極電壓(閘極與源極的電壓差)大於隔離開關120的隔離臨界電壓值Vth2,使得隔離開關120為導通。因為第三開關564、隔離開關120與輸出下拉開關450為導通,使得第二電容561發生放電而降低了第二電容561的兩端電壓差,也就是降低隔離開關120的閘源極電壓。當隔離開關120的閘源極電壓不大於隔離臨界電壓值Vth2時,隔離開關120為截止,使得第二電容561停止放電。至此,隔離開關120的隔離臨界電壓值Vth2便被取樣/保存至第二電容561中。 Referring to FIG. 9 and FIG. 10, in the previous operation, the fourth switch 566 once short-circuits both ends of the first capacitor 565 such that the voltage difference across the first capacitor 565 is zero. During the charging period P3 of the first period PI1 of the initialization mode PI, the control signal V11 turns off the fourth switch 566, the control signals V8 and V10 turn on the first switch 562 and the third switch 564, and the control voltage V3 is pulled down to the negative system. Voltage - Vdd. The negative system voltage -Vdd is applied to the first terminal of the second capacitor 561 via the first capacitor 565. The ground voltage Vss is applied to the second end of the second capacitor 561 via the first switch 562. Therefore, the second capacitor 561 is charged such that the voltage difference across the first capacitor 565 is approximately Vdd. At this time, since the gate-source voltage (the voltage difference between the gate and the source) of the isolation switch 120 is greater than the isolation threshold voltage value V th2 of the isolation switch 120, the isolation switch 120 is turned on. Because the third switch 564, the isolating switch 120 and the output pull-down switch 450 are turned on, the second capacitor 561 is discharged to reduce the voltage difference between the two ends of the second capacitor 561, that is, the gate-source voltage of the isolating switch 120 is lowered. When the gate-source voltage of the isolation switch 120 is not greater than the isolation threshold voltage value V th2 , the isolation switch 120 is turned off, so that the second capacitor 561 stops discharging. At this point, the isolation threshold voltage value V th2 of the isolation switch 120 is sampled/saved into the second capacitor 561.
於初始化模式PI的第一期間PI1的放電期間P4,控制信號V8與V10使第一開關562與第三開關564截止,以便將隔離臨界電壓值Vth2保存於第二電容561中。控制信號V11使第四開關566導通,因此可以將第一電容565的兩端電壓差重置為0。放電期間P4結束後,第二電容561的兩端壓差為Vth2。當驅動電路500操作於正常模式PN時,隔離開關120的汲極電流Id=K(Vc2-Vth2)2=K[(V3+Vth2)-Vth2]2=K(V3)2,其中K為常數。因此,圖10所示驅動電路500可以改善/消除隔離開關120的隔離臨界電壓值Vth2的變異影響。 During the discharge period P4 of the first period PI1 of the initialization mode PI, the control signals V8 and V10 turn off the first switch 562 and the third switch 564 to store the isolation threshold voltage value Vth2 in the second capacitor 561. The control signal V11 turns on the fourth switch 566, so the voltage difference across the first capacitor 565 can be reset to zero. After the end of the discharge period P4, the voltage difference across the second capacitor 561 is V th2 . When the driving circuit 500 PN normal mode of operation, the drain current of the isolation switch 120 I d = K (V c2 -V th2) 2 = K [(V3 + V th2) -V th2] 2 = K (V3) 2 , where K is a constant. Therefore, the driving circuit 500 shown in FIG. 10 can improve/eliminate the variation effect of the isolation threshold voltage value V th2 of the isolation switch 120.
綜上所述,上述諸實施例所述驅動電路及其操作方法可以利用下拉開關單元130取樣其內部的下拉開關131的臨界電壓。當驅動電路操作於正常模式時,下拉開關單元130可以依據 經取樣的臨界電壓去補償下拉開關單元130的輸入電壓。因此,本揭露實施例所述驅動電路及其操作方法可以補償元件的臨界電壓變異。 In summary, the driving circuit and the operating method thereof according to the above embodiments can use the pull-down switch unit 130 to sample the threshold voltage of the internal pull-down switch 131. When the driving circuit operates in the normal mode, the pull-down switch unit 130 can be based on The sampled threshold voltage is used to compensate for the input voltage of the pull-down switch unit 130. Therefore, the driving circuit and the operating method thereof according to the embodiments of the present disclosure can compensate for the threshold voltage variation of the component.
雖然本揭露已以實施例揭露如上,然其並非用以限定本揭露,任何所屬技術領域中具有通常知識者,在不脫離本揭露的精神和範圍內,當可作些許的更動與潤飾,故本揭露的保護範圍當視後附的申請專利範圍所界定者為準。 The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make some changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of this disclosure is subject to the definition of the scope of the appended claims.
100‧‧‧驅動電路 100‧‧‧ drive circuit
110‧‧‧上拉開關單元 110‧‧‧Pull switch unit
120‧‧‧隔離開關 120‧‧‧Isolation switch
130‧‧‧下拉開關單元 130‧‧‧ Pull-down switch unit
131‧‧‧下拉開關 131‧‧‧ pull-down switch
132‧‧‧下拉開關補償電路 132‧‧‧ Pull-down switch compensation circuit
139‧‧‧控制端 139‧‧‧Control end
140‧‧‧控制單元 140‧‧‧Control unit
141‧‧‧第一電晶體 141‧‧‧First transistor
142‧‧‧第二電晶體 142‧‧‧second transistor
143‧‧‧第三電晶體 143‧‧‧ Third transistor
144‧‧‧第四電晶體 144‧‧‧4th transistor
211‧‧‧電容 211‧‧‧ Capacitance
221‧‧‧第一開關 221‧‧‧First switch
222‧‧‧第二開關 222‧‧‧second switch
223‧‧‧第三開關 223‧‧‧third switch
V1‧‧‧第一電壓 V1‧‧‧ first voltage
V3‧‧‧控制電壓 V3‧‧‧ control voltage
V4‧‧‧電壓 V4‧‧‧ voltage
V5~V7‧‧‧控制信號 V5~V7‧‧‧ control signal
Vc1‧‧‧電壓 V c1 ‧‧‧ voltage
Vdd‧‧‧系統電壓 Vdd‧‧‧ system voltage
Vin‧‧‧輸入端 Vin‧‧‧ input
Vout‧‧‧輸出端 Vout‧‧‧ output
Vp2‧‧‧電壓 V p2 ‧‧‧ voltage
Vss‧‧‧接地電壓 Vss‧‧‧ Grounding voltage
Claims (19)
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TW103136281A TWI563482B (en) | 2014-10-21 | 2014-10-21 | Driver circuit with device variation compensation and operation method thereof |
CN201410685054.6A CN105654878B (en) | 2014-10-21 | 2014-11-25 | Driving circuit with element variation compensation and operation method thereof |
US14/592,910 US9543954B2 (en) | 2014-10-21 | 2015-01-09 | Driver circuit with device variation compensation and operation method thereof |
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TW103136281A TWI563482B (en) | 2014-10-21 | 2014-10-21 | Driver circuit with device variation compensation and operation method thereof |
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TW201616472A true TW201616472A (en) | 2016-05-01 |
TWI563482B TWI563482B (en) | 2016-12-21 |
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TWI566218B (en) * | 2015-12-16 | 2017-01-11 | 奕力科技股份有限公司 | Panel drive circuit |
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TWI566218B (en) * | 2015-12-16 | 2017-01-11 | 奕力科技股份有限公司 | Panel drive circuit |
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CN105654878A (en) | 2016-06-08 |
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US20160112046A1 (en) | 2016-04-21 |
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