CN101771041B - Complementary type SCR (Silicon Controlled Rectifier) structure by auxiliary triggering of PMOS (P-channel Metal Oxide Semiconductor) field effect transistors - Google Patents
Complementary type SCR (Silicon Controlled Rectifier) structure by auxiliary triggering of PMOS (P-channel Metal Oxide Semiconductor) field effect transistors Download PDFInfo
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Abstract
The invention discloses a complementary type SCR (Silicon Controlled Rectifier) structure by the auxiliary triggering of PMOS (P-channel Metal Oxide Semiconductor) field effect transistors. The structure comprises a first silicon controlled rectifier, a second silicon controlled rectifier and a third silicon controlled rectifier, wherein the first silicon controlled rectifier is formed by two bipolar transistors and used for ESD (Electro-Static discharge) protection between a positive power cord and a chip pin requiring protection; the second silicon controlled rectifier is formed by another two bipolar transistors and used for the ESD protection between the chip pin requiring protection and a negative power cord; and the third silicon controlled rectifier is formed by two bipolar transistors respectively coming from the first silicon controlled rectifier and the second silicon controlled rectifier and used for the ESD protection between the positive power code and the negative power cord. The structure adopts the PMOS field effect transistors to reduce the trigger voltage of each silicon controlled rectifier and is particularly suitable for the on-chip ESD protection of an integrated circuit of a deep sub-micron process.
Description
Technical field
The invention belongs to integrated circuit fields, relate in particular to the reliability that a kind of complementary SCR structure is used to improve integrated circuit ESD protection.
Background technology
Natural Electrostatic Discharge phenomenon is the topmost integrity problem that causes that integrated circuit (IC) products lost efficacy.Relevant research shows that 30% of ic failure product all is owing to suffer the static discharge phenomenon caused.Therefore, the reliability of improving integrated circuit electrostatic discharge protection is to the rate of finished products that improves product and even drive whole national economy and have very important effect.
The static discharge phenomenon is divided into three kinds of discharge mode: HBM (human body discharge mode) usually according to the difference of charge source, MM (machine discharge mode), CDM (assembly charging and discharging pattern).And the most common two kinds of static discharge patterns that also are the industrial quarters product must pass through are HBM and MM.When static discharge took place, electric charge flowed into and flows out from the another pin from a pin of chip usually, and the electric current that this moment, electrostatic charge produced is usually up to several amperes, and the voltage that produces at the electric charge input pin is up to several volts even tens volts.Can cause the damage of inside chip if bigger ESD electric current flows into inside chip, simultaneously, the high pressure that produces at input pin also can cause internal components generation grid oxygen punch-through, thereby causes the inefficacy of circuit function.Therefore, damaged by ESD, all will carry out effective ESD protection each pin of chip in order to prevent inside chip.And two main points are mainly considered in the design of ESD protective unit: the one, and the ESD electric current that the ESD protective unit can be released bigger; The 2nd, the ESD protective unit can be with the strangulation of input pin terminal voltage at electronegative potential.
In the research and development process of ESD protection, diode, GGNMOS (NMOS of grid ground connection), SCR devices such as (controllable silicons) are used as the ESD protective unit usually.Along with the development of CMOS technology, the CMOS integrated circuit has become the main flow of integrated circuit development.For the CMOS integrated circuit, the input of chip output have usually the input buffering level output buffer stage or the grid of MOS device as input.Therefore, when esd event takes place, the stress (voltage) that ESD produces can directly act on the gate oxide of MOS device, if the ESD protective unit can not in time be opened and with the input strangulation electronegative potential (being often referred to the gate oxide breakdown voltage that is lower than inner MOS device), then can cause input the gate oxide generation punch-through of output MOS device, thereby cause the inefficacy of chip functions.
Because the SCR structure has the very low voltage of keeping, and there is positive feedback loop in inside, and therefore, the SCR structure has very strong ESD current drain ability, becomes the safeguard structure of main flow in ESD protection field.But for common SCR structure, the shortcoming of a maximum is that its trigger voltage (referring generally to the avalanche breakdown voltage between N trap and P trap) is higher, so that common SCR is not suitable for the ESD protection of deep-submicron and even nanoscale integrated circuit.
Complementary SCR structure is by ESD safeguard structure on the sheet that is used for the CMOS integrated circuit of United States Patent (USP) (U.S.Pat.Nos.5473169) proposition.
Fig. 1 is the equivalent circuit diagram of the complementary SCR of this patent, and this safeguard structure constitutes the complementary type ESD protectiving scheme of input IN to positive power line VDD and negative power line VSS by first controllable silicon SCR 1 and second controllable silicon SCR 2.First controllable silicon SCR 1 is made of bipolar transistor 10 and bipolar transistor 11, wherein the emitter of bipolar transistor 10 meets positive power line VDD by trap resistance 16, the base stage of bipolar transistor 10 meets positive power line VDD by trap resistance 14, and the emitter of bipolar transistor 11 meets the chip pin IN that needs protection; The base stage of bipolar transistor 11 meets negative power line VSS by trap resistance 17.
Second controllable silicon SCR 2 is made of bipolar transistor 12 and bipolar transistor 13, wherein the emitter of bipolar transistor 12 meets the chip pin IN that needs protection by trap resistance 18, the base stage of bipolar transistor 12 meets positive power line VDD by trap resistance 15, and the emitter of bipolar transistor 13 meets negative power line VSS; The base stage of bipolar transistor 13 meets negative power line VSS by trap resistance 19.
Fig. 2 is the longitudinal sectional drawing of this complementary SCR, this process using be single trap (P trap) CMOS technology, utilize N type silicon to be substrate.Trap resistance 14 wherein and trap resistance 15 are parasitic resistance substrate, and trap resistance 16, trap resistance 17, trap resistance 18 and trap resistance 19 are parasitic P trap (P_well) resistance.N type substrate 29 is provided with N+ and is injected with source region 20, N+ is injected with source region 22, N+ is injected with source region 24, N+ is injected with source region 26, P+ is injected with source region 21, P+ is injected with source region 23, P+ is injected with source region 25, P+ is injected with source region 27, P trap 28a, P trap 28b, P trap 28c, P trap 28d, wherein N+ is injected with source region 20, N+ is injected with source region 24 and P+ and is injected with source region 25 and is connected to positive power line VDD, P+ is injected with source region 21 and N+ and is injected with source region 26 and is connected to chip input IN, and N+ is injected with source region 22 and P+ is injected with source region 23, P+ is injected with source region 27 and is connected to negative power line VSS.
Wherein P+ is injected with second controllable silicon SCR 2 that source region 21, P trap 28a, N type substrate 29, P trap 28b, N+ are injected with the PNPN type four-level semiconductor structure in 22 pie graphs 1 of source region, and P+ is injected with first controllable silicon SCR 1 that source region 25, P trap 28c, N type substrate 29, P trap 28d, N+ are injected with the PNPN type four-level semiconductor structure in 26 pie graphs 1 of source region.
The shortcoming of above-mentioned complementary SCR structure mainly is that its trigger voltage (avalanche breakdown voltage between N type substrate and P trap) is very high, so that it is difficult to be applicable to ESD protection on the sheet of integrated circuit under the deep submicron process.
Summary of the invention
The technical problem to be solved in the present invention has: the first, and utilize pmos fet as auxiliary trigger element, realize the ESD protection of low trigger voltage, make ESD protection on its sheet that more is applicable to integrated circuit under the deep submicron process.Second; layout by actual domain needing to realize the chip pin of protection to positive power line; positive power line is to the chip pin that needs protection; the chip pin that needs protection is to negative power line; negative power line is to the chip pin that needs protection; positive power line is to negative power line, and negative power line protects to the ESD of various situations between positive power line, thereby reaches maximum chip area utilance.
A kind of pmos fet complementary SCR structure triggered with assistance comprises:
First controllable silicon is made of first bipolar transistor and second bipolar transistor, and wherein the emitter of first bipolar transistor connects positive power line, and the base stage of first bipolar transistor is connected to positive power line by N trap resistance; The emitter of second bipolar transistor connects the chip pin that needs protection, and the base stage of second bipolar transistor is connected to negative power line by P trap resistance;
Second controllable silicon is made of the 3rd bipolar transistor and the 4th bipolar transistor, and wherein the emitter of the 3rd bipolar transistor connects the described chip pin that needs protection, and the base stage of the 3rd bipolar transistor is connected to positive power line by N trap resistance; The emitter of the 4th bipolar transistor connects negative power line, and the base stage of the 4th bipolar transistor is connected to negative power line by P trap resistance;
The base stage of the base stage of first bipolar transistor and the 3rd bipolar transistor is connected to positive power line by N trap resistance; The base stage of the base stage of second bipolar transistor and the 4th bipolar transistor is connected to negative power line by P trap resistance.
The shared N trap of described first bipolar transistor and the 3rd bipolar transistor.
From the annexation between first bipolar transistor and the 4th bipolar transistor as can be seen, first bipolar transistor and the 4th bipolar transistor are equivalent to constitute the another one controllable silicon, i.e. the 3rd controllable silicon.
Complementary SCR structure of the present invention also is provided with pmos fet, the source electrode of pmos fet, grid and substrate are connected, and be connected to the base stage of first bipolar transistor and the 3rd bipolar transistor, the drain electrode of pmos fet inserts the base stage of second bipolar transistor and the 4th bipolar transistor.
The base stage of described first bipolar transistor links to each other with the collector electrode of second bipolar transistor; The collector electrode of described first bipolar transistor links to each other with the base stage of second bipolar transistor; The base stage of described the 3rd bipolar transistor links to each other with the collector electrode of the 4th bipolar transistor; The collector electrode of described the 3rd bipolar transistor links to each other with the base stage of the 4th bipolar transistor.
Described first controllable silicon, second controllable silicon and a kind of domain structure of the 3rd silicon controlled are as follows:
An adjacent successively P trap, N trap and the 2nd P trap of being furnished with on the P type substrate is furnished with successively from a P trap to the two P trap directions:
The one P+ is injected with the source region, is positioned at a P trap, and is divided into the first area of connection negative power line and the second area of the drain electrode that is connected pmos fet;
The one N+ is injected with the source region, is positioned at a P trap, is connected to the chip pin that needs protection;
The 2nd P+ is injected with the source region, is positioned at the N trap, is connected to positive power line;
The 2nd N+ is injected with the source region, is positioned at the N trap, and is divided into first area that is connected to positive power line and the second area that is connected the pmos fet source electrode;
The 3rd P+ is injected with the source region, is positioned at the N trap, is connected to the chip pin that needs protection;
The 3rd N+ is injected with the source region, is positioned at the 2nd P trap, is connected to negative power line;
The 4th P+ is injected with the source region, is positioned at the 2nd P trap, and is divided into first area that connects negative power line and the second area that is connected the pmos fet drain electrode.
Described first controllable silicon, second controllable silicon and second kind of domain structure implementation of the 3rd silicon controlled are as follows:
An adjacent successively P trap, N trap and the 2nd P trap of being furnished with on the P type substrate is furnished with successively from a P trap to the two P trap directions:
The one P+ is injected with the source region, is positioned at a P trap, and is divided into the first area of connection negative power line and the second area of the drain electrode that is connected pmos fet;
The one N+ is injected with the source region, is positioned at a P trap, and is divided into the first area and the second area that is connected negative power line that is connected to the chip pin that needs protection;
The 2nd P+ is injected with the source region, is positioned at the N trap, and is divided into first area that connects positive power line and the second area that is connected to the chip pin that needs protection;
The 2nd N+ is injected with the source region, is positioned at the N trap, and is divided into the second area of first area that is connected to positive power line and the source electrode that is connected pmos fet;
The 3rd P+ is injected with the source region, is positioned at the N trap, and is divided into first area that is connected to the chip pin that needs protection and the second area that is connected to positive power line;
The 3rd N+ is injected with the source region, is positioned at the 2nd P trap, and is divided into first area that is connected to negative power line and the second area that is connected to the chip pin that needs protection;
The 4th P+ is injected with the source region, is positioned at the 2nd P trap, and is divided into first area that connects negative power line and the second area that is connected the pmos fet drain electrode.
The pmos fet complementary SCR structure triggered with assistance of utilizing of the present invention has lower trigger voltage; and needing can realize the chip pin of protection to positive power line; positive power line is to the chip pin that needs protection; the chip pin that needs protection is to negative power line; negative power line is to the chip pin that needs protection; positive power line is to negative power line; negative power line is to the electrostatic discharge protective of various ESD situations between positive power line; be more suitable on the sheet of integrated circuit under the deep submicron process ESD protection, the silicon area that adopts the domain structure of this complementary SCR that the ESD protective unit is taken simultaneously is littler.
Description of drawings
Fig. 1 is the equivalent circuit diagram of existing complementary SCR safeguard structure;
Fig. 2 is the longitudinal sectional drawing of existing complementary SCR safeguard structure;
Fig. 3 is the equivalent circuit diagram of complementary SCR safeguard structure of the present invention;
Fig. 4 is first kind of domain implementation of complementary SCR safeguard structure of the present invention;
Fig. 5 is an A-A profile among Fig. 4;
Fig. 6 is a B-B profile among Fig. 4;
Fig. 7 is second kind of domain implementation of complementary SCR safeguard structure of the present invention;
Fig. 8 is in the complementary SCR safeguard structure of the present invention, and esd event occurs in vdd terminal, and the ESD current drain path during IN end ground connection;
Fig. 9 is in the complementary SCR safeguard structure of the present invention, and esd event occurs in the IN end, and the ESD current drain path during VSS end ground connection;
Figure 10 is in the complementary SCR safeguard structure of the present invention, and esd event occurs in vdd terminal, and the ESD current drain path during VSS end ground connection;
Figure 11 is in the complementary SCR safeguard structure of the present invention, and esd event occurs in the VSS end, and the ESD current drain path during IN end ground connection;
Figure 12 is in the complementary SCR safeguard structure of the present invention, and esd event occurs in the IN end, and the ESD current drain path during vdd terminal ground connection;
Figure 13 is in the complementary SCR safeguard structure of the present invention, and esd event occurs in the VSS end, and the ESD current drain path during vdd terminal ground connection.
Embodiment
A kind of pmos fet complementary SCR structure triggered with assistance of the present invention, its equivalent circuit diagram as shown in Figure 3, it comprises:
First controllable silicon SCR 1 is made of first bipolar transistor 30 and second bipolar transistor 31, and wherein the emitter of first bipolar transistor 30 meets positive power line VDD, and the base stage of first bipolar transistor 30 is connected to positive power line VDD by N trap resistance 36; The emitter of second bipolar transistor 31 meets the chip pin IN that needs protection, and the base stage of second bipolar transistor 31 is connected to negative power line VSS by P trap resistance 37;
Second controllable silicon SCR 2, constitute by the 3rd bipolar transistor 32 and the 4th bipolar transistor 33, wherein the emitter of the 3rd bipolar transistor 32 meets the described chip pin IN that needs protection, and the base stage of the 3rd bipolar transistor 32 is connected to positive power line VDD by N trap resistance 34; The emitter of the 4th bipolar transistor 33 meets negative power line VSS, and the base stage of the 4th bipolar transistor 33 is connected to negative power line VSS by P trap resistance 35;
The base stage of first bipolar transistor 30 links to each other with the collector electrode of second bipolar transistor 31; The collector electrode of first bipolar transistor 30 links to each other with the base stage of second bipolar transistor 31; The base stage of the 3rd bipolar transistor 32 links to each other with the collector electrode of the 4th bipolar transistor 33; The collector electrode of the 3rd bipolar transistor 32 links to each other with the base stage of the 4th bipolar transistor 33.
The base stage of the base stage of first bipolar transistor 30 and the 3rd bipolar transistor 32 inserts positive power line VDD by N trap resistance 36 and N trap resistance 34; The base stage of the base stage of second bipolar transistor 31 and the 4th bipolar transistor 33 inserts negative power line VSS by P trap resistance 37 and P trap resistance 35.Therefrom as can be seen, first bipolar transistor 30 and the 4th bipolar transistor 33 are equivalent to constitute the another one controllable silicon, i.e. the 3rd controllable silicon SCR 3 among the figure.
Referring to Fig. 4, Fig. 5, Fig. 6, the domain of complementary SCR safeguard structure of the present invention is:
An adjacent successively P trap 47a, N trap 48 and the 2nd P trap 47b of being furnished with on the P type substrate 49 is furnished with successively from a P trap 47a to the two P trap 47b directions:
The one P+ is injected with the source region, is positioned at a P trap 47a, and is divided into the first area 40a of connection negative power line VSS and the second area 40b of the drain electrode that is connected pmos fet 38;
The one N+ is injected with source region 41, is positioned at a P trap 47a, is connected to the chip pin IN that needs protection;
The 2nd P+ is injected with source region 42, is positioned at N trap 48, is connected to positive power line VDD;
The 2nd N+ is injected with the source region, is positioned at N trap 48, and is divided into the first area 43a of connection positive power line VDD and the second area 43b of the source electrode that is connected pmos fet 38;
The 3rd P+ is injected with source region 44, is positioned at N trap 48, is connected to the chip pin IN that needs protection;
The 3rd N+ is injected with source region 45, is positioned at the 2nd P trap 47b, is connected to negative power line VSS;
The 4th P+ is injected with the source region, is positioned at the 2nd P trap 47b, and is divided into the first area 46a of connection negative power line VSS and the second area 46b of the drain electrode that is connected pmos fet 38.
Diagonal line hatches zone among Fig. 5, Fig. 6 is a local field oxygen area of isolation (Locos).
Referring to Fig. 7, the another kind of domain execution mode of complementary SCR safeguard structure of the present invention, an adjacent successively P trap 47a, N trap 48 and the 2nd P trap 47b of being furnished with on the P type substrate 49 is furnished with successively from a P trap 47a to the two P trap 47b directions:
The one P+ is injected with the source region, is positioned at a P trap 47a, and is divided into the first area 40a of connection negative power line VSS and the second area 40b of the drain electrode that is connected pmos fet 38;
The one N+ is injected with the source region, is positioned at a P trap 47a, and is divided into the first area 41a and the second area 41b that is connected negative power line VSS that is connected to the chip pin IN that needs protection;
The 2nd P+ is injected with the source region, is positioned at N trap 48, and is divided into the first area 42a that connects positive power line VDD and is connected to the second area 42b that needs protection chip pin IN;
The 2nd N+ is injected with the source region, is positioned at N trap 48, and is divided into the first area 43a of connection positive power line VDD and the second area 43b of the source electrode that is connected pmos fet 38;
The 3rd P+ is injected with the source region, is positioned at N trap 48, and is divided into first area 44a that is connected to the chip pin IN that needs protection and the second area 44b that is connected to positive power line VDD;
The 3rd N+ is injected with the source region, is positioned at the 2nd P trap 47b, and is divided into first area 45a that is connected to negative power line VSS and the second area 45b that is connected to the chip pin IN that needs protection;
The 4th P+ is injected with the source region, is positioned at the 2nd P trap 47b and is divided into the first area 46a of connection negative power line VSS and the second area 46b of the drain electrode that is connected pmos fet 38.
SCR1 shown in Fig. 4 and Fig. 7, SCR2, these three SCR paths of SCR3 correspond respectively to first controllable silicon SCR 1, second controllable silicon SCR 2, the 3rd controllable silicon SCR 3 among Fig. 3.
When esd event occurs in the positive power line vdd terminal; and when needing the chip pin IN end ground connection of protection; because the amplification of pmos fet 38 endoparasitism bipolar transistor PNP; make that the puncture voltage (the oppositely puncture voltage of PN junction) of pmos fet 38 is lower than the reverse breakdown voltage between common trap and trap (as N trap and P trap); at first avalanche breakdown takes place in pmos fet 38; shown in its avalanche breakdown electric current ESD trigger current as shown in phantom in Figure 8; when the ESD trigger current is enough to make first controllable silicon SCR, the 1 generation breech lock of first bipolar transistor 30 and second bipolar transistor, 31 formations; since first controllable silicon SCR, 1 two ends keep voltage ratio pmos fet 38 to keep voltage low; this moment, the ESD electric current can release the ESD electric current big by first controllable silicon SCR 1 that first bipolar transistor 30 and second bipolar transistor 31 constitute, and released shown in the ESD electric current arrow of path shown in solid line among Fig. 8.
Occur in the chip pin IN end that needs protection when esd event; and during negative power line VSS end ground connection; be still pmos fet 38 avalanche breakdown takes place earlier; shown in its avalanche breakdown electric current ESD trigger current as shown in phantom in Figure 9; when the ESD trigger current is enough to make second controllable silicon SCR, the 2 generation breech locks of the 3rd bipolar transistor 32 and the 4th bipolar transistor 33 formations; this moment, the ESD electric current can release the ESD electric current big by second controllable silicon SCR 2 that the 3rd bipolar transistor 32 and the 4th bipolar transistor 33 constitute, and released shown in the ESD electric current arrow of path shown in solid line among Figure 10.
When esd event occurs in the positive power line vdd terminal, and during negative power line VSS end ground connection, avalanche breakdown takes place earlier in pmos fet 38, shown in its avalanche breakdown electric current ESD trigger current as shown in phantom in Figure 10, when the ESD trigger current is enough to make the 3rd controllable silicon SCR 3 generation breech locks of first bipolar transistor 30 and the 4th bipolar transistor 33 formations, this moment, the ESD electric current can release the ESD electric current big by the 3rd controllable silicon SCR 3 that first bipolar transistor 30 and the 4th bipolar transistor 33 constitute, and released shown in the ESD electric current arrow of path shown in solid line among Figure 10.
When esd event occurs in negative power line VSS end; and when needing the chip pin IN end ground connection of protection; this moment, the ESD electric current can be by second bipolar transistor, the 31 entozoic forward diode D1 ESD electric current of releasing, shown in the ESD electric current arrow of ESD current drain path shown in solid line among Figure 11.
Occur in the chip pin IN end that needs protection when esd event; and during positive power line vdd terminal ground connection; this moment, the ESD electric current can be by the 3rd bipolar transistor 32 entozoic forward diode D2 ESD electric current of releasing, shown in the ESD electric current arrow of ESD current drain path shown in solid line among Figure 12.
When esd event occurs in negative power line VSS end, and during positive power line vdd terminal ground connection, this moment, the ESD electric current can be by first bipolar transistor 30, second bipolar transistor 31, the 3rd bipolar transistor 32, the 4th bipolar transistor 33 entozoic forward diode D3, the forward diode D4 ESD electric current of releasing, shown in the ESD electric current arrow of ESD current drain path shown in solid line among Figure 13.
Claims (4)
1. pmos fet complementary SCR structure triggered with assistance comprises:
First controllable silicon is made of first bipolar transistor (30) and second bipolar transistor (31), and wherein the emitter of first bipolar transistor (30) is connected to positive power line, and the emitter of second bipolar transistor (31) is connected to the chip pin that needs protection;
Second controllable silicon, constitute by the 3rd bipolar transistor (32) and the 4th bipolar transistor (33), wherein the emitter of the 3rd bipolar transistor (32) is connected to the described chip pin that needs protection, and the emitter of the 4th bipolar transistor (33) is connected to negative power line;
It is characterized in that, be provided with pmos fet (38), source electrode, grid and the substrate of pmos fet (38) are connected, and be connected to the base stage of first bipolar transistor (30) and the 3rd bipolar transistor (32), the drain electrode of pmos fet (38) is connected to the base stage of second bipolar transistor (31) and the 4th bipolar transistor (33);
The base stage of the base stage of described first bipolar transistor (30) and the 3rd bipolar transistor (32) is connected to positive power line by N trap resistance;
The base stage of the base stage of described second bipolar transistor (31) and the 4th bipolar transistor (33) is connected to negative power line by P trap resistance;
The base stage of described first bipolar transistor (30) links to each other with the collector electrode of second bipolar transistor (31);
The collector electrode of described first bipolar transistor (30) links to each other with the base stage of second bipolar transistor (31);
The base stage of described the 3rd bipolar transistor (32) links to each other with the collector electrode of the 4th bipolar transistor (33);
The collector electrode of described the 3rd bipolar transistor (32) links to each other with the base stage of the 4th bipolar transistor (33).
2. complementary SCR structure as claimed in claim 1 is characterized in that, described first bipolar transistor (30) and the shared N trap of the 3rd bipolar transistor (32) (48).
3. complementary SCR structure as claimed in claim 2 is characterized in that, described first controllable silicon and the second silicon controlled domain structure are as follows:
An adjacent successively P trap (47a), described N trap (48) and the 2nd P trap (47b) of being furnished with on the P type substrate (49) is furnished with successively from a P trap (47a) to the 2nd P trap (47b) direction:
The one P+ is injected with the source region, is positioned at a P trap (47a) and is divided into the first area (40a) that is connected to negative power line and the second area (40b) of the drain electrode that is connected to pmos fet (38);
The one N+ is injected with source region (41), is positioned at a P trap (47a), is connected to the chip pin that needs protection;
The 2nd P+ is injected with source region (42), is positioned at described N trap (48), is connected to positive power line;
The 2nd N+ is injected with the source region, is positioned at described N trap (48) and is divided into the first area (43a) that is connected to positive power line and the second area (43b) of the source electrode that is connected to pmos fet (38);
The 3rd P+ is injected with source region (44), is positioned at described N trap (48), is connected to the chip pin that needs protection;
The 3rd N+ is injected with source region (45), is positioned at the 2nd P trap (47b), is connected to negative power line;
The 4th P+ is injected with the source region, is positioned at the 2nd P trap (47b) and is divided into the first area (46a) that is connected to negative power line and the second area (46b) of the drain electrode that is connected to pmos fet (38).
4. complementary SCR structure as claimed in claim 2 is characterized in that, described first controllable silicon and the second silicon controlled domain structure are as follows:
An adjacent successively P trap (47a), described N trap (48) and the 2nd P trap (47b) of being furnished with on the P type substrate (49) is furnished with successively from a P trap (47a) to the 2nd P trap (47b) direction:
The one P+ is injected with the source region, is positioned at a P trap (47a) and is divided into the first area (40a) that is connected to negative power line and the second area (40b) of the drain electrode that is connected to pmos fet (38);
The one N+ is injected with source region (41), is positioned at a P trap (47a) and is divided into first area (41a) that is connected to the chip pin that needs protection and the second area (41b) that is connected to negative power line;
The 2nd P+ is injected with source region (42), is positioned at described N trap (48) and is divided into the first area (42a) that is connected to positive power line and is connected to the second area (42b) of the chip pin that needs protection;
The 2nd N+ is injected with the source region, is positioned at described N trap (48) and is divided into the first area (43a) that is connected to positive power line and the second area (43b) of the source electrode that is connected to pmos fet (38);
The 3rd P+ is injected with source region (44), is positioned at described N trap (48) and is divided into first area (44a) that is connected to the chip pin that needs protection and the second area (44b) that is connected to positive power line;
The 3rd N+ is injected with source region (45), is positioned at the 2nd P trap (47b) and is divided into first area (45a) that is connected to negative power line and the second area (45b) that is connected the chip pin that needs protection;
The 4th P+ is injected with the source region, is positioned at the 2nd P trap (47b) and is divided into the second area (46b) of first area (46a) that is connected to negative power line and the drain electrode that is connected pmos fet (38).
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|---|---|---|---|
| CN 201010040056 CN101771041B (en) | 2010-01-19 | 2010-01-19 | Complementary type SCR (Silicon Controlled Rectifier) structure by auxiliary triggering of PMOS (P-channel Metal Oxide Semiconductor) field effect transistors |
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| CN 201010040056 CN101771041B (en) | 2010-01-19 | 2010-01-19 | Complementary type SCR (Silicon Controlled Rectifier) structure by auxiliary triggering of PMOS (P-channel Metal Oxide Semiconductor) field effect transistors |
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| CN101771041A CN101771041A (en) | 2010-07-07 |
| CN101771041B true CN101771041B (en) | 2011-05-25 |
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