CN101752357A - 无引线壳体封装件 - Google Patents
无引线壳体封装件 Download PDFInfo
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- CN101752357A CN101752357A CN200910253498A CN200910253498A CN101752357A CN 101752357 A CN101752357 A CN 101752357A CN 200910253498 A CN200910253498 A CN 200910253498A CN 200910253498 A CN200910253498 A CN 200910253498A CN 101752357 A CN101752357 A CN 101752357A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 116
- 238000005538 encapsulation Methods 0.000 claims description 44
- 238000004806 packaging method and process Methods 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000000465 moulding Methods 0.000 claims description 9
- 230000001133 acceleration Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000000523 sample Substances 0.000 claims 1
- 239000000463 material Substances 0.000 description 21
- 239000010949 copper Substances 0.000 description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 230000035882 stress Effects 0.000 description 10
- 238000005266 casting Methods 0.000 description 9
- 230000008646 thermal stress Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 239000004033 plastic Substances 0.000 description 5
- 229920003023 plastic Polymers 0.000 description 5
- 230000003044 adaptive effect Effects 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 230000002277 temperature effect Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- B81B7/0045—Packages or encapsulation for reducing stress inside of the package structure
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Abstract
本发明涉及一种用于封装半导体元件的无引线封装件或无引脚封装件,其特征在于,所述无引线封装件具有至少两个半导体元件,所述半导体元件这样地设置所述无引线封装件的引线框的连接区域上,使得在半导体元件出现变形时,所述半导体元件的变形至少部分地或基本上完全地相互补偿。
Description
技术领域
本发明涉及一种用于半导体元件、如传感器芯片元件、ASIC芯片元件和其它芯片元件的无引线的壳体封装件。本发明尤其涉及一种用于所谓的QFN壳体或QFN传感器封装的壳体封装件。
背景技术
传感器通常封装在带有向外弯曲的连接触头的带引线的模制壳体或壳体中。在此,各个传感器和ASIC芯片元件要么是并排地、即肩并肩地(sideby side),要么是相互叠置地、即堆叠地设置在铜基底或引线框(引线框架)上,并且,各个传感器和ASIC芯片元件以浇铸工艺(模制工艺)包封或包铸并接着借助于弯曲的连接触头(引线)作为完整的元件焊接在电路板上。为在模制壳体内部居中地设置硅元件,引线框(引线框架)大多包含一凹下的连接区域(带有向下偏移(Downset)的裸芯片焊盘)。
传感器和半导体也越来越多地埋置在所谓的QFN壳体中。在此,所述壳体没有从壳体伸出的引脚或连接触头。替代引脚或连接触头,所述壳体被扁平地焊接在电路板上。为此,除了包封在壳体中的芯片或传感器部件外,在壳体中还集成相应的连接面或连接区域。
现在,壳体和包含在壳体内的部件通常使用具有不同热膨胀系数的材料,这可能导致热应力。在此,传感器尤其是对例如由壳体及其部件的不同热膨胀产生的挠曲反应敏感。
发明内容
现在,按本发明为无引线的壳体提供一种改进的封装件,在该封装件中至少减小或基本上防止了热应力。
按照本发明提供了一种用于封装半导体元件的无引线封装件或无引脚封装件,其中,无引线封装件具有至少两个半导体元件,所述半导体元件这样地设置在无引线封装件的引线框的连接区域上,使得在半导体元件例如由于热应力出现变形的情况下,半导体元件的所述变形至少部分地或基本上完全地相互补偿。
在此,按本发明的封装件具有这样的优点,即,半导体元件有针对性地设置在引线框的连接区域上,使得因封装件的材料的热膨胀系数不同在半导体元件由于热应力出现变形时,所述变形可以基本上相互补偿。也就是说,按照本发明有针对性地在无引线壳体中产生相反的变形,这些变形至少部分地或基本上完全地相互补偿。因此,例如也可以在这种无引线封装件中设置敏感的传感器芯片元件,这些传感器芯片元件在其它情况下由于在迄今为止公知的壳体中(由诱发的应力引起)的强烈变形而在其传感器信号中具有不希望的漂移。
在此,在无引线封装件中,通过设置引线框的在高度上错开的连接区域,实现了无引线封装件的对称的或几乎对称的结构。也就是说在此可以在连接区域的两侧上设置至少一个或多个半导体元件,例如在连接区域的上侧和下侧上设置一样多的半导体元件,或者也可以在引线框的连接区域的两侧上设置不同数目的半导体元件。在半导体元件数目不同时,半导体元件例如在其布置上这样地选择,即,连接区域的每一侧上的所有半导体元件的总高度基本上一样大,使得半导体元件在连接区域的两侧上的变形可以基本上相互抵消或至少相互减小。
本发明的其它优选实施形式在下面说明。
在本发明的一种实施形式中,无引线封装件的基本上对称的结构在封装件的引线框的连接区域的下侧和上侧上具有一样多或不一样多的半导体元件。在此,基本上对称的结构可以例如至少仅设置在壳体封装件的一个区域或多个区域中,在所述区域中设置有一些敏感的半导体元件,例如敏感的传感器元件。例如可以在无引线封装件的引线框的连接区域的一侧上设置一半导体元件、例如ASIC芯片元件,而在另一侧上设置两个并排地或叠放地设置的半导体元件、例如传感器元件。在此,在对称性上这样地选择半导体元件的布置,使得这些半导体元件延伸跨越相同的高度或总高度和/或相同的面积或总面积。因此,可以产生适当的相反变形,其中,与迄今为止已知的封装件相比,热应力或变形可以相互抵消。
按照另一种按本发明的实施形式,无引线封装件是一种QFN壳体封装件。但本发明不限于这一例子。这种QFN封装件具有这样的优点,即,其通过按本发明的构造也可以用于敏感的传感器元件,这在现有技术中是不可能的。
在另一种按本发明的实施形式中,封装件的引线框的连接区域相对引线框的连接触头在高度上错位。换句话说,连接区域例如借助于深拉或其它恰当的方法相对于引线框的连接触头升高或以一高度错位构造。这具有这样的优点,即,由此可以创造一自由空间,从而可以在引线框的连接区域两侧上设置半导体元件,因此该封装也尤其是可以用在所谓的无引线壳体、例如QFN壳体中。
在一种按本发明的实施形式中,至少两个或更多个半导体元件相叠地设置在无引线封装件的引线框的连接区域的上侧和/或下侧上。作为该方案的替代或与该方案的组合,在另一种按本发明的实施形式中,至少两个或更多个半导体元件并排地设置在无引线封装件的引线框的连接区域的上侧和/或下侧。通过这种方式既可以在元件在连接区域上的所谓的肩并肩的布置中,也可以在所谓的堆叠布置中或两者的组合中实现基本上对称的封装件,该封装件适于补偿热应力。
按照另一种按本发明的实施形式,引线框的连接区域的下侧上的半导体元件形成封装件的下终端。在此,半导体元件例如可从下面接近,也就是没有配设起覆盖作用的模制层或浇铸层。
在另一种按本发明的实施形式中,封装件在下侧至少在半导体元件的区域中通过模制层或浇铸层覆盖,因此,这些半导体元件不能从外部接近。换句话说,该封装件具有模制下端(Moldunterfluss)。因为上侧和下侧都配设有模制层或浇铸层,封装件的对称性被进一步加强,其中,附加的模制下端有助于进一步减小应力。
按照另一种实施形式,无引线封装件的引线框的连接区域一侧上的一个或多个半导体元件的总高度和/或总面积选择为基本上等于或近似等于对置侧上的一个或多个半导体元件的总高度和/或总面积,其中,无引线封装件的引线框的连接区域两侧上的半导体元件的数目一样大或不一样大。即便连接区域两侧上的半导体元件的数目不同,也可以通过半导体元件在基本上相等的总面积和/或相等的总高度上的布置产生相反的变形,所述相反的变形至少可以相互减小。
在本发明的另一种实施形式中,第一半导体元件是传感器芯片元件,其设置在引线框的连接区域的一侧上,而第二半导体元件是ASIC芯片元件,其设置在连接区域的另一侧上。在此,引线框的连接区域可以例如稍微更窄地构造,使得这两个半导体元件例如更轻易地通过相应的键合线连接相互连接。附加地或替代地,下方的半导体元件的连接区域可以通过结构化来释放,或者换句话说,该连接区域可以具有一个或多个空隙,因此,下部区域中的焊盘是暴露的,使得连接区域上侧和下侧上的半导体元件可以通过键合线连接彼此相连。
附图说明
以下根据附图中的示意图详细阐述本发明的实施方式。其中示出:
图1示出按现有技术的、带有连接触头(引线)的SOIC全铸壳体(全模制壳体)的立体视图;
图2示出全铸壳体(全模制壳体)的剖视图,该全铸壳体具有相互堆叠的结构和凹下的连接区域(裸芯片焊盘(Diepad));
图3示出QFN模制壳体的下侧;
图4示出QFN引线框(QFN铜引线框);
图5示出带有复合堆叠的标准QFN封装件,其中,引线框(引线框架)或连接区域(裸芯片焊盘)作为终端包覆模塑,
图6示出壳体和设置在该壳体中的硅芯片元件由热应力引起的变形的示意图;
图7示出按本发明的堆叠形式的无引线封装件或QFN封装件;
图8示出按本发明的第二实施形式的另一种无引线封装件或此处的QFN封装件。
具体实施方式
只要没有另外说明,在所有的图中相同的或功能相同的元件和装置均使用相同的附图标记。
图1首先示出如由现有技术已知的、带有连接触头(引线)12的SOIC(Small Outline Integrated Circuit)全模制壳体10的立体图。在此,弯曲的连接触头12(引脚)或金属管脚设置在壳体10的纵侧上。在此,连接触头12这样地弯曲,使得其平整地贴靠在(未示出的)电路板上,SOIC壳体10可以与该电路板连接。
在图2中还示出了按现有技术的全模制壳体10的剖视图。在此,该模制壳体10具有相互堆叠的传感器结构。在此,引线框22的凹下的连接区域(裸芯片焊盘)14设置在该壳体10中。此外,第一半导体元件16固定在该连接区域14上,而第二半导体元件18又固定在该第一半导体元件16上。在此,这两个半导体元件16,18可以例如以黏附材料或粘结材料固定。设置在壳体10侧面上的连接触头12通过键合线连接20与这两个半导体元件16,18连接。在此,壳体10或封装件形成浇铸连接,在该浇铸连接中,这些半导体元件16,18、带有连接区域14的引线框22和键合线连接20以浇注材料、例如塑料包封,以及连接触头12的一部分被包封。
除了借助图1和2描述的壳体10之外,在此期间也使用新的、现代的壳体形式。其中一种是所谓的QFN(Quad Flat Non-Lead)壳体10。在此,图3、4和5示出了如由现有技术已知的QFN壳体10的封装形式。
在图3中从QFN模制壳体的下侧示出了QFN模制壳体10。对于这种封装形式典型的是:这种所谓的无引线壳体10没有如之前参照图1和2所述的壳体10那样的向外弯曲的连接触头或引脚。换句话说,QFN壳体10具有无引线的壳体封装件或者无引脚的壳体封装件。在QFN壳体10中,作为其替代,设置在铜基底上的硅元件仅仅被包覆模塑或以塑料包封。在此,接着通过引线框(引线框架)22在壳体10的封装件下侧上的接触面12实现与电路板的接通。在图3中示出了相应的接触面或连接触头12,以及设置在中央的连接区域14或连接面(裸芯片焊盘)。
此外,在图4中示出了QFN铜引线框(QFN铜引线框架)22。在此,QFN引线框22首先具有连接区域(裸芯片焊盘)14,以及一排连接触头(接触焊盘)。QFN引线框22还具有用于连接区域14的悬挂点24。
图5还示出了带有复合堆叠的QFN壳体10的例子的剖视图。在此,该QFN壳体10具有连接区域(裸芯片焊盘)14,以及引线框(引线框架)22的连接触头(接触焊盘)12。在此,引线框22的连接区域14和连接触头12位于一个共同的平面上或在一个水平上,也就是说,连接区域14和连接触头12不位于相互错开的平面上。例如在连接区域14上设置有ASIC(Application Specific Integrated Circuit)芯片元件16。在ASIC芯片元件16上例如又设置有传感器芯片元件18,该传感器芯片元件18通过键合线连接20与ASIC芯片元件16连接。该ASIC芯片元件16本身通过键合线连接20与一个相应的连接触头12或多个连接触头12连接。此外,这两个半导体元件16,18、连接区域(裸芯片焊盘)14、键合线连接20和引线框(引线框架)22的连接触头12配设有模制罩30或包封在塑料中。
如图5所示,引线框(引线框架)22和连接区域(裸芯片焊盘)14作为终端模制。换句话说,壳体10在底部具有连接触头12或接触面,用于提供与(未示出的)电路板的电连接。此外,壳体10的封装表面的底部上的连接区域14设计为可从外部接近。
然而,如图6所示,在模制壳体10内部由于温度影响可能导致壳体10或其封装件的变形或扭曲。在图6中示例地示出了壳体10的变形,在该壳体中,例如ASIC芯片元件16和硅芯片元件18相叠地设置或固定在带有接触端口的引线框22的连接区域(裸芯片焊盘)14上。在此,带有两个半导体元件16,18的壳体10由于其不对称的结构和壳体10及其元件16,18的材料缺乏热相容性而强烈的挠曲或扭曲。
由于壳体10及其元件(在此是两个半导体元件16,18)的材料的热膨胀系数不同以及各种材料的与此有关的、缺乏的热适配,由温度影响导致壳体10的这样的变形。其结果是:由于温度变化而在壳体10中产生应力。例如在传感器芯片元件埋置在壳体10中的情况下,这些应力又会对传感器芯片元件的传感器信号产生不利影响。更准确的说,例如会出现不希望的传感器信号飘移。正是这种应力特性或压力特性在过去导致使用尽管能应力较少但也明显更昂贵的预模制壳体。
在所谓的无引线壳体10中,例如之前参照图3、4和5所述的QFN壳体,通常仅对插装有一个或多个硅元件的引线框(引线框架)22进行包覆模塑或包封。因此,如图5所示,引线框(铜引线框架)22是壳体10的终端,并因此不允许对称的复合堆叠。硅芯片在引线框22或铜引线框架两侧的按本发明的堆叠还可以考虑作为用于减小在迄今为止已知的QFN壳体的情况下的热应力的补偿措施。
在图7中现示出了按本发明的无引线封装件34的第一实施例,如其能够在QFN壳体封装件中应用的那样。按照按本发明的实施形式,如其在图7和8所示的那样,通过适当地修改引线框22(引线框架)或其连接区域14能够实现对称的封装结构,该封装结构在无引线壳体10、例如QFN壳体中实现压力补偿或应力补偿。
如图7所示,按照按本发明的实施形式,为减小壳体封装件34中的应力,使引线框(QFN引线框架)22的连接区域(裸芯片焊盘)14升高或上升(负的下移)。在这种情况下在下壳体终端和引线框22的连接区域之间产生的空隙可以用于安装例如一个、两个或更多的半导体元件16,18。在此,半导体元件16,18例如可以并排地和/或相互堆叠地设置或固定在引线框22的连接区域14的上侧和/或下侧上。
无引线封装件34的基本上对称的结构可以由此实现,即,例如在连接区域14的上侧或下侧上设置一样多的半导体元件16,18,也就是说在连接区域14的两侧设置至少一个、两个或更多的半导体元件16,18。但也可以在引线框12的连接区域14的上侧或下侧上设置不一样多的半导体元件16,18。然而,此时连接区域14的每侧上的半导体元件16,18的总高度尽可能地相等或几乎相等,以实现对称性,其中,壳体10的不同材料或元件的变形可以恰当地相互补偿。因此,例如可以在连接区域的一侧上设置一个相对高的ASIC芯片元件,而在另一侧上相互堆叠地设置两个较低的传感器芯片元件。在此,这两个传感器芯片元件的总高度优选尽可能接近ASIC芯片元件的高度,或者连接区域的两侧上的半导体元件的总高度优选基本上一样大或者几乎一样大。通过这种对称形式同样可以实现对由于不同材料等产生的变形的补偿。
带有连接区域(裸芯片焊盘)14的引线框(引线框架)22例如可以在第一步中冲压、切割和/或蚀刻成扁平的部件,而连接区域14接着被向上弯曲或拉深,以便在连接区域14的平面11和连接触头12的平面13之间创造所谓的上升和相应的空隙36或高度错位15。但也可能的是,首先相应的向上拉深或成型连接区域(裸芯片焊盘)14,并创造高度错位15,接着冲压、切割和/或蚀刻出带有连接区域(裸芯片焊盘)14的引线框(引线框架)22。但本发明不限于这些用于带有连接区域14的引线框22的制造方法。
如图7所示,在所述的实施例中,连接区域14例如相对于引线框(引线框架)22的连接区域12错位或升高下面的半导体元件18的高度、例如一个ASIC芯片元件的高度。下面的半导体元件18,也就是在连接区域14下侧上的半导体元件,在此可以形成壳体10在底部的终端并构造成可接近的(如图7所示),或者在底部通过模制物料或浇铸材料包封(未示出)并且因而无法从下面接近。在连接区域14的上侧设置有另一个半导体元件16,例如一传感器芯片元件。在此,两个半导体元件16,18可以通过键合线连接20相互连接。在这种情况下,为了设置在连接区域14的下侧和/或上侧的半导体元件16,18的相应的线键合焊盘区域或者说键合线连接,连接区域14或裸芯片焊盘例如可以稍微更窄地设置(如图7所示)和/或配设一个或多个(未示出的)空隙。
如图7所示,在该例子中,例如一个或两个半导体元件16、18,例如ASIC芯片元件可以通过相应的键合线连接20与一个或多个连接触头12连接。通过连接区域14下侧上的半导体元件18的共同作用,可以与连接区域14或连接面(裸芯片焊盘)的上侧上的另一个硅芯片元件16形成半导体元件16,18的对称的或基本上对称的复合序列。换句话说,可以产生下面的硅芯片元件Si、引线框Cu(在此是铜引线框架)和上面的硅芯片元件Si的复合顺序(Si=>Cu=>Si)。通过这种基本上对称的结构,例如可以在温度变化过程中导致相反的变形或扭曲,这些相反的变形或扭曲可以基本上相互补偿。换句话说,压力或出现的应力可以基本上相互补偿或至少减小。
在此,引线框22的连接区域14的平面11与带有连接触头12的平面13在高度上错位。在此,高度或高度错位15可以任意地改变,这视以下情况而定:在一种相互堆叠中,在连接区域14的下侧上相互堆叠有多少个半导体元件16,18以及单个半导体元件16,18有多高或其总高度有多大。这也适用于所有的按本发明的实施形式。
在图8中示出了按本发明的实施形式的另一实施例。在此,连接区域(裸芯片焊盘)14在高度上这样远地相对引线框(引线框架)22的连接触头12错位或具有这样大的高度错位15,使得设置在连接区域14的下侧上的半导体元件或并排地设置的半导体元件不形成壳体10的底部,而是例如形成塑料制成的模制下端或浇铸物料30。相应的半导体元件16,18可以例如是ASIC芯片元件或传感器芯片元件等等。
如图8所示,通过连接区域14的相应大的上升或相应大的高度错位15(向上偏移)也可以形成模制下端或浇铸材料下端20。在此,连接区域14的平面11和连接触头12的面13之间的高度错位15比图7中所示的大,因而最下面的半导体元件18的底部可以用浇铸物料填充。在此,通过例如在连接区域14的上侧和下侧上设置一样多的半导体元件16,18,能够实现对称或基本上对称的复合序列(就半导体元件的数目而言)。如图7和8所示,在此可以在连接区域14的两侧上设置至少一个或更多的半导体元件16,18。作为关于尺寸对称的或基本上对称的结构的替代方案,也可以在引线框12的连接区域14的上侧和下侧上设置不一样多的半导体元件16,18。但是,半导体元件16,18的总高度作为尺寸在连接区域14的每侧上基本上相等或几乎相等。在此,可以在连接区域14的一侧上设置相对高的ASIC芯片元件,而在另一侧上相互堆叠地设置两个较低的传感器芯片元件。如之前参照图7所述,两个传感器芯片元件在此具有尽可能接近ASIC芯片元件的高度的总高度,或连接区域的两侧上的半导体元件的总高度基本上大小相等或几乎大小相等。
如图8所示,在按本发明的实施例中,可以在引线框Cu(例如铜引线框)的连接区域14的下侧上设置或固定一ASIC芯片元件18(Si),在连接区域14的上侧上设置一硅芯片元件16(Si)。在此,获得了由模制材料或浇铸材料MC、ASIC芯片元件Si、引线框或其连接区域Cu、硅芯片元件Si组成的层的复合封装顺序,并且更新了模制材料或浇铸材料MC、例如塑料的层或分层(MC=>Si=>Cu<=Si<=MC)。
本发明重要的优点在于:所谓的无引线壳体10(如例如QFN壳体)关于其复合堆叠(半导体元件的数目)和/或尺寸(例如总高度)产生了对称的封装件34并且减小或基本上避免壳体10的热变形,其方式是通过对称的结构产生相反的变形,所述相反的变形能够至少部分地或基本上完全地被相互补偿。因此,例如可能在无引线壳体10中出现例如硅芯片元件不希望的强烈挠曲以及例如在传感器芯片元件的情况下由此产生的、不希望的信号飘移。
如图4和5所示,与按本发明的实施形式不同,标准的QFN引线框(引线框架)包括与作为下终端的连接触头或接触焊盘水平相同的高度上的或在同一平面上的连接区域(裸芯片焊盘)。由于不对称的堆叠,也就是说,在这种情况下通过在引线框Cu的一侧上设置两个芯片元件Si(Cu=>Si=>Si)可能导致壳体10的挠曲或变形,原因是材料的热膨胀系数不同以及材料之间缺乏热适配。壳体10和包含在其中的半导体元件16,18、如传感器芯片元件和ASIC芯片元件等等的变形可以导致信号漂移并从而导致不精确。
按照本发明的该实施形式,引线框11、在此例如铜引线框被修改。如图7和8所示,连接区域(裸芯片焊盘)14在制造过程中从连接触头(接触焊盘)12的高度水平向上弯曲出来(向上偏移)。用于此的技术在引线框(引线框架)制造商那里公开,因为如图1和2所示,对于用于全模制壳体10的引线框22执行连接区域14的下沉(向下偏移)。
如附加地在图4中所示,连接区域(裸芯片焊盘)14在QFN引线框(引线框架)22的情况下例如通过连接区域的角上的四个桥接条连接,并且可以非常容易地借助于拉深获得深度错位或高度错位。如图7和8所示,通过按本发明的高度错位(向上偏移),例如为QFN封装件34形成了在作为无引线壳体10下终端的连接触头(接触焊盘)12和连接区域(裸芯片焊盘)14之间的高度水平差15。该空隙36可以用于定位至少一个或多个半导体元件16,18,这些半导体元件以其连接焊盘朝上指向地粘结(Die Atach)在连接区域14上。此外,连接区域几何形状或裸芯片焊盘几何形状的适配对此是有意义的。在此,连接区域几何形状应这样构造,即,例如粘结的半导体元件16,18的连接触头(接触焊盘)12不被覆盖,并且例如可从上方通过键合线连接20接通。
在图7和8所示的两种实施形式中,连接区域(裸芯片焊盘)14例如比一侧或两侧上的半导体元件16,18设计的稍微更窄。在此,半导体元件18例如是ASIC芯片元件,其设置在连接区域14的下侧上。设置在连接区域14的上侧上的第二半导体元件16例如是一传感器芯片元件。然而,本发明不限于这些类型的半导体元件16,18。所述的半导体元件16,18仅仅是示例性的并且用于说明本发明。在该例子中,传感器芯片元件16借助于粘结剂固定在连接区域14上并且与ASIC芯片元件18接触或通过相应的键合线连接20与该ASIC芯片元件连接。因此,形成了例如由在引线框Cu或其连接区域的每侧上的各至少一个半导体元件Si组成的对称的复合序列(Si=>Cu<=Si)。
根据连接区域14相对于连接触头(接触焊盘)12的错位的大小,下面的半导体元件18,在此在图7和8的例子中是ASIC芯片元件,用作下终端(如图7所示),或者配设模制下端或浇铸层30(如图8所示)。模制下端或浇铸层30具有这样的优点,即,其导致压力或应力的进一步减小,因为结构的对称性通过两侧的模制罩或浇铸罩30进一步改进。因此,本发明的主要功能是:通过为引线框(引线框架)22中的连接区域(裸芯片焊盘)14引入高度错位,在无引线壳体10、例如QFN模制壳体中实现对称的或基本上对称的复合顺序(Si=>Cu<=Si)。如前面所述,对称的复合序列可以在QFN封装件34中导致热变形的减小,因为由不同热膨胀系数(如双金属)引起的变形允许相互补偿。因此,按本发明的无引线壳体封装件可以主要在相对敏感的传感器或传感器芯片等以及其它半导体元件的情况下用在无引线壳体、例如QFN壳体中。在此,可以至少减小或基本上防止由于具有不同热膨胀系数的材料缺乏适配造成的信号漂移。这使得传感器将来也可以设置或封装在无引线壳体、如QFN壳体等等中,作为多种使用可能性中的一个例子例如用于汽车中的ESP系统。
Claims (13)
1.一种用于封装半导体元件(16,18)的无引线封装件(34,10)或无引脚封装件,其特征在于,所述无引线封装件(34,10)具有至少两个半导体元件(16,18),所述半导体元件这样地设置在所述无引线封装件(34,10)的引线框(22)的连接区域(14)上,使得在所述半导体元件出现变形的情况下,所述半导体元件(16,18)的变形至少部分地或基本上完全地相互补偿。
2.如权利要求1所述的无引线封装件,其特征在于,所述无引线封装件具有基本上对称的结构或几乎对称的结构。
3.如权利要求1或2所述的无引线封装件,其特征在于,所述无引线封装件(34,10)是QFN壳体封装件。
4.如权利要求1至3之一所述的无引线封装件,其特征在于,所述无引线封装件(34,10)的引线框(22)的连接区域(14)相对所述引线框(22)的连接触头(12)在高度上错位,其中,所述连接区域(14)相对所述引线框(22)的连接触头(12)升高地设置。
5.如权利要求1至4之一所述的无引线封装件,其特征在于,封装件(34,10)的基本上对称的结构在所述无引线封装件的引线框的(22)的连接区域(14)的下侧和上侧上具有一样多的半导体元件(16,18)。
6.如权利要求1至5之一所述的无引线封装件,其特征在于,所述连接区域(14)的一侧上的一个或多个半导体元件的总高度和/或总面积基本上等于或几乎等于相对侧上的一个或多个半导体元件的总高度和/或总面积,其中,所述无引线封装件的引线框(22)的连接区域(14)的两侧上的半导体元件的数量一样大或不一样大。
7.如权利要求1至6中至少之一所述的无引线封装件,其特征在于,在所述引线框(22)的连接区域(14)的上侧和/或下侧上相叠地设置有至少两个半导体元件(16,18)。
8.如权利要求1至7中至少之一所述的无引线封装件,其特征在于,在所述引线框(22)的连接区域(14)的上侧和/或下侧上并排地设置至少两个半导体元件(16,18)。
9.如权利要求1至8中至少之一所述的无引线封装件,其特征在于,所述引线框(22)的连接区域(14)的下侧上的最下面的那个半导体元件(16,18)或最下面的那些半导体元件(16,18)形成所述无引线封装件的下终端,其中,至少一个最下面的半导体元件(18)可从下面接近。
10.如权利要求1至9中至少之一所述的无引线封装件,其特征在于,所述无引线封装件(34,10)在下侧上具有模制层或浇铸层(30),使得至少一个最下面的半导体元件(18)不能从下面接近。
11.如权利要求1至10中至少之一所述的无引线封装件,其特征在于,在所述引线框(22)的连接区域(14)的上侧和下侧上分别设置至少一个半导体元件(16,18),
其中,在所述连接区域(14)的一侧上的半导体元件(16)是传感器芯片元件,而在所述连接区域(14)的另一侧上的半导体元件(18)是ASIC芯片元件,
其中,选择式地在所述传感器芯片元件(16)上设置至少一个附加的半导体元件,例如一个另外的传感器芯片,其中,所述传感器芯片元件和所述至少一个附加的半导体元件的总高度优选基本上等于或几乎等于ASIC芯片元件的总高度。
12.如权利要求1至11中至少之一所述的无引线封装件,其特征在于,所述无引线封装件(34,10)的引线框(12)的连接区域(14)具有至少一个、两个或更多个空隙,用于设置在所述连接区域(14)的下侧和/或上侧上的半导体元件(16,18)的相应的线键合焊盘区域或键合线连接(20)。
13.如权利要求1至12中至少之一所述的无引线封装件,其特征在于,每个半导体元件(16,18)可以是一个芯片元件;一个传感器元件,如硅基底上的微机械传感器元件;一个加速度传感器元件;一个ASIC芯片元件;或一个转速传感器元件。
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DE102012200648B4 (de) | 2012-01-18 | 2020-06-04 | Robert Bosch Gmbh | Sensorvorrichtung |
US9312234B2 (en) * | 2012-05-29 | 2016-04-12 | Nsk Ltd. | Semiconductor module and method for manufacturing the same |
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