CN101740514A - MOS (Metal Oxide Semiconductor) transistor and fabricating method thereof - Google Patents
MOS (Metal Oxide Semiconductor) transistor and fabricating method thereof Download PDFInfo
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Abstract
The invention provides an MOS (Metal Oxide Semiconductor) transistor and a fabricating method thereof. The fabricating method of the MOS transistor comprises the steps of: providing a semiconductor substrate, wherein an active area in the semiconductor substrate comprises a channel area of the MOS transistor; introducing a first ion in the active area of the semiconductor substrate to form an isolation well; introducing a second ion in the active area of the semiconductor substrate to adjust the threshold voltage of an MOS transistor to be formed; and introducing a carbon ion in the channel area of the MOS transistor, wherein the step of the introduction of the carbon ion is carried out before or after the introduction of the first ion, or before or after the introduction of the second ion. Accordingly, the invention also provides an MOS transistor fabricated by the fabricating method. By introducing the carbon ion in the channel area of the MOS transistor, the invention stops ions injected in the channel area of the MOS transistor later from diffusing in a subsequent process for forming a gate dielectric layer by oxidization, thereby achieving the aim of inhibiting the transient enhanced diffusion effect.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly MOS transistor and preparation method thereof.
Background technology
Along with transistor gate length continue dwindle, oxidation-enhanced diffusion (Oxidation-EnhancedDiffusion, OED) become the key factor that influences boron ion and phosphonium ion diffusion, because OED effect, caused transient enhanced diffusion effect (TED), and the transient enhanced diffusion effect not only causes transistorized short-channel effect, and influences transistor channel mobility, junction capacitance and junction leakage.
Prior art discloses a kind of utilization and has injected the diffusion of carbon-based group (carbon cluster) formation shallow junction with the interior boron ion of source, the drain electrode of oxide-semiconductor control transistors, injection carbon-based group by high dose is to form stress in silicon substrate, particular content is described in detail below with reference to Fig. 1 to 2.
Fig. 1 comprises: the n trap 81 and the P trap 82 that are arranged in Semiconductor substrate for the cross-sectional view that is injected with the carbon ion group in forming cmos device of prior art; Be arranged in the isolation structure 85 of Semiconductor substrate; Be positioned at gate dielectric layer 84 and gate electrode 83 on the Semiconductor substrate, in addition, photoresist mask layer 86 is formed at the PMOS zone.
At first, carbon ion group 88 is infused in the not zone of mask, and this injection zone will become the drain electrode extension area of nMOS, injects the degree of depth and is generally 20～50nm or lower, and the dosage range of the carbon ion of described injection is 3E14 to 2E15cm
-2, this dosage will make the injection region decrystallized, and carbon is mixed silicon.
Then,, provide the cross-sectional view that forms n channel drain extension area 89, form by injecting n type group 88 with reference to Fig. 2.
Technology subsequently also is included in the nMOS zone and forms photoresist mask layer, injects p type group formation pMOS transistor drain extension area and form the transistorized source of nMOS/drain electrode respectively and the transistorized source of pMOS/drain electrode in the pMOS zone, does not add at this to be described in detail.
In being the U.S. Patent application of US11/634565, application number can also find more information relevant with technique scheme.
In technique scheme, by before forming the transistorized source of nMOS/drain electrode extension area, injecting carbon ion with the inhibition source/P atom of drain electrode extension area injection or the diffusion of As atom, its basic principle is: owing to can produce the clearance-type defective in polysilicon gate oxidation and source/drain region ion implantation technology, and the carbon ion that injects can adsorb these clearance-type defectives, has reached inhibition TED purpose like this.In existing formation MOS transistor technology, usually need in raceway groove, inject ion to regulate transistorized threshold voltage, the ion of this injection is generally the boron ion for the nMOS transistor, be generally phosphonium ion for the pMOS transistor, the step that carbon ion in the technique scheme injects fail to play suppress that above-mentioned raceway groove injects and growth of gate oxide layer to form the problem that source/drain electrode extension areas such as gate dielectric layer form the defective that preceding technology caused, because the existence of these defectives and low temperature process process subsequently, can cause the enhancing diffusion of channel region impurity, influence the control and the coupling of transistorized threshold voltage.
Summary of the invention
The problem that the present invention solves provides a kind of MOS transistor and preparation method thereof, to suppress the transient enhanced diffusion effect that oxidation-enhanced diffusion causes.
For addressing the above problem, the invention provides a kind of manufacture method of MOS transistor, comprising: Semiconductor substrate is provided, and described Semiconductor substrate is divided into the different active areas of MOS transistor to be formed, and described active area comprises the channel region of MOS transistor; In active area of semiconductor substrate, introduce first ion, form isolation well; In active area of semiconductor substrate, introduce second ion, to adjust the threshold voltage of MOS transistor to be formed; Also comprise: in the channel region of MOS transistor, introduce carbon ion.
Described introducing carbon ion step is carried out after introducing the first ion step.
Described introducing carbon ion injects by ion and carries out.
Described injection carbon ion depth bounds is 5nm to 50nm.
The energy range of described injection carbon ion is for being lower than 20KeV, and the dosage range of described injection carbon ion is 1E12 to 1E14cm
-2, angular range is 0 to 9 °.
Correspondingly, the present invention also provides a kind of MOS transistor, comprising: Semiconductor substrate, described Semiconductor substrate are divided into the different active areas of MOS transistor to be formed, and described active area comprises the channel region of MOS transistor; Isolation well is positioned at active area of semiconductor substrate, and described isolation well forms by introducing first ion; The second ion district is positioned at active area of semiconductor substrate, is used to adjust the threshold voltage of MOS transistor to be formed; Also comprise: the carbon ion district is positioned at the channel region of MOS transistor.
Described carbon ion district forms after introducing first ion formation isolation well.
Inject by ion and form in described carbon ion district.
The depth bounds of the injection carbon ion in described formation carbon ion district is 5nm to 50nm.
The energy range of the injection carbon ion in described formation carbon ion district is for being lower than 20KeV, and the dosage range of described injection carbon ion is 1E12 to 1E14cm
-2, angular range is 0 to 9 °.
Compared with prior art, the technical program has the following advantages: by introduce carbon ion in the channel region of MOS transistor, utilize " gettering " effect of carbon ion, stop the follow-up ion that is used for adjusting the MOS transistor threshold voltage that in the channel region of MOS transistor, injects to form gate dielectric layer technology and spread, strengthen the diffusion effect purpose thereby reach transient suppression in follow-up oxidation.
Also the energy range by optimizing carbon ion is for being lower than 20KeV for the technical program, and the dosage range of described injection carbon ion is 1E12 to 1E14cm
-2, can prevent owing to injecting the excessive higher junction leakage that causes of carbon ion damage.
Description of drawings
Fig. 1 is the cross-sectional view that is injected with the carbon ion group in the formation cmos device of prior art;
Fig. 2 is the cross-sectional view of the formation n channel drain extension area of prior art;
Fig. 3 is the schematic flow sheet of the formation MOS transistor of one embodiment of the present of invention;
Fig. 4 to Fig. 8 is the cross-sectional view of the formation MOS transistor of one embodiment of the present of invention;
Fig. 9 is the carbon ion dosage of injection of formation MOS transistor of the present invention and the relation between the junction capacitance;
Figure 10 is the carbon ion energy of injection of formation MOS transistor of the present invention and the relation between the junction capacitance;
Figure 11 is the relation of formation nMOS transistor of the present invention between various dose threshold voltages and saturated drain current;
Figure 12 is the relation of formation nMOS transistor of the present invention between different-energy threshold voltages and saturated drain current.
Embodiment
Below describe specific embodiment in detail by the foundation accompanying drawing, above-mentioned purpose and advantage of the present invention will be clearer:
The present invention at first provides a kind of manufacture method of MOS transistor, specifically please refer to Fig. 1, comprise: execution in step S11, Semiconductor substrate is provided, be formed with isolation structure in the described Semiconductor substrate, described isolation structure is divided into the different active areas of MOS transistor to be formed with Semiconductor substrate, and described active area comprises the channel region of MOS transistor; Execution in step S13 introduces first ion in active area of semiconductor substrate, form isolation well; Execution in step S15 introduces second ion, to adjust the threshold voltage of MOS transistor to be formed in active area of semiconductor substrate; Execution in step S17 introduces carbon ion in the channel region of MOS transistor.
Described introducing carbon ion step is before introducing first ion or afterwards or before introducing second ion or carry out afterwards.Preferably after introducing the first ion step, carry out.
Describe formation MOS transistor technology of the present invention in detail below in conjunction with Fig. 4 to 8, in the present embodiment, carrying out after introducing the first ion step with described introducing carbon ion step is example.
At first with reference to Fig. 4, Semiconductor substrate 100 is provided, be formed with isolation structure 101 in the described Semiconductor substrate 100, described isolation structure 101 is divided into the different active areas (unmarked) of MOS transistor to be formed with Semiconductor substrate 100, and described active area comprises the channel region of MOS transistor.Also be formed with pad oxide 103 on the described Semiconductor substrate 100.
In the active area of Semiconductor substrate 100, introduce first ion, form isolation well 102.The kind of the MOS transistor that described first ion and this active area are to be formed is relevant, if the channel type of MOS transistor to be formed is the n type, then first ion is the p type, such as being generally the boron ion; If the channel type of MOS transistor to be formed is the p type, then first ion is the n type, such as being generally phosphonium ion.
Usually, forming isolation well 102 forms by injecting first ion.
Since form described isolation well purpose between the semiconductor device that will form on the Semiconductor substrate 100 and and Semiconductor substrate 100 between isolate, in isolation well 102, form semiconductor device then, therefore form the conduction type and the conductivity type opposite of Semiconductor substrate 100 of first ion of the injection of isolation well 102 so that and between the Semiconductor substrate 100 the formation PN junction isolate.
Simultaneously, the structure of isolation well 102 can also comprise multiple, be not limited to illustrated single isolation well 102 structures in the present embodiment, can be the triple-well structure, such as: if Semiconductor substrate is the p type, then can injects n type ion and form first isolation well, can form p type MOS transistor in this first isolation well, nMOS transistor area in first isolation well is injected p type ion then, forms second isolation well, forms n type MOS transistor then in this second isolation well.
With reference to Fig. 5, for introduce the cross-sectional view of carbon ion in the channel region of MOS transistor, in the present embodiment, described introducing carbon ion step is carried out after introducing first ion.
Technical scheme of the present invention forms based on following know-why: the present inventor finds, when introduce second ion in the channel region of follow-up MOS transistor in Semiconductor substrate 100, in order to the threshold voltage of adjusting MOS transistor in, introducing second ion always upsets the atomic arrangement of former this rule in the Semiconductor substrate 100, form various defectives and comprise interstitial atom, and the existence of these defectives can make second ion diffusion in the technology of follow-up thermal oxidation formation gate dielectric of introducing accelerate.The present inventor also finds, the carbon ion that in the channel region of MOS transistor, injects, can form cluster with the defective reaction, play the effect of deciding bundle (trap) impurity, so just reduced free defective, some defectives of introducing in the channel region can be attracted around it, form irregular lattice arrangement in the part, and can make atomic arrangement more regular on the whole, lattice is more perfect, therefore the scattering that is subjected to of electronics reduces, thereby makes the second ions diffusion rate of introducing reduce, and reduces or has avoided because the transient enhanced diffusion effect that oxidation causes.
Simultaneously the present inventor also finds, the carbon ion of too high dose or energy injects also can bring too much defective, thereby causes that higher interband satisfies the leakage electric current, therefore the condition of injecting carbon ion need be optimized.
In the embodiments of the invention, described introducing carbon ion injects by ion and carries out, and the depth bounds of described injection carbon ion is 5nm to 50nm.The energy range of described injection carbon ion is for being lower than 20KeV, and the dosage range of described injection carbon ion is 1E12 to 1E14cm
-2, angular range is 0 to 9 °.The source of above-mentioned optimized parameters is according to the relevant description that please refer to hereinafter.
In practical semiconductor technology, this implantation step can directly adopt the mask plate that forms above-mentioned isolation well 102, promptly the carbon ion of Zhu Ruing can be not limited to the channel region of MOS transistor to be formed, can not bring ill effect even be injected into the source/drain extension region of raceway groove both sides yet, on the contrary, according to aforesaid prior art, be infused in source/drain extension region and can also play the effect that reduces the junction capacitance between source/leakage and the Semiconductor substrate.
As one embodiment of the present of invention, the energy of described injection carbon ion is 5KeV, and the degree of depth of described injection carbon ion is 10nm, and the dosage of described injection carbon ion is 1E14cm
-2
As an alternative embodiment of the invention, the degree of depth of described injection carbon ion is 25nm.The energy range of described injection carbon ion is 10KeV, and the dosage of described injection carbon ion is 2E13cm
-2
As another embodiment of the present invention, the degree of depth of described injection carbon ion is 40nm.The energy of described injection carbon ion is 15KeV, and the dosage of described injection carbon ion is 1E12cm
-2
Through above-mentioned optimization, can prevent owing to injecting the higher junction leakage that carbon ion causes.Specifically please refer to the curved line relation between the energy of carbon ion of relevant injection hereinafter and dosage and junction capacitance, the junction leakage.
Inject after the carbon ion, form carbon ion district 104 in the channel region of the MOS transistor in isolation well 102.Simultaneously, under the condition that does not influence technique effect of the present invention, this carbon ion district 104 also extends in the source/drain extension region of raceway groove both sides.
Then, with reference to Fig. 6, in the active area of Semiconductor substrate 100, introduce second ion, to adjust the threshold voltage of MOS transistor to be formed.Usually, introducing second ion at active area forms by injecting.
Equally in this step, in fact can directly adopt the mask plate that forms isolation well, second ion that promptly works the injection of adjusting the threshold voltage effect can be not limited to only be infused in the channel region of MOS transistor to be formed, can not bring ill effect equally even be injected into the source/drain extension region of raceway groove both sides.
Described second ion is different and different according to MOS transistor kind to be formed, if the channel type of MOS transistor to be formed is the n type, then second ion is the p type, such as being boron ion or indium ion; If the channel type of MOS transistor to be formed is the p type, then second ion is the n type, such as being phosphonium ion or arsenic ion.
Inject after second ion, form the second ion district 105 in the channel region of the MOS transistor in isolation well 102.Simultaneously, this second ion district 105 also extends in the source/drain extension region of raceway groove both sides.
With reference to Fig. 7, technology subsequently comprises: remove pad oxide 103; On Semiconductor substrate 100, form gate dielectric layer 106 and polysilicon layer 107.
With reference to Fig. 8, etching gate dielectric layer 106 and polysilicon layer 107 form grid structure; In Semiconductor substrate 100,105 formation source, the second ion district, grid structure both sides/drain electrode extension area; Form side wall in the grid structure both sides; Formation source/drain electrode 108 in Semiconductor substrate 100, forming described these structures is those skilled in the art's known technology, does not add detailed description at this.
In the present embodiment; described introducing carbon ion step carries out promptly forming after forming isolation well after introducing first ion; because in actual process; usually when forming gate dielectric layer, just in semiconductor technology, introduce the annealing of first road; therefore on the introducing carbon ion principle among the present invention can any step before forming gate dielectric layer carry out all can, should too much not limit protection scope of the present invention at this.But, can form noncrystalline state in the injection region owing to inject carbon ion, and this amorphous state helps stoping the diffusion of second ion that injects subsequently, so the technical scheme of comparative optimization is that the carbon ion implantation step carried out before the second ion implantation step.
Form MOS transistor of the present invention through above-mentioned technology, comprise: Semiconductor substrate 100, be formed with isolation structure 101 in the described Semiconductor substrate 100, described isolation structure 101 is divided into the different active areas of MOS transistor to be formed with Semiconductor substrate 100, and described active area comprises the channel region of MOS transistor; Isolation well 102 is positioned at the active area of Semiconductor substrate 100, and introducing in the described isolation well 102 has first ion; The second ion district 105 is used to adjust the threshold voltage of MOS transistor to be formed; Also comprise: carbon ion district 104 is positioned at the channel region of MOS transistor.
Described carbon ion district before introducing first ion or afterwards, before perhaps follow-up introducing second ion processes or carry out afterwards, preferably introduce first ion form isolation well after formation.
Inject by ion and carry out in described carbon ion district.
The depth bounds of the injection carbon ion in described formation carbon ion district is 5nm to 50nm.
The energy range of the injection carbon ion in described formation carbon ion district is for being lower than 20KeV, and the dosage range of described injection carbon ion is 1E12 to 1E14cm
-2, angular range is 0 to 9 °.
Respectively semiconductor device of the present invention is simulated under TSUPREM4 in the TCAD simulation softward of employing U.S. Si Nuofeisi (Synopsys) company and the MEDICI environment.The process conditions of simulation are 65nm, and Semiconductor substrate is a silicon.
Fig. 9 is the carbon ion dosage of injection of formation MOS transistor of the present invention and the relation between the junction capacitance, and energy is fixed as 10KeV; Figure 10 is the carbon ion energy of injection of formation MOS transistor of the present invention and the relation between the junction capacitance, and dosage is fixed as 2.6E13cm
-2As can be seen, junction capacitance is along with the dosage and the energy that inject all change, and junction capacitance increases along with the dosage that injects subtracts afterwards earlier, along with increasing afterwards earlier, the energy that injects subtracts, therefore, the present invention optimizes energy and dosage according to this characteristic, and the dosage range of choosing is for being lower than 1E12 to 1E14cm
-2, energy range is for being lower than 20KeV, and junction leakage is lower in this scope, can effectively suppress short-channel effect and anti-short-channel effect (RSCE).
Figure 11 is the relation of formation nMOS transistor of the present invention between various dose threshold voltages (Vth) and saturated drain current (Idsat), and wherein, the performance of the MOS transistor of carbon ion is not injected in the chain-dotted line representative; All the other represent implantation dosage respectively is 5E12,1E13,1E14,3E14,1E15cm
-2MOS transistor (various patterns and corresponding implantation dosage thereof in Figure 11 mark), the energy that injects is 5KeV, as can be seen, on the whole, the threshold voltage vt h of the MOS transistor behind the injection carbon ion is along with the variation of drain saturation current Idsat tends towards stability, and the threshold voltage vt h that does not inject the MOS transistor of carbon ion changes along with the variation of drain saturation current Idsat obviously, it can be said that bright injection carbon ion can effectively suppress short-channel effect and anti-short-channel effect (RSCE), so the performance of MOS transistor is much relatively stable.
In addition, as seen from Figure 11, when the dosage that injects at 5E12～1E14cm
-2Between, the threshold voltage vt h of MOS transistor changes very little, and more than or equal to 1E14cm
-2Adverse effect is apparent in view afterwards, the threshold voltage of MOS transistor is along with the variation tendency of drain saturation current Idsat increases again, illustrate that excessive dosage can cause the implant damage that can't repair, can adsorb the advantageous effect of defective thereby offset the injection carbon ion, prove the necessity of above-mentioned optimized process conditions equally.
Figure 12 is the relation of formation nMOS transistor of the present invention between different-energy threshold voltages (Vth) and saturated drain current (Idsat).The Energy distribution of injecting is 5,10,15,25KeV, and the dosage of injection is fixed as 1.0E14cm
-2(various patterns and corresponding injection energy thereof such as Figure 12 mark), as can be seen, when the energy that injects reaches 25KeV, the threshold voltage vt h of MOS transistor is along with the variation tendency of drain saturation current Idsat increases again, illustrate that excessive carbon energy also can cause the implant damage that can't repair, thereby offset the injection carbon ion and can adsorb the advantageous effect of defective, the energy-optimised generation that in being lower than the 20KeV scope, can avoid above-mentioned situation of injection of the present invention.
Simultaneously, by Figure 11 and Figure 12 as can be seen, variation has still taken place (under this experiment condition in threshold voltage after injecting carbon ion under the different drain saturation currents a little, all decrease), but with respect to strengthening diffusion effect by inject the transient suppression that carbon ion brought at channel region, this variation can be ignored comparatively speaking, still more, this variations in threshold voltage can be injected and remedies by adjusting follow-up second ion that is used to adjust threshold voltage.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. the manufacture method of a MOS transistor comprises:
Semiconductor substrate is provided, and described Semiconductor substrate is divided into the different active areas of MOS transistor to be formed, and described active area comprises the channel region of MOS transistor;
In active area of semiconductor substrate, introduce first ion, form isolation well;
In active area of semiconductor substrate, introduce second ion, to adjust the threshold voltage of MOS transistor to be formed;
It is characterized in that, also comprise:
In the channel region of MOS transistor, introduce carbon ion.
2. the manufacture method of MOS transistor according to claim 1, described introducing carbon ion step is carried out after introducing the first ion step.
3. the manufacture method of MOS transistor according to claim 1 and 2, described introducing carbon ion are injected by ion and are carried out.
4. the manufacture method of MOS transistor according to claim 3, described injection carbon ion depth bounds is 5nm to 50nm.
5. the manufacture method of MOS transistor according to claim 3, the energy range of described injection carbon ion is for being lower than 20KeV, and the dosage range of described injection carbon ion is 1E12 to 1E14cm
-2, angular range is 0 to 9 °.
6. MOS transistor comprises:
Semiconductor substrate is divided into the different active areas of MOS transistor to be formed in the described Semiconductor substrate, described active area comprises the channel region of MOS transistor;
Isolation well is positioned at active area of semiconductor substrate, and described isolation well forms by introducing first ion;
The second ion district is positioned at active area of semiconductor substrate, is used to adjust the threshold voltage of MOS transistor to be formed;
It is characterized in that, also comprise:
The carbon ion district is positioned at the channel region of MOS transistor.
7. MOS transistor according to claim 6, described carbon ion district forms after introducing first ion formation isolation well.
8. according to claim 6 or 7 described MOS transistor, inject by ion and form in described carbon ion district.
9. MOS transistor according to claim 8, the depth bounds of the injection carbon ion in described formation carbon ion district is 5nm to 50nm.
10. MOS transistor according to claim 8, the energy range of the injection carbon ion in described formation carbon ion district is for being lower than 20KeV, and the dosage range of described injection carbon ion is 1E12 to 1E14cm
-2, angular range is 0 to 9 °.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102737965A (en) * | 2011-04-12 | 2012-10-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of Halo structure |
| CN109728071A (en) * | 2017-10-30 | 2019-05-07 | 台湾积体电路制造股份有限公司 | It is doped with the semiconductor devices of conductive component |
| CN111863607A (en) * | 2020-07-28 | 2020-10-30 | 哈尔滨工业大学 | Radiation-resistant power transistor and preparation method thereof |
| CN111863606A (en) * | 2020-07-28 | 2020-10-30 | 哈尔滨工业大学 | Radiation-resistant power transistor and preparation method thereof |
| US11764296B2 (en) * | 2017-10-20 | 2023-09-19 | Infineon Technologies Austria Ag | Method for manufacturing a semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100483665C (en) * | 2006-02-20 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor isolating structure and its forming method |
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2008
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102737965A (en) * | 2011-04-12 | 2012-10-17 | 中芯国际集成电路制造(上海)有限公司 | Formation method of Halo structure |
| US11764296B2 (en) * | 2017-10-20 | 2023-09-19 | Infineon Technologies Austria Ag | Method for manufacturing a semiconductor device |
| CN109728071A (en) * | 2017-10-30 | 2019-05-07 | 台湾积体电路制造股份有限公司 | It is doped with the semiconductor devices of conductive component |
| US11450741B2 (en) | 2017-10-30 | 2022-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Doping for semiconductor device with conductive feature |
| US11742386B2 (en) | 2017-10-30 | 2023-08-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Doping for semiconductor device with conductive feature |
| CN111863607A (en) * | 2020-07-28 | 2020-10-30 | 哈尔滨工业大学 | Radiation-resistant power transistor and preparation method thereof |
| CN111863606A (en) * | 2020-07-28 | 2020-10-30 | 哈尔滨工业大学 | Radiation-resistant power transistor and preparation method thereof |
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