CN101673682A - Method for etching wafer - Google Patents
Method for etching wafer Download PDFInfo
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- CN101673682A CN101673682A CN200910196450A CN200910196450A CN101673682A CN 101673682 A CN101673682 A CN 101673682A CN 200910196450 A CN200910196450 A CN 200910196450A CN 200910196450 A CN200910196450 A CN 200910196450A CN 101673682 A CN101673682 A CN 101673682A
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- silicon oxide
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Abstract
The invention provides a method for etching a wafer. The wafer is sequentially provided with a substrate layer, a basic component layer and a second component layer, wherein the second component layerand the basic component layer are separated by a silicon oxide layer, and the periphery of the second component layer and the surface of the basic component layer which is not covered by the second component layer are also covered with the silicon oxide layers. The method comprises the following steps: implanting ions at the surfaces of the silicon oxide layers; etching the silicon oxide layers in a wet method and stopping at the upper surface of the basic component layer. In the method provided by the invention, the structure of the silicon oxide surface layer is loose by injecting the ionsinto the silicon oxide layers in a directional way, the etching rate is quickened, and the original etching rate is kept as the ions are not injected into the side wall, thus quickening the time of anetching procedure and reducing the erosion degree of the longitudinal side wall of silicon oxide.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process flow process, more relate to a kind of method that in wet-etching technology, reduces the sidewall erosion degree.
Background technology
As shown in Figure 1a, in the manufacture craft of wafer (wafer), at first on basalis 11, form basic device layer 12 and silicon oxide layer 13 successively, on partial oxidation silicon layer 13, form second device layer 14 then, cover one deck silicon oxide layer 13 in second device layer, 14 peripheries again, thereby form the surperficial lobed device architecture shown in the figure.
Wherein, having one or more layers device that forms in the basic device layer 12 in technology before, be used for carrying out function corresponding in the follow-up wafer of making, for example can be transistorized source-drain area.
For the needs of subsequent technique, the method that utilize etching is removed unnecessary silicon oxide layer 13, thereby the upper surface that reaches basic device layer 12 is exposed to the purpose of silicon oxide layer 13, but second device layer 14 of silicon oxide layer 13 inside can not incur loss.
The method of etching is just like the wet etching of the liquid state shown in Fig. 1 b, and the dry etching based on plasma of the gaseous state shown in Fig. 1 c.These two kinds of lithographic methods exist shortcoming separately:
Though dry etching has anisotropy, can control the degree of vertical and horizontal etching,, there is the problem of over etching in dry etching, and under the not etched industrial requirements of basic device layer 12, dry etching obviously can't reach requirement.
There is not the problem of over etching in wet etching, but, wet etching is isotropic, when silicon oxide layer 13 is etched in the vertical, the silicon oxide layer 13 that covered of second device layer, 14 sidewalls also be etched (being that sidewall corrodes) transversely, make silicon oxide layer 13 transverse width d1 reduce greatly, become the d2 among Fig. 1 b.Under wet etching, reducing significantly of silicon oxide layer 13 transverse widths can cause the transverse width d3 of second device layer 14 also to be reduced simultaneously, and second device layer 14 can sustain damage.
Summary of the invention
The present invention proposes a kind of method that reduces the silicon oxide side wall erosion degree in wet-etching technology, can address the above problem.
In order to achieve the above object, the invention provides a kind of method for etching wafer, wafer has basalis, basic device layer and second device layer successively, adopt silicon oxide layer to separate between second device layer and the basic device layer, and the periphery of second device layer and the basic device layer surface that is not covered by second device layer also are coated with silicon oxide layer, said method comprising the steps of: ion is carried out on the silicon oxide layer surface implant; Silicon oxide layer is carried out wet etching, stop at basic device layer upper surface.
Optionally, wherein in this ion implantation step, wherein in this ion implantation step, implantation be argon ion.
Optionally, wherein the injection energy of this argon ion is that 2keV, concentration are 2E15/cm
2
Optionally, wherein in this ion implantation step, implantation be arsenic ion.
Optionally, wherein in this ion implantation step, implant along carry out ion perpendicular to the direction on silicon oxide layer surface.
Optionally, wherein in the wet etching step, the hydrofluoric acid that adopts dilution is as etching solution.
The technology that the present invention proposes, by injecting ion to the silicon oxide layer orientation, make the silica surface structure loose, etch rate accelerates, top layer transversely is not owing to inject ion, keep original etch rate, thereby accelerated the time of etching procedure, reduced the sidewall erosion degree of silicon oxide layer.
Description of drawings
Fig. 1 a～1c is depicted as and adopts existing method the silicon oxide layer of wafer surface to be carried out the effect schematic diagram of etching;
Fig. 2 a～Fig. 2 d is depicted as the process schematic diagram that in the preferred embodiment of the present invention wafer is carried out etching;
Figure 3 shows that the processing step that in the preferred embodiment of the present invention wafer is carried out etching.
Embodiment
In order more to understand technology contents of the present invention, especially exemplified by specific embodiment and cooperate appended graphic being described as follows.
Fig. 2 a～Fig. 2 d is depicted as the process schematic diagram that in the preferred embodiment of the present invention wafer is carried out etching; Figure 3 shows that the processing step that in the preferred embodiment of the present invention wafer is carried out etching.
Shown in Fig. 2 a for carrying out the wafer schematic diagram before the wet-etching technology with stepped section.Wafer is bottom-up to have basalis 21, basic device layer 22, silicon oxide layer 23 and second device layer 24 successively.
Have one or more layers device that in technology before, forms in the device layer 22 of basis, be used in the follow-up wafer of making, carrying out function corresponding.
According to background technology as can be known, among Fig. 2 a, the silicon oxide layer sidewall 231 that covers second device layer, 24 sides is thinner, if directly carry out wet etching, can damage second device layer 24 in the silicon oxide layer sidewall 231 because of lateral corrasion, for this reason, preferred embodiment of the present invention proposes following method, to avoid the problems referred to above.
At first, shown in Fig. 2 b,, promptly, the step that ion is implanted, i.e. step S301 are carried out in the surface of silicon oxide layer 23 perpendicular to the direction of silicon oxide layer 23 along the direction of the sidewall 231 of silicon oxide layer 23.Ion herein for example is argon ion (Ar
+), arsenic ion (As
+) waiting heavier ion, preferable in the present embodiment is argon ion, the implantation of argon ion can make that the surface structure of silicon oxide layer 23 is loose, can improve the etch rate of subsequent oxidation silicon layer 23 when wet etching.
The injection energy of argon ion is that 2keV, concentration are 2E15/cm in the present embodiment
2Particularly, the energy of argon ion depends on the thickness of silicon oxide layer 23, and the injection energy span of argon ion is 0.1KeV～100KeV; The concentration of argon ion (perhaps dosage) is big more, and is many more to the raising of silicon oxide layer 23 etch rates, and the concentration span of argon ion can be 1E12/cm
2～2E16/cm
2
In addition, argon ion is implanted has directivity, and in the step that argon ion is implanted, the restriction argon ion is only along the top layer of implanting silicon oxide layer 23 perpendicular to the direction of silicon oxide layer 23.Like this, argon ion is not implanted in the sidewall 231 of silicon oxide layer 23, does not change the etch rate of sidewall 231 when wet etching yet.
Then, execution in step S302 carries out wet etching to the wafer of handling through step S301.Shown in Fig. 2 c.Wafer is placed in the hydrofluoric acid of dilution, and the sidewall of silicon oxide layer 23 can react with different etch rates in hydrofluoric acid with the bottom.
The present invention does not have specific (special) requirements for the concentration of hydrofluoric acid, and the concentration of hydrofluoric acid can be regulated according to etching speed of wanting to reach or the thickness of desiring the silicon oxide layer of etching.
In certain density hydrofluoric acid, the ratio that carried out the etch rate of silicon oxide layer 23 vertical direction that argon ion injects and horizontal direction is about 1.5: 1～and 4: 1, these ratios depend on the implantation dosage and the concentration of argon ion in step S301.
The degree of control etching when etching into basic device layer 22 upper surfaces on vertically, stops etching, takes out wafer.
The chip architecture that etching is finished is shown in Fig. 2 d, implant on the direction at argon ion, because this a part of surface structure of silicon oxide layer 23 is comparatively loose, in etching process, can react with etching solution quickly, so the degree that this a part of top layer is etched is heavier.And the sidewall 231 of silicon oxide layer 23, owing in step S301, there is not implanted ion, therefore it has kept original etch rate, than that part of top layer that is placed into ion, etch rate is obviously lower, therefore the etching degree is lighter, thereby can make second device layer 24 not contaminated and damage in etching process of silicon oxide layer 23 inside.
The present invention has adjusted the sidewall of silicon oxide layer and the etch rate between other surfaces by implanting ions directionally to silicon oxide layer, reached to keep the silicon oxide layer transverse width, with the transversely not impaired purpose of assurance silicon oxide layer internal components as far as possible.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (6)
1. method for etching wafer, described wafer has basalis, basic device layer and second device layer successively, adopt silicon oxide layer to separate between described second device layer and the basic device layer, and the periphery of described second device layer and the basic device layer surface that is not covered by second device layer also are coated with silicon oxide layer, it is characterized in that, said method comprising the steps of:
Ion is carried out on the silicon oxide layer surface to be implanted;
Silicon oxide layer is carried out wet etching, stop at basic device layer upper surface.
2. method for etching wafer according to claim 1 is characterized in that, wherein in this ion implantation step, implantation be argon ion.
3. method for etching wafer according to claim 2 is characterized in that, wherein the injection energy of this argon ion is that 2keV, concentration are 2E15/cm
2
4. method for etching wafer according to claim 1 is characterized in that, wherein in this ion implantation step, implantation be arsenic ion.
5. method for etching wafer according to claim 1 is characterized in that, wherein in this ion implantation step, implants along carry out ion perpendicular to the direction on silicon oxide layer surface.
6. method for etching wafer according to claim 1 is characterized in that, wherein in the wet etching step, the hydrofluoric acid that adopts dilution is as etching solution.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101964501A CN101673682B (en) | 2009-09-25 | 2009-09-25 | Method for etching wafer |
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|---|---|---|---|
| CN2009101964501A CN101673682B (en) | 2009-09-25 | 2009-09-25 | Method for etching wafer |
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| CN101673682A true CN101673682A (en) | 2010-03-17 |
| CN101673682B CN101673682B (en) | 2012-07-04 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243998A (en) * | 2010-05-14 | 2011-11-16 | 三美电机株式会社 | Method of manufacturing semiconductor device |
| CN102437051A (en) * | 2011-11-24 | 2012-05-02 | 上海华力微电子有限公司 | Silicide stop layer etching method and through-hole etching stop layer forming method |
| CN102956562A (en) * | 2011-08-22 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Memory device forming method |
| CN104143515A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | Method for forming MOS transistor |
| CN105304632A (en) * | 2014-07-01 | 2016-02-03 | 台湾积体电路制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN105810607A (en) * | 2016-04-21 | 2016-07-27 | 苏州能屋电子科技有限公司 | Method and system for realizing P-type nitride enhanced HEMT (High Electron Mobility Transistor) through in-situ etching monitoring |
| CN109148374A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
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| WO2017009964A1 (en) * | 2015-07-15 | 2017-01-19 | 三菱電機株式会社 | Method for producing semiconductor device |
Family Cites Families (3)
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| US20070238254A1 (en) * | 2006-03-28 | 2007-10-11 | Applied Materials, Inc. | Method of etching low dielectric constant films |
| CN100468650C (en) * | 2006-04-12 | 2009-03-11 | 中芯国际集成电路制造(上海)有限公司 | Making method of semiconductor memory part |
| CN101197264B (en) * | 2007-12-25 | 2013-01-09 | 上海集成电路研发中心有限公司 | Forming method of L-shaped side wall |
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2009
- 2009-09-25 CN CN2009101964501A patent/CN101673682B/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243998A (en) * | 2010-05-14 | 2011-11-16 | 三美电机株式会社 | Method of manufacturing semiconductor device |
| CN102956562A (en) * | 2011-08-22 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Memory device forming method |
| CN102956562B (en) * | 2011-08-22 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Memory device forming method |
| CN102437051A (en) * | 2011-11-24 | 2012-05-02 | 上海华力微电子有限公司 | Silicide stop layer etching method and through-hole etching stop layer forming method |
| CN104143515A (en) * | 2013-05-09 | 2014-11-12 | 中芯国际集成电路制造(上海)有限公司 | Method for forming MOS transistor |
| CN105304632A (en) * | 2014-07-01 | 2016-02-03 | 台湾积体电路制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN105810607A (en) * | 2016-04-21 | 2016-07-27 | 苏州能屋电子科技有限公司 | Method and system for realizing P-type nitride enhanced HEMT (High Electron Mobility Transistor) through in-situ etching monitoring |
| CN105810607B (en) * | 2016-04-21 | 2018-06-22 | 苏州能屋电子科技有限公司 | Pass through the method and system in situ for etching monitoring and realizing the enhanced HEMT of p-type nitride |
| CN109148374A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN109148374B (en) * | 2017-06-28 | 2021-04-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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|---|---|
| CN101673682B (en) | 2012-07-04 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |