CN109148374B - Method for manufacturing semiconductor device - Google Patents
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- CN109148374B CN109148374B CN201710509360.8A CN201710509360A CN109148374B CN 109148374 B CN109148374 B CN 109148374B CN 201710509360 A CN201710509360 A CN 201710509360A CN 109148374 B CN109148374 B CN 109148374B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a first dummy gate structure is formed on the semiconductor substrate of the first region, and the first dummy gate structure comprises a first dummy gate electrode layer; performing ion implantation to modify the first dummy gate electrode layer; and removing the first dummy gate electrode layer by using a dry etching process to form a first groove, wherein the side wall of the first groove is vertical to the bottom. According to the manufacturing method of the semiconductor device, the side wall of the groove formed after the pseudo gate electrode layer is removed is vertical to the bottom, so that the corner effect caused by the inclined side wall is avoided, and the yield of the semiconductor device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
When the nodes of the semiconductor process reach 28nm and below, replacing the conventional silicon oxynitride or silicon oxide dielectric layer/polysilicon gate structure with a high-k dielectric layer/metal gate structure is considered as a main or even only method for solving the problems of the conventional gate structure, which mainly include gate leakage, polysilicon loss and boron penetration caused by a thin gate silicon oxide dielectric layer.
For transistor structures with higher process nodes, the high-k metal gate process is usually a gate-last (gate-last) process, and a typical implementation thereof includes: firstly, forming a pseudo gate structure on a semiconductor substrate, wherein the pseudo gate structure is composed of an interface layer, a high-k dielectric layer, a covering layer and a pseudo gate electrode layer from bottom to top; then, forming gate gap wall structures at two sides of the dummy gate structure, removing the dummy gate electrode layer in the dummy gate structure, and leaving a groove between the gate gap wall structures; then, sequentially depositing a work function metal layer (work function metal layer), a barrier layer (barrier layer), a wetting layer (wetting layer) and the like in the groove; and finally, filling a metal gate material to form a metal gate structure on the covering layer. However, the yield loss of the transistor formed by the gate-last process is severe.
Therefore, in order to solve the above problems, it is necessary to provide a new method for manufacturing a semiconductor device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a first dummy gate structure is formed on the semiconductor substrate of the first region, and the first dummy gate structure comprises a first dummy gate electrode layer;
performing ion implantation to modify the first dummy gate electrode layer;
and removing the first dummy gate electrode layer by using a dry etching process to form a first groove, wherein the side wall of the first groove is vertical to the bottom.
Illustratively, the implantation source of the ion implantation includes As, P and/or B.
Illustratively, after the step of performing the ion implantation, a step of performing a thermal annealing process is further included.
Illustratively, the thermal annealing process is laser annealing and/or spike annealing.
Illustratively, the semiconductor substrate further comprises a second region, a second dummy gate structure is formed on the semiconductor substrate of the second region, the second dummy gate structure comprises a second dummy gate electrode layer, wherein the first region is a PMOS region, and the second region is an NMOS region; the object of the ion implantation includes the first dummy gate electrode layer and the second dummy gate electrode layer.
Illustratively, gapped walls are formed on sidewalls of the first dummy gate structure and the second dummy gate structure.
Illustratively, the material of the first dummy gate electrode layer includes polysilicon.
Illustratively, after the step of removing the first dummy gate electrode layer, the method further comprises the step of removing the second dummy gate electrode layer to form a second trench, wherein the side wall of the second trench is vertical to the bottom.
Illustratively, the method further comprises: and forming a metal gate in the first groove and the second groove.
According to the manufacturing method of the semiconductor device, the side wall of the groove formed after the pseudo gate electrode layer is removed is vertical to the bottom, so that the corner effect caused by the inclined side wall is avoided, and the yield of the semiconductor device is improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
fig. 1 is a process flow diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2A-2F are schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
In order to provide a thorough understanding of the present invention, a detailed structure will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
The "gate last" process is one of the major processes for forming high-K metal gate transistors. The typical implementation process comprises the following steps: firstly, forming a pseudo gate structure on a semiconductor substrate, wherein the pseudo gate structure is composed of an interface layer, a high-k dielectric layer, a covering layer and a pseudo gate electrode layer from bottom to top; then, forming gate gap wall structures at two sides of the dummy gate structure, removing the dummy gate electrode layer in the dummy gate structure, and leaving a groove between the gate gap wall structures; and finally, filling a metal gate material to form a metal gate structure on the covering layer. However, the yield loss of the transistor formed by the gate-last process is severe. PFA chip failure analysis shows that in the prior art, the etching strength of dry etching is too strong to damage a low-layer high-K dielectric layer and the like, so that the etching strength is generally reduced, the deeper the etching depth is, the weaker the etching capability is, the dummy gate electrode layer below the trench cannot be completely removed, and the side wall of the trench formed after the dummy gate electrode layer is removed is inclined. When the barrier layer is formed later, the inclined sidewall causes a corner effect (the corner effect refers to a phenomenon that when the corner of the trench is an acute angle, the material formed in the trench cannot completely fill the corner), so that the barrier layer cannot be formed at the corner of the trench, and the material of the metal gate is diffused to the active region, thereby causing the chip to fail.
In view of the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a first dummy gate structure is formed on the semiconductor substrate of the first region, and the first dummy gate structure comprises a first dummy gate electrode layer;
performing ion implantation to modify the first dummy gate electrode layer;
and removing the first dummy gate electrode layer by using a dry etching process to form a first groove, wherein the side wall of the first groove is vertical to the bottom.
The implantation source of the ion implantation comprises As, P and/or B.
After the step of performing the ion implantation, a step of performing a thermal annealing process is further included. The thermal annealing process is laser annealing and/or peak annealing.
The semiconductor substrate further comprises a second region, a second dummy gate structure is formed on the semiconductor substrate of the second region, the second dummy gate structure comprises a second dummy gate electrode layer, the first region is a PMOS region, and the second region is an NMOS region;
the object of the ion implantation includes the first dummy gate electrode layer and the second dummy gate electrode layer.
Gapped walls are formed on the side walls of the first and second dummy gate structures.
The material of the first dummy gate electrode layer comprises polysilicon.
And after the step of removing the first dummy gate electrode layer, the method further comprises the step of removing the second dummy gate electrode layer to form a second groove, wherein the side wall of the second groove is vertical to the bottom.
The method further comprises the following steps: and forming a metal gate in the first groove and the second groove.
According to the manufacturing method of the semiconductor device, the side wall of the groove formed after the pseudo gate electrode layer is removed is vertical to the bottom, so that the corner effect caused by the inclined side wall is avoided, and the yield of the semiconductor device is improved.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
[ exemplary embodiments ]
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to fig. 1 and fig. 2A to 2F.
Firstly, step 101 is executed, and a semiconductor substrate is provided, wherein the semiconductor substrate comprises a first region, a first dummy gate structure is formed on the semiconductor substrate of the first region, and the first dummy gate structure comprises a first dummy gate electrode layer. In the present embodiment, as shown in fig. 2A, a semiconductor substrate 200 is provided, the semiconductor substrate includes a first region 201 and a second region 202, and a first dummy gate structure and a second dummy gate structure are respectively formed on the semiconductor substrate 200 of the first region 201 and the second region 202. The first dummy gate structure includes a gate dielectric layer and a first dummy gate electrode layer 206a stacked from bottom to top, and the first dummy gate structure includes a gate dielectric layer and a second dummy gate electrode layer 206b stacked from bottom to top. In this embodiment, the first region 201 is a PMOS region, and the second region 202 is an NMOS region. It is to be noted that the first region 201 and the second region 202 are adjacent in the direction in which the gate extends.
Specifically, the constituent material of the semiconductor substrate 200 may be undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stack (SSOI), silicon-on-insulator germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is monocrystalline silicon. An isolation structure 203 is formed in the semiconductor substrate 200, and the isolation structure 203 is, for example, a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. In the present embodiment, the isolation structure 203 is a shallow trench isolation structure that divides the semiconductor substrate 200 into an NMOS region and a PMOS region. Various well structures are also formed in the semiconductor substrate 200, and are omitted from the drawing for simplicity.
In the present embodiment, a first dummy gate structure is formed on the semiconductor substrate 200 of the first region 201, and a second dummy gate structure is formed on the semiconductor substrate 200 of the second region 202, the first dummy gate structure including, as an example, the gate dielectric layer 204, the capping layer 205, and the first dummy gate electrode layer 206a stacked from bottom to top, and the second dummy gate structure including the gate dielectric layer 204, the capping layer 205, and the second dummy gate electrode layer 206b stacked from bottom to top. The gate dielectric layer 204 is preferably a high-k dielectric layer, and has a k value (dielectric constant) of usually 3.9 or more, and is made of a material such as hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, and particularly preferably hafnium oxide, zirconium oxide, or aluminum oxide; the capping layer 205 is made of a material including titanium nitride or tantalum nitride, and functions to prevent diffusion of a metal material in a subsequently formed workfunction setting metal layer into the high-k dielectric layer 204; the material of the first dummy gate electrode layer 206a and the second dummy gate electrode layer 206b includes polysilicon, silicon nitride, or amorphous carbon, and is preferably polysilicon.
Further, as an example, sidewall structures 207 are formed at both sides of the first and second dummy gate structures. In one embodiment, the sidewall structure 207 comprises at least an oxide layer and a nitride layer.
An embedded silicon germanium layer 208 is formed in the semiconductor substrate 200 of the PMOS region 201 on both sides of the dummy gate structure, and the forming process generally comprises the following steps: forming sigma-shaped grooves in the PMOS area 201 on two sides of the pseudo gate structure by adopting a process of firstly performing dry etching and then performing wet etching; the embedded sige layer 208 is formed to completely fill the sigma-shaped trench using a selective epitaxial growth process, which may employ one of Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE), and the formed embedded sige layer 208 may be doped with boron. The process of firstly performing dry etching and then performing wet etching comprises the following specific steps: firstly, longitudinally etching the semiconductor substrate of the PMOS regions at two sides of the pseudo gate structure by adopting a dry etching process to form a groove; continuously etching the groove by adopting an isotropic dry etching process, and forming an oval groove below the groove to form a bowl-shaped groove; and finally, expanding and etching the bowl-shaped groove by adopting a wet etching process to form the sigma-shaped groove, wherein the temperature of the wet etching is 30-60 ℃, the time is determined according to the expected size of the sigma-shaped groove and is generally 100-300s, and in the embodiment, a tetramethylammonium hydroxide (TMAH) solution is adopted as an etching solution of the wet etching.
A salicide 209 is formed on top of the embedded silicon germanium layer 208 and on the source/drain regions of the NMOS region 202. The process of forming the salicide is well known to those skilled in the art and will not be described herein.
After the salicide 209 is formed, an etch stop layer 210 completely covering the first and second dummy gate structures is formed on the semiconductor substrate 200, and an interlayer dielectric layer 211 covering the etch stop layer 210 is formed. The material of the contact hole etch stop layer 210 is preferably silicon nitride, and the material of the interlayer dielectric layer 211 may be a silicon oxide layer, including a doped or undoped silicon oxide layer formed by a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In addition, the interlayer dielectric layer 211 may be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, tetraethoxysilane (BTEOS) doped with boron, or the like.
Next, as shown in fig. 2B, a first planarization process is performed on the interlayer dielectric layer 211 to expose the etch stop layer 210. The first planarization process includes a planarization method, such as a Chemical Mechanical Polishing (CMP) process, which is conventional in the semiconductor manufacturing field.
Next, as shown in fig. 2C, a second planarization process is performed on the interlayer dielectric layer 211 and the etch stop layer 210 to expose the dummy gate electrode layer. The second planarization process includes a planarization method, such as a Chemical Mechanical Polishing (CMP) process, which is conventional in the semiconductor manufacturing field.
Next, step 102 is performed, as shown in fig. 2D, ion implantation is performed to modify the first dummy gate electrode layer 206 a. Preferably, the object of the ion implantation includes the first dummy gate electrode layer 206a and the second dummy gate electrode layer 206B, and the implantation source of the ion implantation includes As, P, B, and the like. The ion implantation process can modify the pseudo gate electrode layer, improve the stability of the etching rate of the pseudo gate electrode layer in the subsequent etching step, and avoid the situation that the pseudo gate electrode layer at the bottom cannot be removed, so that the side wall of the formed groove is vertical to the bottom.
In the present embodiment, after the ion implantation process is performed, a thermal annealing process is performed to activate the dopant ions. In one embodiment, the annealing process is a peak annealing process (spike anneal) that uses an annealing temperature of, for example, 850 ℃ to 1150 ℃. In another embodiment, the annealing process is a laser annealing process (laser annealing), the temperature of the laser annealing process is accurately controlled, the position of an annealing region is accurately positioned, and the annealing time is short. Illustratively, the laser annealing process employs an annealing temperature greater than 800 ℃. The adoption of a peak annealing process or a laser annealing process to replace furnace tube annealing can reduce the influence of the high temperature of the thermal annealing process on the semiconductor device.
Next, step 103 is performed, and the first dummy gate electrode layer is removed by using a dry etching process to form a first trench, where a sidewall of the first trench is perpendicular to a bottom of the first trench. In this embodiment, first, as shown in fig. 2E, a mask layer 212 covering the NMOS region 201 is formed. Illustratively, the mask layer 212 is a photoresist layer. Illustratively, a photoresist layer is first coated, and exposure, development, etc. are performed to obtain the photoresist layer 212 covering only the NMOS region 202.
Next, as shown in fig. 2F, a dry etching process is performed to remove the first dummy gate electrode layer 206a, so as to form a first trench, where a sidewall of the first trench is perpendicular to a bottom of the first trench. In this embodiment, the dummy gate electrode layer is modified by ion implantation, so that the etching rate in the etching step is stable, and the sidewall of the formed first trench is perpendicular to the bottom thereof. In this embodiment, the first dummy gate electrode layer 206a is removed by using a dry etching process, which has a higher directionality and causes less damage to the spacer 206, thereby contributing to improving the flatness of the sidewall of the trench and improving the quality of the metal gate formed in the trench subsequently.
After the first trench is formed, a step of removing the second dummy gate electrode layer 206b of the second region 202 to form a second trench is further included. Since the trench sidewall of the first region 201 is perpendicular to the bottom and the sidewall of the second region 202 adjacent to the trench sidewall is also perpendicular to the bottom, no corner effect, i.e. no barrier layer missing at the corner of the inclined sidewall, occurs when the barrier layer is formed subsequently. The barrier layer is a layer having a barrier effect on a material of the metal gate, and may be a work function layer or the like. The first and second trenches may be subsequently filled with a metal material to form a metal gate. Since the barrier layer is not missing at the trench corners, the metal material does not diffuse at the trench corners. As an example, the material of the metal gate material layer includes tungsten, aluminum, or the like. The metal gate may further include a plurality of stacked layers of work function layers, barrier layers, and the like. The method for forming the metal gate comprises the steps of depositing a metal gate material layer by using an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process and the like, and then performing a planarization process, such as a chemical mechanical polishing process, on the surface of the device until the dielectric layer is exposed.
Thus, the description of the steps related to the method of manufacturing a semiconductor device of the embodiment of the present invention is completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above-described steps but also other necessary steps before, during or after the above-described steps, which are included in the scope of the manufacturing method of the present embodiment.
According to the manufacturing method of the semiconductor device, the side wall of the groove formed after the pseudo gate electrode layer is removed is vertical to the bottom, so that the corner effect caused by the inclined side wall is avoided, and the yield of the semiconductor device is improved.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a first dummy gate structure is formed on the semiconductor substrate of the first region, and the first dummy gate structure comprises a first dummy gate electrode layer;
sequentially performing ion implantation and thermal annealing processes to modify the first dummy gate electrode layer;
removing the first pseudo gate electrode layer by using a dry etching process to form a first groove, wherein the side wall of the first groove is vertical to the bottom;
and forming a metal gate in the first groove.
2. The method of manufacturing according to claim 1, wherein the implantation source of the ion implantation comprises As, P and/or B.
3. The manufacturing method according to claim 1, characterized in that the thermal annealing process is laser annealing and/or spike annealing.
4. The manufacturing method according to claim 1, wherein the semiconductor substrate further comprises a second region, a second dummy gate structure is formed on the semiconductor substrate of the second region, the second dummy gate structure comprises a second dummy gate electrode layer, wherein the first region is a PMOS region, and the second region is an NMOS region; the object of the ion implantation includes the first dummy gate electrode layer and the second dummy gate electrode layer.
5. The method of manufacturing according to claim 4, wherein a spacer is formed on sidewalls of the first dummy gate structure and the second dummy gate structure.
6. The manufacturing method according to claim 1, wherein a material of the first dummy gate electrode layer includes polysilicon.
7. The manufacturing method according to claim 4, further comprising a step of removing the second dummy gate electrode layer to form a second trench after the step of removing the first dummy gate electrode layer, wherein a sidewall of the second trench is perpendicular to a bottom.
8. The manufacturing method according to claim 7, further comprising: and forming a metal gate in the second groove.
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| CN105632908A (en) * | 2014-11-06 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure forming method |
| CN105826176A (en) * | 2015-01-06 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| CN105990113A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
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