CN101673676A - 半导体元件的制造方法 - Google Patents

半导体元件的制造方法 Download PDF

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CN101673676A
CN101673676A CN200910163899A CN200910163899A CN101673676A CN 101673676 A CN101673676 A CN 101673676A CN 200910163899 A CN200910163899 A CN 200910163899A CN 200910163899 A CN200910163899 A CN 200910163899A CN 101673676 A CN101673676 A CN 101673676A
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semiconductor element
manufacture method
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廖舜章
钟昇镇
郑光茗
庄学理
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种含高介电常数金属栅极结构的半导体元件的制造方法。提供一包含虚置栅极结构(例如牺牲多晶硅栅极)的基材，一第一及第二硬掩模层位于此虚置栅极结构上方。在一实施例中，一应变区形成在此基材上。在形成此应变区之后，移除此第二硬掩模层。形成一源/漏极区，接着在此基材上形成一层间介电层(ILD)。在进行一化学机械研磨(CMP)工艺平坦化此层间介电层时，可用此第一硬掩模层作为停止层。此化学机械研磨工艺可持续进行以移除此第一硬掩模层。移除此虚置栅极结构并形成一金属栅极。本方法也可防止硅化物形成在虚置栅极结构上(例如在牺牲多晶硅上)。并且，本方法以硬掩模层作为化学机械研磨(CMP)工艺在平坦化层间介电层时的良好的停止层。

Description

半导体元件的制造方法
技术领域
本发明涉及一种IC电路元件，且特别涉及一种高介电常数金属栅极结构及一种IC电路元件的形成方法。
背景技术
随着集成电路尺寸不断的减小，半导体工业已试着使用许多方法来满足其需求。其中一种方法即为使用高介电常数材料作为栅极电极。高介电常数栅极介电质为包含介电常数较传统栅极介电质(例如二氧化硅)高的介电材料。高介电常数栅极介电质可在相似的等效氧化层厚度(EOT)下提供一较厚的栅极介电层(例如相对于二氧化硅)。此较厚的介电层可加强可靠度及有较低的漏电流(1eakage currents)。在半导体制造的最近趋势为使用金属栅极技术。金属栅极的电阻可低于传统多晶硅栅极，且可与位于其下方的高介电常数介电质相容。
然而，使用高介电常数介电质加上金属栅极结构的工艺面临了挑战。“后栅极”(gate last)工艺的发展可用于减少最后栅极结构损坏的风险，例如在高温工艺中形成栅极堆叠。一后栅极工艺包含在基材上形成虚置栅极结构(dummy gate structure)，此虚置栅极结构包含可被金属栅极结构替换的牺牲栅极结构。然而，仍然有许多问题存在于后栅极工艺中，例如关于在栅极之间的化学机械研磨(CMP)工艺及层间介电层(ILD)的沉积(例如减少空洞)。
因此，业界需要的是一形成栅极结构的改良方法。
发明内容
在一实施例中，本发明提供一种半导体元件的制造方法，包含：提供一基材，其上设置有一虚置栅极结构(dummy gate structure)；形成一硬掩模层于该虚置栅极结构上；沉积一介电层；平坦化该介电层并使用该硬掩模层作为一停止层；及移除该硬掩模层。
在另一实施例中，本发明提供一种半导体元件的制造方法，包含：提供一基材，其上设置有一虚置栅极结构；形成一第一及一第二硬掩模层于该虚置栅极结构上；形成一应变区(strained region)于该虚置栅极结构旁；在形成该应变区后移除该第二掩模层；在移除该第二掩模层后，于该应变区中形成一源极及一漏极区；沉积一介电层；及使用该第一硬掩模层作为一停止层来移除至少一部分该介电层。
在一实施例中，本发明提供一种半导体元件的制造方法，包括：形成一牺牲多晶硅栅极于一基材上，其中在该基材上形成该牺牲多晶硅栅极包含使用一第一及一第二硬掩模层至少其一来图案化该牺牲多晶硅层；形成一源极及一漏极区于该牺牲多晶硅栅极旁；形成一接触点于该源极及该漏极区上，其中该接触点的形成包含使用该第一及该第二硬掩模层至少其一来防止硅化物形成在该牺牲多晶硅栅极上。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1为一实施例的流程图，用以说明形成一栅极结构的方法。
图2～图9为一系列与图1的流程步骤相对应的半导体元件剖面图。
【附图标记说明】
202～基材；204～浅沟槽隔离(STI)结构；206～第一元件区域；208～第二元件区域；210～虚置栅极结构；212～第一硬掩模层；214～第二硬掩模层；302～虚置间隔元件；306～应变区；400～栅极结构；502～间隔物；504～含P型掺质的源/漏极区；506～含N型掺质的源/漏极区；602～接触点；702～层间介电层；902～沟槽。
具体实施方式
以下将先说明在一基材上形成半导体元件的工艺，且特别是有关于形成栅极结构的说明。在本说明书的各种例子中可能会出现重复的元件符号以便简化描述，但这不代表在各个实施例及/或图示之间有何特定的关联。再者，当提到某一层在另一层“之上”或“上方”，可代表两层之间直接接触或中间还插有其他元件或膜层。
图1显示本发明提供一实施例形成栅极电极的方法100。图2至图9为依照图1的制造步骤相对应的工艺剖面示意图。方法100可包含部分或完整的集成电路的工艺，包含静态随机存取存储器(Static Random Access Memory；SRAM)及/或其他逻辑电路、无源元件例如电阻、电容及电感(inductor)，及有源元件例如P通道场效应晶体管(P-channel field effect transistor；PFET)、N通道场效应晶体管(N-channel field effect transistor；NFET)，金属氧化物半导体场效应晶体管(MOSFET)、互补型金属氧化物半导体场效应(CMOS)晶体管、双极晶体管(bipolar transistors)、高功率晶体管(high voltage transistor)、高频晶体管(high frequency transistors)、其他记忆胞(memory cells)或其他合适的元件。本方法100包含一后栅极(gate last)工艺用以制造高介电常数金属栅极结构。
本方法100的起始步骤102为提供一基材例如晶片。此基材包含一虚置栅极结构形成于其上。第一及第二硬掩模层形成在此虚置栅极结构上。此虚置栅极结构可为在一后栅极(金属栅极)工艺中所形成的牺牲多晶硅栅极结构。在一实施例中，此第一硬掩模层包含氮化硅。在一实施例中，此第二硬掩模层包含一氧化物(例如氧化硅)。此第一及/或第二硬掩模层可在形成虚置栅极结构时作为掩模的元件(例如图案化)。例如，可沉积一多晶硅层，然后形成第一硬掩模层及第二硬掩模层于此多晶硅层上。可通过像是旋转涂布光致抗蚀剂、图案化此光致抗蚀剂、蚀刻此光致抗蚀剂以提供图案、使用此光致抗蚀剂图案作为掩模来图案化此第一硬掩模层及/或第二硬掩模层(例如蚀刻或其他合适处理方式)。
图2显示提供一基材202。在一实施例中，此基材202包含一晶体结构的硅基材(例如晶片)。此基材202可包含各种公知且依照需求设计配置的掺质(dopant)，例如p型基材或n型基材。在另一些实施例中，此基材202可包含其他元素半导体例如锗及钻石。或者，此基材202可包含化合物半导体例如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)或磷化铟(InP)。此外，此基材202可包含一外延层(epitaxial layer；epi layer)，其可通过应变效应以增进效能，及/或包含绝缘层上覆硅(Silicon on Insulator；SOI)结构。此基材202包含多个隔离区域，例如浅沟槽隔离(STI)结构204。此浅沟槽隔离(STI)结构204定义出第一元件区域206及第二元件区域208。浅沟槽隔离(STI)结构204可包含氧化硅、氮化硅、氮氧化硅、含氟掺杂硅玻璃(FSG)及/或一低介电常数材料。除了浅沟槽隔离(STI)之外，其他的隔离方法及/或元件也可适用。此浅沟槽隔离结构204可使用像是反应式离子蚀刻(reactiveion etch；RIE)的工艺形成沟槽，接着将此沟槽填满介电材料然后进行化学机械研磨(CMP)工艺。
在一实施例中，此第一元件区域206包含一PMOS元件区域及此第二元件区域包含一NMOS元件区域，不过有可能是任何结构。虚置栅极结构210设置在基材202上。此虚置栅极结构210可包含多晶硅。此虚置栅极结构210可使用像是沉积、光刻技术(photolithography)(例如使用光致抗蚀剂图案化)、蚀刻及/或其他合适工艺来形成。此虚置栅极结构210可通过使用硬掩模层212及/或214作为掩模元件来形成(例如图案化)。
多个膜层可位于虚置栅极结构210的下方，包含像是界面层、栅极介电层、盖层及/或其他合适的膜层。界面层可包含硅、氧及/或氮。在一实施例中，此界面层为二氧化硅。界面层可用原子层沉积(ALD)或其他合适的工艺形成。栅极介电层包含一高介电常数材料。在一实施例中，此高介电常数介电材料包含氧化铪(HfO2)。在其他例子中，此高介电常数介电质包含HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或前述之组合，及/或其他合适的材料。一盖层可形成在此栅极介电层上。此盖层可包含一金属氧化物层，例如La2O3、DyO、Al2O3及/或其他合适材料。在一实施例中，盖层可对随后形成的金属栅极的功函数造成影响。
图2显示第一硬掩模层212及第二硬掩模层214设置在虚置栅极结构210上。在一实施例中，此第一硬掩模层212包含氮化硅。在一实施例中，此第二硬掩模层214包含一氧化物。
步骤104为在基材中形成一应变区(strained region)。此应变区可增加基材中电子或空穴的迁移率。因此，可增进与此应变区相连的元件的效能。在一实施例中，一应变区形成在一元件(例如一PMOS元件)的源/漏极区中。此应变区可包含锗化硅(SiGe)区。此锗化硅区可用外延成长工艺来形成。此应变区可邻近虚置栅极且与其间隔一段距离。虚置间隔元件可用于控制此应变区的位置。
图3显示虚置间隔元件302形成在基材202上。虚置间隔元件及掩模层304可保护此元件区域208。此掩模层304可与虚置间隔元件302同时形成且大抵与虚置间隔元件302相同。虚置间隔元件302可形成在此包含虚置栅极结构210(及下方膜层)的栅极结构的两侧。此虚置元件302可由氧化硅、氮化硅、氮氧化硅、碳化硅、氟掺杂玻璃(FSG)、低介电常数材料或前述的组合，及/或其他合适材料形成。虚置间隔元件302可拥有一多层结构，例如包含一或多个衬层(liner layers)。这些衬层可包含一介电材料，像是二氧化硅、氮化硅及/或其他合适材料。虚置间隔元件302的形成方法包含沉积适当的介电材料及对此材料做一非等向性蚀刻以形成虚置间隔元件302的轮廓。
应变区306为形成在基材202中(例如在基材中没有被掩模层304及虚置间隔元件302遮盖的区域)。此应变区306包含锗化硅，例如外延的锗化硅。以图3所示为例，虚置隔离元件302确保了应变区306与虚置栅极结构210的隔离；此应变区306大抵沿着此虚置隔离元件的边缘对齐。在一实施例中，此应变区306提供一应变区让第一区域206中的一PMOS元件的源/漏极可在此形成。可牺牲此虚置间隔元件302(例如在应变区306成长后将其移除)。
步骤106接着为移除一掩模层，例如从基材中移除在步骤102形成的第二硬掩模层。在一实施例中，可移除一包含氧化物的硬掩模层。可用湿蚀刻工艺或干蚀刻工艺(例如RIE，等离子体蚀刻)及/或其他合适工艺将此硬掩模层移除。图4显示将图3中虚置间隔元件302(及掩模层304)移除后的结构。第二硬掩模层214也已被移除。栅极结构400包含此虚置栅极结构210及硬掩模层212。因此，此栅极结构400可包含一缩减的高度(相对于图2及图3所描述的栅极结构，包含虚置栅极结构210、硬掩模层212及硬掩模层214)。
步骤108为形成源极及漏极区。可依照晶体管结构的需求来注入P型或N型的掺质或杂质进入基材中以形成此源/漏极区。此源/漏极元件可使用包括光刻技术(photolithography)、离子注入、扩散及/或其他合适工艺形成。步骤108可包含下列所述的一或多个工艺。
步骤108可起始于形成轻掺杂漏极(low dose drain；LDD)区。此轻掺杂漏极区可通过注入掺质进入邻近于栅极结构的基材中来形成。依方法100所制造的栅极结构，其高度在此可为一缩减后的高度。此缩减后的高度可减少进行轻掺杂漏极(LDD)注入时的遮影效应(shadow effect)。
进行轻掺杂漏极(LDD)注入之后，步骤108可包含形成间隔元件。此间隔元件可形成在虚置栅极结构的两侧且遮盖基材中的轻掺杂漏极部分。在此间隔物形成后，可进行源极及漏极的注入。此源极及漏极的形成可包含使用一种或多种的掺质进行离子注入，例如使用硼、磷及/或其他合适的掺质。
图5显示间隔物502可在进行轻掺杂漏极(LDD)注入之后(如果有)形成于基材上。此间隔物502可形成在此包含虚置栅极结构210(及下方膜层)的栅极结构的两侧。此间隔物可由氧化硅、氮化硅、碳化硅、氟掺杂硅玻璃(FSG)、低介电常数材料或前述的组合及/或其他合适材料形成。此间隔物502可拥有一多层结构，例如包含一或多个衬层。这些衬层可包含一介电材料，例如氧化硅、氮化硅及/或其他合适材料。间隔物502的形成方法包含沉积适当的介电材料及对此材料做一非等向性蚀刻以形成间隔物502的轮廓。漏/源极区504/506(例如源/漏极注入提供在基材中的掺杂区域)设置在基材202中，大抵对齐间隔物502。在PMOS元件中，此源/漏极区504可包含硼或其他合适的P型掺质。在NMOS元件中，此源/漏极区506可包含磷、砷或其他合适的N型掺质。值得注意的是，此源/漏极区注入504与设置于基材中202的区域206中的一元件相关，且该元件至少部分位于应变区306中。
步骤108可包含形成设置在此源/漏极区上的接触元件。此接触点(contacts)可包含硅化镍(nickel silicide)、硅化钴(cobalt silicide)、硅化钨(tungsten silicide)、硅化钽(tantalum silicide)、硅化钛(titanium silicide)、硅化铂(platinum silicide)、硅化铒(erbium silicide)、硅化钯(palladium silicide)或前述的组合。依图6所示为例，接触点602为设置在此基材上并且与漏/源极区504/506相接触。在一实施例中，此接触点602包含硅化镍。可通过一自对准硅化(salicide)工艺使此接触点602形成在源/漏极区域504及/或506上。硬掩模层212可防止硅化物形成在虚置栅极结构210上。
步骤110为在基材上形成层间介电层(ILD)。可用层间介电层材料进行沉积以形成一覆盖层。化学机械研磨(CMP)工艺可用于平坦化此层间介电层。在一实施例中，第一硬掩模层(在图2中所述)可用于作为此CMP工艺的停止层。图7为显示为层间介电层702的形成。此介电层702可用可由化学气相沉积(CVD)、高密度等离子体CVD、旋涂(spin-on)、溅镀(sputtering)或其他合适方法形成。此介电层可包含氧化硅、氮氧化硅或一低介电常数材料。在一实施例中，此介电层702为一高密度等离子体(high density plasma；HDP)介电质。硬掩模层212可用于作为化学机械研磨(CMP)工艺的停止层以提供此介电层702。在一实施例中，此硬掩模层212包含氮化硅。值得注意的是栅极结构400包含虚置栅极结构212及硬掩模层212，而此栅极结构的高度可降低两个栅极结构之间的开口的深宽比(例如在基材202中，区域206的栅极与区域208的栅极之间的间隙)。因此，可使介电层702填充间隙的效果较佳(例如减少空洞)。
步骤112为移除第一硬掩模层。在一实施例中，可继续使用如步骤110所述的化学机械研磨(CMP)工艺将第一硬掩模层移除(过研磨(over-polish)步骤)。以图8所示为例，部分的介电层702被移除后，此介电层702与虚置栅极结构210共平面。第一硬掩模层已被移除。
步骤114为形成一金属栅极结构。如步骤102所述的虚置栅极结构将从基材上移除。此虚置栅极结构可用湿蚀刻、干蚀刻(例如RIE、等离子体蚀刻)及/或其他合适工艺来移除。图9所显示为移除虚置栅极结构210而留下沟槽902。金属栅极可形成在此沟槽902中。
此金属栅极可包含一层或多层，包含钛、氮化钛(TiN)、氮化钽(TaN)、钽、碳化钽(TaC)、氮硅化钽(TaSiN)、钨、氮化钨(WN)、氮化钼(MoN)、氮氧化钼(MoON)、氧化钌(RuO2)或前述的组合。此栅极可包含一或多层，可由物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)、电镀(plating)及/或其他合适工艺形成。在一些实施例中，此金属材料可包含沉积P型金属材料及N型金属材料。P型金属材料成分可包含例如钌、钯、铂、钴、镍、导电金属氧化物及/或其他合适材料。N型金属材料成分包含例如铪、锆、钛、钽、铝、金属碳化物(例如碳化铪、碳化锆、碳化铪、碳化钛、碳化铝)、铝化物(aluminide)及/或其他合适材料。在一实施例中，一金属栅极形成在基材202中区域208的沟槽902内并包含N型金属。在一实施例中，一金属栅极形成在基材202中区域206的沟槽902内并包含P型金属。除了功函数金属之外亦可沉积其他材料例如填充金属，可包含氮化钛、钨、钛、铝、钽、氮化钽、钴、铜、镍及/或其他合适材料。此金属栅极可包含及/或位于盖层、栅极介电层、界面层及/或其他合适的膜层之上。
在一些实施例中，方法100可继续更进一步的工艺步骤，像是形成内连线、盖层及/或其他合适的元件。
综上所述，本发明提供了使用后栅极工艺制造金属栅极结构的方法。本方法使用虚置栅极结构使层间介电层对间隙的填充效果较佳。此虚置栅极堆叠也包含一高度用以防止在进行注入工艺(例如轻掺杂漏极；LDD)的遮影效应(shadow effect)。本方法也可防止硅化物形成在虚置栅极结构上(例如在牺牲多晶硅上)。硅化物的成长可能会使化学机械研磨(CMP)在平坦化层间介电层时造成问题。最后，本方法以硬掩模层作为化学机械研磨(CMP)工艺在平坦化层间介电层时的良好的停止层。
虽然本发明已以数个优选实施如上，然其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视后附的权利要求所界定的范围为准。

Claims (15)

1.一种半导体元件的制造方法，包含：
提供一基材，其上设置有一虚置栅极结构；
形成一硬掩模层于该虚置栅极结构上；
沉积一介电层；
平坦化该介电层并使用该硬掩模层作为一停止层；及
移除该硬掩模层。
2.如权利要求1所述的半导体元件的制造方法，还包含：
移除该虚置栅极以形成一沟槽；及
在该沟槽中形成一金属栅极电极。
3.如权利要求1所述的半导体元件的制造方法，其中该硬掩模层的形成包含形成一氮化硅层。
4.如权利要求1所述的半导体元件的制造方法，还包含：
在该硬掩模层上形成一氧化物掩模层。
5.如权利要求4所述的半导体元件的制造方法，还包含：
在该基材上形成一应变区接着移除该氧化物掩模层。
6.如权利要求1所述的半导体元件的制造方法，其中该硬掩模层的移除包含在平坦化该介电层时进行一过研磨步骤。
7.一种半导体元件的制造方法，包含：
提供一基材，其上设置有一虚置栅极结构；
形成一第一及一第二硬掩模层于该虚置栅极结构上；
形成一应变区于该虚置栅极结构旁；
在形成该应变区后移除该第二掩模层；
在移除该第二掩模层后，于该应变区中形成一源极及一漏极区；
沉积一介电层；及
使用该第一硬掩模层作为一停止层来移除至少一部分该介电层。
8.如权利要求7所述的半导体元件的制造方法，还包含继续该移除步骤超过该停止层以移除该第一掩模层。
9.如权利要求7所述的半导体元件的制造方法，其中该应变区的形成包含外延成长一锗化硅区。
10.如权利要求7所述的半导体元件的制造方法，还包含：
移除该虚置栅极结构及形成一金属栅极。
11.一种半导体元件的制造方法，包括：
形成一牺牲多晶硅栅极于一基材上，其中在该基材上形成该牺牲多晶硅栅极包含使用一第一及一第二硬掩模层至少其一来图案化该牺牲多晶硅层；
形成一源极及一漏极区于该牺牲多晶硅栅极旁；
形成一接触点于该源极及该漏极区上，其中该接触点的形成包含使用该第一及该第二硬掩模层至少其一来防止硅化物形成在该牺牲多晶硅栅极上。
12.如权利要求11所述的半导体元件的制造方法，还包含：
沉积一介电层于该牺牲多晶硅栅极上；及
使用该第一及该第二硬掩模层至少其一作为一停止层来移除至少一部分该介电层。
13.如权利要求11所述的半导体元件的制造方法，其中该第一硬掩模层包含氮化硅。
14.如权利要求11所述的半导体元件的制造方法，其中该第二硬掩模层包含一氧化物。
15.如权利要求11所述的半导体元件的制造方法，还包含：
继续移除该介电层并超过该停止层以移除该第一及该第二硬掩模层至少其一。
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